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The optimization of drift region specific ON-resistance (${R} _{on,sp}$) for superjunction (SJ) MOSFETs with three-dimensional (3-D) and insulator-pillar (${i}$ -pillar) concepts is proposed and compared with the two-dimensional conventional SJ (2-D C-SJ) MOSFETs. With the constraints of avalanche breakdown and critical depletion, the optimized ${R} _{on,sp}$ and the corresponding design parameters are numerically determined. For the 3-D concept, a superior ${R} _{on,sp}$ can be obtained only for a high breakdown voltage (BV) or a low pillar aspect-ratio (AR) due to the better charge compensation. The junction field-effect transistor (JFET) effect induced by the lateral pillars depletion exceeds the charge compensation due to the stronger electric field crowding effect. For the ${i}$ -pillar concept, parasite depletion is alleviated due to an additional voltage sustained across the insulator pillar, especially for a narrow SJ pillar. The optimization design for the 650-V class SJ MOSFETs with 3-D and ${i}$ -pillar concepts demonstrates an optimized ${R} _{on,sp}$ with 3.99 $\text{m}\Omega \cdot $ cm2 at AR = 10 and 1.40 $\text{m}\Omega \cdot $ cm2 at AR = 70 can be obtained in 3-D ${i}$ -pillar SJ (3-D I-SJ) and 2-D ${i}$ -pillar SJ (2-D I-SJ), respectively. For the 650-V class SJ MOSFETs, 3-D and 2-D I-SJ structures have a lowest ${R} _{on,sp}$ than the other structures for AR less and greater than 57, respectively. The charge imbalance effects of BV for these structures are also discussed. [ABSTRACT FROM AUTHOR]

In this article, a novel ${p}$ -GaN high-electron-mobility transistor (HEMT) with a built-in Schottky barrier diode (SBD) is proposed and investigated by TCAD simulation. The anode contact of the integrated SBD is isolated from the ohmic contact of the source electrode by a ${p}$ -GaN isolation region. The cathode of the SBD is connected to the drain electrode. In the proposed Schottky barrier diode/HEMT (SB-HEMT), a channel under the ${p}$ -GaN isolation region is turned on during forward conduction to further reduce the specific ON-resistance (${R}_{ {\text{ON}},\text {sp}}$). With a minimum sacrifice on ${R}_{ {\text{ON}},\text {sp}}$ , the reverse ON-state voltage, ${V}_{\text {R}- {\text{ON}}}$ (at a current density of 50 mA/mm), for the SB-HEMT is reduced by 33% (from 2.43 to 1.62 V) when compared with a conventional HEMT (C-HEMT). Compared with the C-HEMT with a separate on-chip SBD (C-HEMT/SBD), the SB-HEMT shows much better trade-off between ${V}_{\text {R}- {\text{ON}}}$ and ${R}_{ {\text{ON}},\text {sp}}$. The total switching loss (${E}_{\text {total}}$) of the proposed SB-HEMT with resistive load is lower than that of the C-HEMT and is reduced by up to 21% when compared with that of the C-HEMT/SBD with different area ratio between the HEMT and SBD regions. [ABSTRACT FROM AUTHOR]

An improved lateral power p-channel trench metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed. By using a technique of variation vertical doping (VVD), the threat of charge imbalance posted by the parasitic trench capacitance is eliminated. Moreover, a p-type VVD increases the number of carriers, and an n-type VVD intensifies the charge compensation effect. Hence, compared to the conventional device without VVD, the proposed device gets a significantly improved tradeoff relationship between the breakdown voltage (BV) and the specific ON-resistance (RON,SP). According to the simulation results, the proposed device using the triple piecewise VVD obtains a RON,SP of 10.6 mΩ ⋅ cm2 at a BV of 440 V, reaching a figure of merit (FOM = BV2/RON,SP) being 2.4 times larger than that of the prior art. [ABSTRACT FROM AUTHOR]

This article proposes a MATLAB-based optimization methodology of the drift region specific ON-resistance (${R}_{on,sp}$) both for the high-permittivity (Hk) MOSFETs and superjunction (SJ) MOSFETs with design parameters expressed by breakdown voltage (BV) and aspect ratio (AR). The optimized method has three distinctive features. First, based on the built-in functions in MATLAB, the proposed method is very efficient to accurately obtain the optimized Ron,sp (Ron,sp(opt)) and the design parameters for both MOSFETs. Second, as the reflection of the process difficulty in the Hk or SJ structure, AR is used as one of the design variables. Third, the cubic polynomial functions are used to obtain a more accurate fitting for the optimization. The optimized results demonstrate that for a given BV, the Ron,sp(opt) for the SJ MOSFET decreases as AR increases, whereas an optimum AR exists for a minimal Ron,sp(opt) for the Hk MOSFET. Extensive comparisons demonstrate that when AR is small and BV is large, the Ron,sp(opt) for the Hk MOSFET could be lower than that for the SJ MOSFET. Parameter designs are performed for the 900-V Hk MOSFET and SJ MOSFET. The impacts of important parameter variations on BV and Ron,sp are also discussed. The validity of the proposed optimization method is demonstrated by the TCAD simulations. [ABSTRACT FROM AUTHOR]

In this article, a novel reverse-conducting lateral insulated gate bipolar transistor (RC-LIGBT) with embedded diode and p-type Schottky Barrier Diode (p-SBD) is proposed. The two diodes are connected in series through a floating electrode, which provides a current path for carriers in reverse-conducting mode. Compared with the Separated Shorted-Anode RCLIGBT (SSA-RC-LIGBT), the proposed structure not only eliminates the snapback voltage (Δ VSB) but also avoids the waste of device area. Therefore, the superior reverse recovery characteristics and excellent tradeoff relationship between ON-state voltage (VON) and turn-off loss (EOFF) are obtained. The reverse recovery charge of the proposed RC-LIGBT shows 43.9% and 63.2% reduction compared with those of the SSA-RC-LIGBT with LB (distance between the p+ collector and the shorted n+ collector) being 34 and 64μm, respectively. The turn-off loss of the proposed RC-LIGBT at VON = 2.6 V is reduced by 68.2% and 87.1% compared with those of the SSA-RC-LIGBT with Δ VSB = 0.48 V and Δ VSB = 0.17 V, respectively. Moreover, the proposed RC-LIGBT has a self-adjusted collector injection efficiency under different temperatures to dramatically improve the Short Circuit Safe Operation Area (SCSOA). [ABSTRACT FROM AUTHOR]

A novel insulated gate bipolar transistor modulated by a high-k dielectric (HK-IGBT) is presented. By laterally alternating the HK-pillar and N-drift, HK-IGBT can offer a quick and complete depletion to the drift region during the turn-off transient. This merit greatly reduces the current varying time of an HK-IGBT. Moreover, HK-IGBT can obtain a better electric field distribution, which enables the carrier stored layer (CSL) to have a higher doping dose when compared to a typical carrier stored trench gate bipolar transistor (CSTBT). These advantages improve the relationship between the static and transient power losses. According to the simulation results, HK-IGBT obtains a 66% lower turn-off loss than that of a field stop (FS) IGBT with the same ON-state voltage. Moreover, by using a CSL, the performance of an HK-IGBT can be comparable with that of a super-junction IGBT (SJ-IGBT). [ABSTRACT FROM AUTHOR]

A new lateral power metal-oxide-semiconductor field-effect transistor (MOSFET) with dual conduction paths and high- ${k}$ passivation is proposed. The high- ${k}$ passivation enables the dual conduction paths to realize the double reduced surface field (RESURF) action and facilitates the formation of an accumulation layer during forward conduction. The proposed device offers a 42% reduction in specific on-resistance (${R}_{{ON},{SP}}{)}$ when compared to a similar size baseline device with the same breakdown voltage (BV). The technology computer-aided design (TCAD) simulation results, based on a $0.5~\mu \text{m}$ bipolar-CMOS-DMOS (BCD) compatible process, show that the proposed device is able to provide a ${R}_{{ON},{SP}}$ as low as 0.28 $\text{m}\Omega \cdot $ cm2 with a BV of 92 V. [ABSTRACT FROM AUTHOR]

In this article, a novel diode-clamped carrier stored trench IGBT (DC-CS-TIGBT) is proposed and investigated by the TCAD tool. Two series-connected diodes implemented on the surface of the IGBT is proposed to clamp the voltage potential of the carrier stored layer (CSL). Hence, the CSL can be heavily doped. A significant improvement in the tradeoff between ON-state voltage (VON) and turn-off loss (EOFF) can be achieved due to enhanced emitter injection. Moreover, due to the shielding effect on the voltage potential of the CSL, the saturation current is reduced by over 41% compared with that of the buried P-shield CS-TIGBT(PS-CS-TIGBT). Consequently, the withstand time of short-circuit is improved from 6.7 to 15~μs compared with that of the PS-CS-TIGBT. [ABSTRACT FROM AUTHOR]

An oppositely doped islands insulated gate bipolar transistor (ODI-IGBT) is investigated for the first time. By adding one or several ODIs in the drift longitudinally equidistantly, the ODI-IGBT obtains a better electric field distribution than the field-stop IGBT (FS-IGBT) at OFF-state, which means a larger breakdown voltage. Moreover, at inductive load turn off transient, its space charge region is wider along with the better electric field distribution. Hence, less excess carriers are left when the anode voltage rises to the bus voltage. That is, its current decaying time is smaller than FS-IGBT, so does the turn off loss. Compared with the FS-IGBT in TSUPREM4 simulation, the ODI-IGBT can achieve a much lower turn off loss, which is only 52% of that of the FS-IGBT at the same breakdown voltage and same ON-state voltage. In addition, the ODI-IGBT has a simpler manufacturing process and better immunity to process deviation than the super junction IGBT (SJ-IGBT). [ABSTRACT FROM AUTHOR]

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal (${V}_{\mathrm {\textsf {Gn}}}$). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor (${R}\text{p}$) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively. [ABSTRACT FROM AUTHOR]

In this letter, a p-channel lateral double-diffused MOSFET (p-LDMOS) with double electron paths used to enhance the current capability is proposed. The proposed p-LDMOS has two n-channels that are controlled by an auto-generated voltage signal (${V}_{\text {Gn}}$). The voltage signal ${V}_{\text {Gn}}$ is generated during the ON and OFF states of the hole current that flows across an integrated resistor ($R_{\text {p}}$) implemented in the P-base region. Thus, the current capability of the p-LDMOS can be significantly enhanced by the introduced electron current. The simulation results show that the current capability of the proposed p-LDMOS can be comparable to that of the n-type triple RESURF technique without any conductivity modulation effect. The power loss of the proposed p-LDMOS is reduced by approximately 78.6% and 15.6% compared with the triple RESURF p-LDMOS and n-LDMOS, respectively, at a rated load current density of $25~\mu \text{A}/\mu \text{m}$. [ABSTRACT FROM AUTHOR]

A new type of “quasi-p-lateral diffused metal oxide semiconductor” (quasi-p-LDMOS), in which electrons are used as conductive carriers in the drift region is proposed. A floating electrode F is used in the “quasi-p-LDMOS” to transform the hole current into electron current. Then, by using an integrated low-voltage power and an inverter to control the electron current automatically, the specific on-resistance (R on,sp) is significantly reduced and the device can be successfully turned on and off. Simulation results show that the Ron,sp is 12.77 and 31 mΩ·cm2 for a 349 and 630 V “quasi-p-LDMOS,” being only about 19.7% and 14.7% of a Triple-RESURF p-LDMOS, respectively. Moreover, the Ron,sp is even lower than that of a Triple-RESURF n-LDMOS at the same rated breakdown voltage. The figure of merit of the device is 3 to 7 times of that of state-of-the-arts. The “quasi-p-LDMOS” is designed as a low-side device in a new high-voltage CMOS circuit. By applying the “quasi-p-LDMOS” in the CMOS circuit, the total power loss is much lower than that of a conventional half-bridge circuit in a wide operating frequency. The “quasi-p-LDMOS” is suitable for smart power integrated circuit to improve both the integration level and system efficiency, and simplifies the circuit design. [ABSTRACT FROM PUBLISHER]

A trench insulated gate bipolar transistor (TIGBT) with floating n-well (FN) region is proposed. In the off-state, the n-well region, which is pinched off by its adjacent trenches, would almost have no effect on the breakdown voltage. In the turn-on transient, only a few holes could be attracted into the FN region, because it has a high barrier to holes. So the increase of the potential of the FN region is prevented, which suppresses the reverse displacement current that charges the gate capacitance significantly. As a result, the proposed TIGBT shows excellent controllability on the turn-on dVCE/dt, and hence, the reverse-recovery dVKA/dt of free-wheeling diode (FWD). The simulation results based on 1.2-kV TIGBT show that, in comparison with the TIGBT with floating P-base, the lower limit of the reverse-recovery dVKA/dt of FWD can be reduced by 85.7%. [ABSTRACT FROM AUTHOR]

An improved p-channel lateral double-diffused MOSFET (pLDMOS) with silicon-on-insulator substrate is proposed. On one hand, the improvement is attributed to a dielectric film with high permittivity (high-k), which is employed at the silicon surface to optimize the electric field distribution. Thus, the drift region dose could be increased, while its deviation has less influence on the breakdown voltage (BV). On the other hand, an additional pLDMOS is introduced to form another hole current path, which contributes to a decreased specific ON-resistance ( R\textsf {on,sp} ). The simulation results show that the proposed structure exhibits a BV of 366 V and an R\textsf {on,sp} of 24 \textm\Omega \cdot cm ^\textsf 2 , at a back gate bias of −200 V. Compared with the previous one, R\textsf {on,sp} is decreased by 39%, and the dose deviation window of the drift region for ensuring the breakdown voltage above 300 V is relaxed from ±2% to ±5%. [ABSTRACT FROM AUTHOR]

The structure of multilevel low-voltage power supplies with a self-clamped characteristic is proposed and experimentally demonstrated using a 0.5- \mu \textm BiCMOS process. The power supply can achieve two output voltages by its intrinsically integrated structure with the values of 25.0 and 13.6 V when the applied high voltage is 90 V and the two load resistances are both 30 \textk\Omega . The two output voltages also appear good stability. When the applied high voltage is changed from 90 to 150 V, its line regulation is 0.07%/V, and when the two load resistances vary within 30–100 \textk\Omega , its load regulation is 9.6%. The proposed power supply is able to be integrated with most high-voltage devices without passive components and additional processes, which makes it considerable in the applications of high-voltage integrated circuits. [ABSTRACT FROM PUBLISHER]

A novel trench insulated bipolar transistor (TIGBT) is proposed, where a p-layer beneath the trench gate is introduced to form a self-biased pMOS and provide an additional path for the hole current. In the on-state, the drain-to-source voltage of the trench nMOS is clamped, which helps to decrease the saturation current. In the blocking state, the reverse voltage is sustained by the junction of p-layer/n-drift, so that the n-layer sandwiched by the p-base region and the n-drift region can be as heavily doped as possible to reduce the on-state voltage without affecting the breakdown capability. The simulation results show that, in comparison with the conventional one, under the same breakdown voltage, the saturation current and the on-state voltage of the proposed TIGBT are decreased by 47% and 35%, respectively. [ABSTRACT FROM PUBLISHER]

A new planar junction edge termination technique, using the optimum variation lateral doping with a buried layer, is proposed and studied. A voltage equal to 100% of the breakdown voltage of a single-sided abrupt parallel-plane junction with the same substrate can be achieved within a smallest area on the surface. The proposed technique can be realized by a process compatible with conventional CMOS or BiCMOS technologies and verified by the results of numerical simulations. [ABSTRACT FROM PUBLISHER]

In the prior art of the optimum variation lateral doping (OPTVLD) technique, the dose deviations between designs and products should be tightly controlled to achieve the eligible breakdown voltages (BVs); however, an approach presented in this letter overcomes this shortcoming without any penalty. Its physical explanation is discussed, and the simulations show that, through using this approach, the allowed dose-deviation range is relaxed from about \pm1.5\% to about \pm5\%, which can significantly enhance the yield over the existing state of the art. As a result, at an artificial dose-deviation rate of \pm5 \%, the OPTVLD products with the high yield of 94.4 \% are first fabricated in the BiCMOS process, and the measured maximal BV of 1000 V corresponds very well to the ideal value of 1090 V. [ABSTRACT FROM AUTHOR]