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This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $\text{L}_{\text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.

In this work, we propose replacement metal contact (RMC) flow by using sacrificial ILD0 that is suitable for wrap around contact (WAC). RMC minimize erosion of gate plug, spacer and S/D area at scaled contact formation. The concept of the flow has been demonstrated in short loop flow with ~50% contact resistance improvement for both NMOS, Si:P and PMOS, SiGe:B.

This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, I on =500μA/μm at I off =100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si 0.3 Ge 0.7 SRB.

Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (L g =40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (L g =40nm) with DIBL of 30mV/V and sub-threshold slope (SS sat ) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.

Sub-30nm L G Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14–16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The I ON /I OFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible processing steps such as STI formation, replacement metal gate (RMG), in-situ Phosphorus-doped raised-Source/Drain and a Ni-based contact scheme have been successfully implemented. This first industry-compatible Ge n-FinFET has a G M,SAT,EXT / SS SAT of 250 µS.µm−1 / 130 mV.dec−1 (at the targeted V DS =0.5V) which is on par with accumulation-mode junction-less Ge n-FETs.

We present a comprehensive study of Si 0.55 Ge 0.45 -cladded p-channel FinFETs, including a comparison with planar SiGe quantum-well devices. The SiGe-cladded FinFETs exhibit ~2× higher hole mobility, ~2× better I ON /I OFF , and improved DIBL compared to Si control devices. Superior NBTI reliability over equivalent Si FinFETs is demonstrated for cladding thicknesses down to 3 nm. The dependencies of drive current and hole mobility on both SiGe thickness and device width are examined in detail. This analysis shows that SiGe thickness conformality and epitaxial facet control are crucial for the optimization of SiGe-cladded FinFETs.

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET INV -normalized G M,SAT,INT of 6.7 nm.mS/μm, the Si 0.3 Ge 0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

An analysis of dopant diffusion and defects in 3D Fin structure using an atomistic lattice kinetic Monte Carlo (KMC) approach are shown. Atomistic KMC simulations are compared with 3D methodology of Atom Probe Tomography (APT). Atomistic dopant distribution in 3D Fin structure is shown. KMC simulation shows that implant temperature has an impact on amorphization and residual defects and dopant-defect complexes are formed at top-of-Fin and edge-of-Fin-side after SPER.

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are reported for the first time, demonstrating peak transconductance gmSAT of 1.3mS/μm at VDS=-0.5V and good short channel control down to 60nm gate length. Optimization of P-doping in the SiGe, optimized Si cap passivation thickness on the Ge, and improved gate wrap of the channel all improve device characteristics. The Ge FinFETs presented in this work outperform published relaxed Ge FinFET devices for the gmSAT/SSSAT benchmarking metric.

Atomistic Kinetic Monte Carlo (KMC) diffusion modeling is used for dopant diffusion and defect analysis in ultra shallow junction formation in Si and SiGe. An analysis of dopant diffusion and defects in SiGe-channel Quantum Well (QW) using an atomistic KMC approach are shown. Thin SiGe layer with high Ge content for SiGe-channel QW has an impact on implantation damage and Boron-Transient Enhanced Diffusion (TED) suppression, and defect evolution. KMC shows that As-pocket in SiGe-channel pFET shows enhanced diffusion toward SiGe-channel and higher As concentration in SiGe-channel. The difference of pocket diffusion is one of possible reason for the higher Vth mismatch for SiGe-channel with As pocket than for Si-channel. To avoid implant damage influence, Implant-Free SiGe channel-QW with B-doped SiGe epi for extension-S/D formation is used. KMC simulation and SSRM shows that B migration from B-doped SiGe raised-S/D to SiGe-channel can form S/D-extension overlap.

An analysis of dopant diffusion and defects in SiGe-channel (SiGe-ch) Implant-Free Quantum Well (IFQW) using an atomistic KMC approach are shown. B-doped SiGe layer is used for S/D-extension formation. KMC and SSRM show that B migration from B-doped SiGe raised-S/D can form S/D-extension gate overlap. Arsenic Vt-adjustment implant before SiGe-ch formation instead of Arsenic pocket implant after SiGe-ch formation can reduce Arsenic concentration in channel region and shows better Vt-mismatch.

We propose a cell structure with monocrystalline floating gate and 6 nm to 8 nm of thermally grown SiO2 interpoly dielectric (IPD) for

A transient leakage current was measured as a function of time for thin (~9 nm) strontium titanate (STO) capacitor dielectrics with RuOx as a bottom electrode and TiN as a top electrode at different temperatures under constant direct current (DC) bias stress. With the space-charge-limited (SCL) current theory, the mobility of oxygen vacancies (VO) and the activation energy (E0) of VO were extracted. By closely examining the time-zero current-voltage (I-V) curves for a positively and a negatively held DC bias conditions before and after the stresses, an understanding of trap-assisted-tunneling (TAT) current, initiated by oxygen vacancies (VO) is presented. Based on this understanding, a way to further reduce the leakage current for a sub-10 nm dielectric film is provided.

An analysis of dopant diffusion and defects in SiGe-channel Quantum Well (QW) with Laser annealing using an atomistic KMC approach are shown. Thin SiGe layer with high Ge content for SiGe-channel QW has an impact on implantation damage and Boron-Transient Enhanced Diffusion (TED) suppression, and defect evolution. KMC shows that As-pocket in SiGe-channel pFET shows enhanced diffusion toward SiGe-channel and higher As concentration in SiGe-channel. The difference of pocket diffusion is one of possible reason for the higher Vth mismatch for SiGe-channel with As pocket than for Si-channel.

Electrical data of advanced capacitor dielectrics such as Sr-rich (Sr/(Sr + Ti) ~ 62%) strontium titanate (STO), rutile TiO 2 , which have dielectric constants higher than 60 even with physical thicknesses in the 7-10 nm range are presented. A practical capacitor model is proposed based on planar metal insulator-metal (MIM) system fabricated using 300 mm toolsets to access required capacitor dielectrics and to predict technical challenges of each technology node. Based on this practical model, mass production friendly path for the introduction of advanced capacitor dielectrics and its choice of electrode to extend life time of Dynamic Random Access Memory (DRAM) is proposed.

A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F 2 ) without the need for pipeline connections. We introduced a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells.

We study the properties of a single gate oxide trap subjected to AC Bias Temperature Instability (BTI) stress conditions by means of Time Dependent Defect Spectroscopy. A theory for predicting the occupancy of a single trap after AC stress is developed based on first order kinetics and verified on experimental data. The developed theory can be used to develop circuit simulators and predict time dependent variability.

An analysis of pocket profile deactivation and its impact on Vth variation for Laser annealed devices using an atomistic kinetic Monte Carlo (KMC) approach are shown. The Carbon co-implant impacts on pFET extension/pocket are also modeled using an atomistic KMC. KMC clarified that although B-pocket in nFET shows significant deactivation, As-pocket in pFET does not show deactivation with thermal budget scaling. pFET device shows smaller thermal budget scaling dependence of Vt mismatch than that of nFET. The difference of pocket deactivation is one of important reason for higher Vth mismatch for nFET than for pFET.

Flash pitch scaling will lead to cells for which the wordline no longer fits between the floating gates, which results in loss of sidewall coupling, causing unacceptable program saturation due to IPD leakage. We present a dual layer poly/metal floating gate (FG) memory device avoiding this saturation and demonstrate +4V programming above the fresh level in a fully planar cell without sidewall coupling using an Al 2 O 3 IPD. The data retention at 200C and cycling performance up to 100k cycles are similar to cells with poly FG.

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

In this study, we report on the device impact related to B pocket diffusion/deactivation using an atomistic kinetic Monte Carlo (KMC) diffusion modeling. An atomistic distribution of B-clusters in nFET channel region is shown. Spike-RTA scaling down to 1000°C for shallow extension formation induces about 10% of B pocket deactivation. KMC reveals that the dominant B-clusters in nFET channel region are BI 2 , B 3 I, B 3 I 2 and come from B pocket implants. B-clusters distribute around the tip of the extension and possibly have an influence on Vth variation. Laser annealing (LA) before spike-RTA improves the B pocket effectiveness and can reduce B pocket dose. This fundamental understanding of the LA impact on B pocket clustering enables us to improve the short-channel effect and Vth variation over a Spike-RTA reference.

Carbon-based thermal stabilization techniques have been used for improving performance of CMOS periphery devices in memory application. Current drives are shown to improve by 15 and 30% for N & PMOS, respectively, external resistance of P+ improves by 15 X and N+ by 30%, and RO delay reduction of 25% compared to the conventional contact scheme.

Atomistic modeling and optimized TCAD simulation strategy for Laser-only annealing device are shown. Multiple laser annealing scans are modeled by using atomistic KMC. KMC clarified that dopant diffusion is changed as a function of laser scan number. SSRM with 1 nm special resolution is used for the 2-dimensional carrier distribution measurement and dopant active level determination. It is shown that 2D profile mapping using SSRM is useful in TCAD simulations.

We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM VDD scalability down to 0.6V (SNM>0.1VDD) and healthy electrical characteristics (VT, sigma(DeltaVT), I-V) for the cell transistors are obtained.

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La2O3, Dy2O3 and Al2O3 on both HfSiO(N) and SiO2 to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lgmin meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices.

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket wafers and electrical measurements on nMOS FUSI/HfSiON device it is found that the RTP1 temperature process window (PW) to obtain NiSi or Ni3Si2 at the FUSI/dielectric interface is significantly widened for spike anneals (30degC < PW < 50degC) compared to soak anneals (15degC < PW < 25degC). Good overlap between the RTP1 process window for nMOS (NiSi or Ni3Si2 at the FUSI/dielectric interface) and the RTP1 process window for pMOS (Ni-rich silicide at the interface) is achieved by the reduction of the poly-Si height for the pMOS gate.

This paper reports a novel approach to implement low Vt Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5 Aring) can lower the NiSi FUSI nFET Vt by 300 mV/500 mV on HfSiON/SiON (resulting in a Vt,lin of 0.25 V/0.18 V respectively), w/o compromising the Tinv (

We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-VT NMOS and PMOS devices with 725/370 muA/mum (at VDD=1.1 V, Ioff=20 pA/mum and Jg= 100/1 mA/cm2). We demonstrate that adding embedded Si0.75Ge0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the VT distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni31Si12 or Ni2Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: -shifting up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; -extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.

We report a record 9% improvement in pMOS performance achieved by using non-melt laser annealing followed by spike-RTA in a conventional poly-Si/SiON CMOS flow. This is the highest pMOS gain with milli-second anneal reported to date, while maintaining at the same time a 7% nMOS gain. The gain is correlated not only to poly-depletion reduction but also to significant S/D resistance lowering. The latter is obtained by switching the annealing sequence, performing laser prior to the Spike-RTA anneal. Different integration sequences and the influence of the absorbing layer on dopants activation and diffusion are investigated in detail in this study. It enables significant transistor performance and short-channel effect improvement over a Spike-RTA reference.

We achieved 635/250 muA/mum @ Ioff=20 pA/mum unstrained FuSI/HfSiON nMOS/pMOS devices (Vdd=1.1 V, Ioff=20 pA/mum, Jg=20/8 mA/cm2) representing a 20%/2% device improvement enabling 10% power delay improvement compared to our previous report. This was reached by a careful optimization of the nitrogen content into our HfSiON gate dielectric (to be 3-6%). Second, we demonstrate that the nitrogen content impacts not only the device performance but also the gate leakage current, the gate oxide integrity as well as PBTI and NBTI. We also report for the first time a 0.8 nm EOT HfSiON dielectric with Ni-FuSI gate and its impact on ring oscillator delay resulting in 9 ps delays. This is an absolute record for any CMOS with metal gate to date.

One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, "independent" double-gate (DG) FinFETs (named "4-terminal-FinFET" because of its four terminals; source, drain, gate 1 and gate 2) have a promising potential to overcome this issue thanks to a post-fabrication flexible Vth controllability in addition to their superior SCE immunity. This paper presents novel 4T-FinFET device technology based on experimental demonstrations. Newly-developed DG separation processes for the 4T-FinFETs, successful fabrication of the optimum 4T-FinFET with asymmetric gate oxides, and dynamic power management demonstration using 4T-FinFET are presented.

In this work, by employing a sub-monolayer HfSiON cap (via ALD deposition) on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices, we report that 1) the devices (both n-FETs and p-FETs) V, is effectively modulated likely due to the Fermi-level pinning relaxation; 2) the gate leakage is significantly reduced; 3) the dielectrics reliability characteristics (such as TZBD, pFETs NBTI, and nFETs PBTI) are clearly improved; 4) both the gate capacitance equivalent thickness (Tinv) and the long channel device high Eeff mobility are preserved. High-Vt ring oscillator with a delay of 17ps has been demonstrated, showing a much-reduced static power (~10 times) as compared to the devices using the pure SiON dielectrics. It is proposed that the SiON dielectrics capped with sub-monolayer HfSiON, in combination with the phase-controlled Ni-FUSI technology, is promising for 45 nm and beyond low power CMOS applications.

n-type dopant diffusion during sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through the experiments and atomistic KMC modeling. Laser-only annealing can improve the n-type dopant activation and achieve shallow junctions. KMC model with vacancy complexes indicates that laser-only annealing for nFET can achieve highly activated junctions and reduce dopant fluctuations in the channel region and that P is an attractive replacement for the As extension with laser-only anneal.

This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-VT applications) have been achieved (17ps at VDD=1.1V and 20pA/?m Ioff), meeting the ITRS 45nm node requirement for low power CMOS.

We report record unloaded ring oscillator delay (17ps at VDD = 1.1V and 20pA/mum Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report presented in A. Lauwers et al. (2005). First, we have improved the (unstrained) devices Idsat to be 560/245muA/mum for nMOS/pMOS at an Ioff = 20pA/mum and VDD=1.1V. Second, we demonstrate that the use of metal gates enables a reduction of the junction anneal temperature, yielding an Lgmin reduction of 7nm/14nm for nMOS/pMOS over our poly-Si/SiON reference. We also report for the first time that metal gate on HfSiON devices can outperform optimized conventional poly-Si/SiON devices by up to 25% in unloaded ring oscillator speed. Finally, our study shows that there is no intrinsic difference between Ni-FUSI compared to inserted metal gates (TiN, TaN)

The optimum gate WF for the pin-controllable CMOS 4T-MuGFETs has been experimentally investigated for the first time. Based on analysis of experimental data, it was concluded that the optimum gate WF is around 4.27eV (5.20eV) for NMOS (PMOS) 4T-MuGFETs

Flexibly-Vth-controllable four-terminal-FinFETs (4T-FinFETs) (Fried, et al., 2003) have great potential to prevent catastrophic increases in static power consumption. Previously-reported 4T-FinFETs had symmetrically thin gate oxides on both channels, unfortunately resulting in large S-slope due to the negative effect of the high second gate (G2) controllability (Lim, et al., 1983). To attain a good S-slope even after DG separation, the asymmetric gate oxide thickness (Tox) (thin drive-gate oxide and slightly thick V th-control-gate oxide) have been suggested. (Wong, et al., 1998) This paper demonstrates, for the first time, asymmetric-Tox 4T-FinFETs with HfO2 (EOT=1.4nm) for one side and HfO 2+thick SiO2 (EOT=6.4-9.4nm) for the other side fabricated by using a novel ion-bombardment-enhanced etching (IBEE) process

We demonstrate for the first time CMOS integration of dual WF (work function) metal gates on HfSiON using Ni-phase controlled FUSI. The novel integration scheme that we demonstrate uses our optimized 2-step Ni FUSI process (1) for simultaneous full silicidation of nMOS and pMOS, achieving different Ni/Si ratios on nMOS and pMOS by reduction of the pMOS poly height through a selective and controlled poly etch back prior to gate silicidation. This novel integration scheme offers the advantages of 1) simplicity (same Ni deposition and silicidation process on nMOS and pMOS), 2) large process window for poly etch-back process (same pMOS characteristics for poly thickness variation of 50%), 3) WF and Vt tuning on HfSiON by phase control, with 4) scalable, linewidth independent suitable Vt's for nMOS (0.5 V) and pMOS (-0.3 V), and 5) solves process yield issues of Ni-rich silicides related to volume expansion, stress, filaments and voiding, resulting in a continuous silicide that is nicely confined between the sidewall spacers. Ring oscillator operation was also demonstrated

This work presents the first comprehensive evaluation of the manufacturability and reliability of dual WF phase controlled Ni-FUSI/HfSiON CMOS (NMOS: NiSi; PMOS: Ni2Si and Ni31 Si12 evaluated) for the 45 nm node. RTP1 and poly/spacer height were identified as the most critical process control parameters in our flow. We demonstrate that a novel sacrificial SiGe cap addition to the flow (improved poly-Si/spacer height control) opens the RTP1 process window from ~5degC to ~20degC for gate lengths down to 45nm, making scalable dual WF CMOS Ni-FUSI manufacturable. We demonstrate Vt control with sigma~19mV (including wafer to wafer variation, N=1000, 45 nm devices) for NMOS (NiSi), and sigma~21mV for PMOS. TDDB and NBTI reliability evaluation of NiSi and, for the first time, of Ni2Si and Ni31Si12 was done. ~1V or larger operating voltages (Vop) were extrapolated for a 10 years lifetime. Using a higher back-end thermal budget showed no reliability degradation

The authors demonstrate a novel CMP-less FUSI integration scheme which uses a spin-on sacrificial material for planarization showing 45nm gate length Ni-rich FUSI pMOS and NiSi FUSI nMOS transistors on HfSiON. This new scheme does not require CMP but remains compatible with phase-controlled dual-WF CMOS with independent silicidation of the S/D and the gate. This approach uses very selective dry etch processes that result in uniform poly-Si height, widening the RTP process window of NiSi FUSI from 5degC (Kittl et al., 2005) for the CMP approach to 15degC, without additional process complexity. Furthermore it is less disruptive compared to the standard CMP approach making it more compatible with stressed liners

We demonstrate for the first time the scalability of NiSi and Ni/sub 3/Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V/sub t/ control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V/sub t/ shifts - at higher thermal budgets. We show that V/sub t/ and WF shifts are larger on high-K (HfO/sub 2/ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni/sub 3/Si FUSI, with no phase control issues, and report HfSiON Ni/sub 3/Si FUSI PMOS devices with V/sub t/= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

This work presents the use of ultimately thin (15 nm) L-shaped spacers to open the process window for deposition-related steps. Whereas conventional spacers prevent the correct active area silicidation between two closely located transistors, these thin L-shaped spacers allow the formation of a low resistive active interconnect between transistors as close as 40 nm apart. With respect to conventional spacers, thin L-shaped spacers show equally good silicide bridging immunity, device characteristics and electrostatic discharge performance.