Search

To develop a photoplethysmogram (PPG)-based authentication system with countermeasures, we investigate a "presentation attack" against the authentication. The attack uses the PPG for performing measurements on various sites on each subject's body. It records PPG on a nongenuine measurement site stealthily, generates a spoofing signal based on the recorded PPG, and transmits the signal to the authentication device. To investigate the feasibility of the attack, we developed a PPG-based authentication system. We recorded the PPGs of the subjects' bodies using the developed system and investigated the feasibility of attack in the experiment. The results indicated that an attack can occur with a probability of more than 80 % under ideal conditions.

A nonvolatile FPGA, where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, a synthesizable nonvolatile FPGA is proposed, where the circuit-configuration information is described in a hardware description language and is pushed through a standard ASIC tool flow with nonvolatile logic circuit IPs such as nonvolatile flip-flops. The use of the ASIC tool flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical design example under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, the performance of the proposed nonvolatile FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.

Field-programmable gate array (FPGA) is growing as a new platform for accelerating heavy computational tasks such as machine learning and cryptography. To making FPGA acceleration as easy as conventional one by graphics processing units, FPGA vendors are providing high-level synthesis tools, such as Xilinx’s SDAccel, that synthesize a circuit from a program written by languages such as C, C++, and OpenCL. The benefit of high-level synthesis, however, comes with the stronger abstraction that makes optimization challenging compared to conventional development using a hardware description language, and there is only a limited publications on how to optimize the performance of a synthesized circuit. In this paper, we take the authenticated encryption algorithm AES-GCM as an example, and show the case study on how to optimize the performance: starting from a naive baseline implementation and achieving a fully pipelined implementation that accepts 128-bit message block every cycle. The optimized implementation achieves 392.173 MB/s, which is 50 times faster than the baseline implementation.

This research proposes a subject identification method using PPG (Photoplethysmogram) signals towards continuous authentication. The proposed method uses feature values derived from heartbeat and respiration extracted from PPG signals by means of frequency filtering and MFCC (Mel-Frequency Cepstrum Coefficients) to identify subjects. An experiment was conducted using an open dataset containing PPG signals to investigate the identification performance of the method. The feature values were extracted from the PPG signals and classifiers were generated to evaluate the performance of the method. As a result, the proposed method was found to be capable of identifying 46 people with the accuracy of 92.9 % by using feature values derived from heartbeat and respiration.

We fabricated a polymer interconnection waveguide aiming for switching between multi-core fibers using 45° mirror and self-formation polymer lens. It can be realized at lower cost by oblique-exposure photolithograph and polymer drop in the hole. According to the analysis results, a very low optical coupling loss would be expected.

Recently, the demand for low-power, high-performance microcontroller units (MCUs) for power-supply-critical sensor node applications has been increasing. In response to this demand, the use of nonvolatile memory elements for realizing MCUs for sensor node applications has been actively researched and developed. The latest nonvolatile MCUs (NV-MCUs) demonstrated 32b operation at 30MHz [1] and 8b operation at 100MHz [2]. However, this performance level is not suitable for sensor node applications that process large numbers of received signals and extract valuable information from them immediately to reduce the amount of transfer data to a data center. The use of various nonvolatile devices has also been proposed. However, these devices exhibit critical drawbacks when applied to sensor node applications, including limited endurance and low compatibility with standard CMOS. A spintronics-based nonvolatile device with unlimited endurance, a short switching time, and CMOS compatibility is a promising candidate for designing a low-power, high-performance NV-MCU.

In this paper, we suggest a three-dimensional fabricating method with biocompatible microgels by using relatively diamagnetic assembly. Microgels were charged positively or negatively before assembly. These microgels attracted each other, whereby an aggregate was constructed. Furthermore, an aggregate hard to disperse after transferring to a dish was obtained by mixing the same amounts of positive microgels 490 nm in diameter and negative microgels 2400 nm in diameter. This result shows that the modeling method is one of the most promising approaches for biocompatible three-dimensional printing.

Magnetic-Tunnel Junction (MTJ)-based non-volatile logic circuits have some possibility to solve the power-dissipation problem seriously focusing on the present CMOS-only-based VLSI processors. Three terminal MTJ devices are the promising candidate as nonvolatile storage device to realize such a nonvolatile logic circuit. However, its writing energy is still serious in comparison with conventional CMOS-only-based logic circuits. In this paper, a new MTJ-based nonvolatile logic circuit with self-terminated mechanism is proposed and its energy efficiency is evaluated in comparison with the corresponding previous work. In addition, some recent research topics related to MTJ-based nonvolatile logic-circuit design and its application, such as a computer-aided-design (CAD) tool considering a stochastic MTJ-switching behavior and the application to a resilient “die-hard” VLSI processor against sudden power-supply outage, are also demonstrated.

An approach for thermal control of an electric heating system having halogen lamp heaters driven by AC line voltage with zero-cross switch is proposed. The feeding power is governed with a delta-sigma modulator estimating the resistance of the halogen lamps dynamically to evaluate the instantaneous feeding power. The thermal model of the halogen heater is identified with the linear functional model around an equilibrium point. The effectiveness of the proposed approach is demonstrated comparing the spectra of feeding power.

A nonvolatile field-programmable gate array (NVFPGA), where both magnetic tunnel junction (MTJ) devices and greedy power-saving techniques are utilized, is proposed. Because the circuit components are shared among several MTJ devices by the use of logic-in-memory (LIM) structure, the number of leakage current paths is reduced, which results in leakage power reduction during power-on. Moreover, the use of the self-termination scheme, which automatically turns off the write current immediately after the desired data is written, makes it possible to minimize power consumption during the backup operation. In fact, the proposed NVFPGA exhibits a 90 % power reduction in comparison with that of a conventional SRAM-based FPGA under typical benchmark-circuit implementations.

The idea to use physical unclonable function (PUF) as a sensor is proposed. Environment-dependent behavior of PUF, which is conventionally unwanted, is used for sensing. Such PUF-based sensor has advantages over ordinary sensors. As a proof of concept, a voltage sensor is prototyped using an ASIC implementation of glitch PUF. The performance of the PUF-based sensor is evaluated by injecting pulses to power supply. The experiment emulates a hostile environment in which an attacker is attempting to inject fault. As a result, the PUF-based sensor successfully detects the injected pulses at high accuracy.

Notable progress has been made recently on the properties and applications of Carbon nanotube (CNT). However, CNT has not achieved any remarkable practical applications from the industrial point of view. In this article, we report our recent progress on the bulk fiber structure of CNT yarn spun from the CNT forest. The unique fiber-like structure of CNT yarns gives them exceptional mechanical toughness, electrical conductivity, resilience to bending stress, and blend with polymer materials for a composite structure. CNT yarn, which is produced by spinning of high dense and relatively long CNT forest, has emerged as a new high-performance CNT-based bulk and composite material. We have made improvements in properties of CNT yarn by applying high voltage (HV) to the CNT yarn in a vacuum chamber. The tensile strengths of as-spun and HV-treated CNT yarns were 624 MPa and 955 MPa, respectively. The crystallization behavior of the amorphous carbon on CNTs was confirmed by a Transmission Electron Microscope (TEM). The CNT yarns provide them mechanical properties different from those of original high-performance fiber.

Novel logic-LSI architecture, “nonvolatile logic-in-memory (NV-LIM) architecture,” where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

A 6-input nonvolatile lookup table (LUT) circuit is proposed using an energy-efficient single-ended logic-in-memory (LIM) structure in conjunction with a magnetic tunnel junction (MTJ) device. While the use of a conventional single-ended LIM structure makes the multi-input LUT circuit compact, a long delay due to the small difference in the MTJ resistance and a large amount of dynamic power consumption due to a DC current path are unavoidable. To overcome the problem, a PMOS feedback transistor which makes it possible to accelerate the logic operation is utilized in the proposed LUT circuit. The use of the PMOS feedback transistor also makes it possible to reduce dynamic power consumption by automatically cutting off the DC current just after logic value ‘0’ is read. In fact, the power-delay product of the proposed 6-input LUT circuit is reduced by 66% in comparison with that of the conventional single-ended one under a 90-nm CMOS technology.

A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.

In this paper, we present a new architecture-level approach, called “nonvolatile logic-in-memory (NV-LIM) architecture,” to solving performance-wall and power-wall problems due to the present CMOS-only-based logic-LSI processors [1]. Figure 1(a) shows a conventional logic LSI chip architecture, where global interconnections between logic and volatile memory modules dominates performance and power dissipation as well as leakage power continuously consumed by volatile memories. In contrast, since nonvolatile storage elements such as magnetic tunnel junction (MTJ) devices are easily distributed over a logic-circuit plane by using a 3D stack structure as shown in Figure 1(b), performance degradation due to intra-chip global wires can be drastically mitigated, which leads to a high- performance, ultra-low-power and highly reliable (or highly resilient) logic LSI.

The authors presented a novel and unique technique of energy trapping applicable for thickness vibrations of backward-wave modes. A special arrangement of electrodes and introduction of a capacitance connected in series with the excitation electrodes enabled the creation of trapped-energy modes. Equivalent-network analysis clarified special energy trapping features. However, the network model used at that time was for one-dimensional analysis and was not applicable for widely used resonators having circular electrodes. As described herein, an equivalent network representation in cylindrical coordinates is presented for backward-wave-type trapped-energy resonators having circular electrodes. Distinguishing features of the trapped-energy resonator of backward-wave modes were reconfirmed.

The recent progress in surface mount technology has highlighted an urgent demand for a higher performance level of inspection technology. X-ray inspection is one of the most suitable systems for substituting the conventional automated optical inspection system. In particular, X-ray computed tomography (CT) inspection provides precise inspection as it can obtain three-dimensional data and can distinguish the features on the top side of a double-sided printed circuit board (PCB) from those on the bottom side. However, X-ray inspection systems are not in common use in the surface mount production line due to their complex image capturing mechanism, which requires a longer inspection time. Taking this limitation into consideration, we developed a simple mechanism utilizing an X-ray line sensor to obtain CT images of a wide area at a faster rate. We term this system as linear CT. In this paper, we explain the image capturing mechanism of linear CT and report that this mechanism can generate cross-sectional images of sufficiently high quality for precise inspection.

The purpose of this study was to compare multi-dimensional construct of people's attitudes toward robots across international regions. A questionnaire was developed with 125 elements representing people's attitudes toward robots, and used in an investigation in Japan, China and Taiwan. A factor analysis was conducted on the responses to the questionnaire from all regions, and a twelve-factor structure was extracted. Moreover, a factor analysis was conducted on the responses of the each region, and factor structures were compared with the universal factor structure extracted from all regions. Regional similarities and differences in dimensions of attitudes towards robots were discussed.

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of today's VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow.

Circuit simulation method for Fault Sensitivity Analysis (FSA) is proposed. The simulation can be used both for (i) security evaluation before fabrication and (ii) investigation of leak mechanism. The proposed method extracts fault sensitivity data from post place-and-route logic simulation results, thus it can easily be integrated with conventional LSI design flow. As a proof of concept, the proposed method is applied to netlist of an AES implementation on 130-nm SASEBO LSI. In the experiment, key recovery attack is successfully recreated using simulated data of a standard implementation (AES_Comp). In addition, to bridge a gap between the simulation and real measurement, we model the effect of induced timing jitter (measurement noise) on the resulting correlation.

A compact lookup table (LUT) circuit using spin transfer-torque magnetic tunnel junction (STT-MTJ) devices combined with MOS transistors is proposed for a standby-power-free field-programmable gate array (FPGA). Since STT-MTJ devices essentially have an asymmetric characteristic in switching currents, one of two write-control transistors can be implemented with a small feature size, while the width of the other one is still large. By sharing the large size of write-control transistor, almost all the transistor size in the proposed LUT circuit becomes small. In fact, the effective silicon area of the proposed write-control transistors for a 6-input LUT circuit is reduced to 68 % in comparison with that of a conventional nonvolatile LUT circuit without applying the asymmetric transistor sizing.

This paper addresses the need for a non-volatile reconfigurable FPGA in order to allow for many current applications to transition away from costly ASIC development. It is assumed that an architecture has been selected and needs to be filled with blocks designed at the transistor level. These are to allow for non-volatility by means of magnetic tunnel junction devices (MTJs). Circuit level designs are presented, together with their successful simulations. The blocks are therefore assembled together and electrically sound simulations are presented for a fully functional FPGA of minimal size. Design and testing is carried out in Cadance Virtuoso and Spectre along with the IBM p13 toolkit. The typical parameters of a University of Tohoku MTJ are used in a SPICE model developed by University of Minnesota.

The Japan Network Security Association reports that leakage through removable memory caused by unauthorized operation has increased. The incidence of business-related information leakage has increased, which has resulted in many legal issues and trials. This paper focuses on information leakage through a PC from USB memory and proposes an information leakage measures system on the USB device that can prevent information leakage due to unauthorized operation or a PC computer virus. This can be achieved using the APIHook function on the PC. The proposed system was implemented on a PC and USB device. As well, the functionality, safety, and performance of the implemented system were evaluated.

In this paper, we focus on comparison between the complementary logics and masked logics as countermeasures against side channel attacks and we develop AES co-processors to which the countermeasures are applied for this purpose. To evaluate the difference that depends on target devices and process, the co-processors are mounted on 130nm-ASIC, 90nm-ASIC and FPGA. Through our performance and security evaluation of the circuits, we demonstrate that the complementary and masked logics do not have the difference on the implementation performance but masked logic is advantageous from the viewpoint of side channel security in a semi-custom design flow.

We studied resonant generation of coherent phonon in ZnTe by a nondegenerate EO sampling measurement. The pump energy dependence of the initial amplitude can be explained by the intense absorption of the pump pulse.

A novel driving method is proposed to improve the picture quality of active-matrix organic light-emitting diode displays. A pulse-width modulation with current uniformization is presented to overcome the non-uniform characteristics and degradation phenomena of thin-film transistors and organic light-emitting diodes. Its working and effect are confirmed using an actual pixel equivalent circuit.

A magnetocardiograph (MCG), which consists of a sensor comprising four superconducting-quantum-interference device (SQUID) gradiometers and a magnetic shielding cylinder made of nanocrystalline soft magnetic materials, has been developed. The sensor can be handled easily because the gradiometers are made of high-critical-temperature (Tc) superconductor operated in liquid nitrogen. Further, the shielding cylinder is lightweight (160 kg) and compact (2 m long and 1 m in diameter). The gradiometer balance is high enough (typically 0.1%) for recording magnetocardiograms inside the shielding cylinder, whose shielding factor is -35 dB at 1 Hz. We used the new MCG to record magnetocardiograms of a healthy volunteer at four different positions. From this magnetocardiograms we then obtained a current arrow map, by which myocardium activity can be estimated, at 16 sites (4 /spl times/ 4 matrix) on the measurement plane. The similarity between the current-arrow map obtained by a conventional MCG and that from the newly developed MCG indicates that the developed compact MCG is also capable of estimating the region of cardiac activity.

We have investigated the growth behavior of sulfur-doped n-InP layers around the dry-etched mesas as a function of various H/sub 2/S flow rates. It is found that the growth rate of the n-InP layer of the sidewall of the mesa is significantly affected by the H/sub 2/S flow rate. Consequently the regrown shape of the embedding layer is found to be exactly controlled by the H/sub 2/S flow rate. Using this technique, we have fabricated a p-substrate 1.3/spl mu/m BH laser with a pnp current-blocking structure around the dry-etched mesa and realized excellent lasing characteristics with high reliability for the first time.

The DFB-LD with a width-tapered waveguide lens is fabricated and narrow beam divergence property is realized. Excellent light output-current (L-l) characteristics in wide-temperature range and error-floor-free transmission at 622 Mbps-40 km are also confirmed. It is promising for the surface-mountable DFB-LD modules.

We have investigated the selective MOCVD re-growth of InP around mesa-stripes along [11¯0] direction formed with reactive ion etching by the addition of HCl gas during MOCVD growth. It is shown that the large overgrowth on the SiO 2 mask in the conventional growth condition is remarkably reduced by the addition of the HCl gas. The mechanism of this effect is analyzed experimentally. It is found that the growth rate on (110) plane (mesa side wall) decreases more remarkably than that on the (001) plane (mesa base) with increasing HCl flow rate. Therefore the growth rate on the side wall can be effectively reduced by the addition of adequate amount of HCl. The reduction of the growth rate on the (110) plane suppress the formation of (111)A plane, which is the cause of the large overgrowth near the mask edge of the mesa stripes. Using these results, we have successfully achieved planar embedded re-growth of InP around dry-etched mesa along [11¯0] direction. This technique is very useful in the application of selective MOCVD growth to the photonic integrated circuits

Beryllium (Be) has been investigated as p-type dopant for InGaAs layers grown using bismethylcyclopentadienyl-beryllium ((MeCp)/sub 2/Be) by low-pressure metalorganic chemical vapor deposition. It is found that hole concentration is in proportion to the (MeCp)/sub 2/Be flow rate, which results in excellent doping controllability. Moreover, the doping efficiency of (MeCp)/sub 2/Be is one order of magnitude higher than that of diethylzinc (DEZn). InGaAs increases with increasing growth temperature in the temperature range from 570 to 625/spl deg/C. Heavily Be-doped InGaAs layers with specular surface morphology have been attained with a hole concentration in excess of 10/sup 19/ cm/sup -3/ by optimization of growth condition. (MeCp)/sub 2/Be is promising precursor as p-type dopant source for optoelectronic devices.