Search

Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly exclusive selections to efficiently select the rare events inside the huge background. We present a fast, high-quality, trackbased event selection for the self-triggered SLIM5 silicon telescope. This is an R&D experiment whose innovative trigger will show that high rejection factors and manageable trigger rates can be achieved using finegranularity, low-material tracking detectors. This strategy requires massive computing power to minimize the online execution time of complex tracking algorithms. Affordable latency and rates are provided by a dedicated device, the Associative Memory (AM). The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the AM exploiting parallelism to the maximum level: it compares the event to precalculated “expectations” (pattern matching) at once. This approach reduces to linear the typical exponential complexity of the CPUbased algorithms. The problem is solved by the time data are loaded into the AM devices. We describe the AM-based trigger and its successful use in the SLIM5 test beam where a silicon detector telescope has been recently tested on the CERN SPS beam.

The front IR quadrupole absorbers (TAS) and the IR neutral particle absorbers (TAN) in the high luminosity insertions of the Large Hadron Collider (LHC) each absorb approximately 1.8 TeV of forward collision products on average per pp interaction (/spl sim/235 W at design luminosity 10/sup 34/ cm/sup -2/ s/sup -1/). This secondary particle flux can be exploited to provide a useful storage ring operations tool for optimization of luminosity. A novel segmented, multi-gap, pressurized gas ionization chambers is being developed for sampling the energy deposited near the maxima of the hadronic/electromagnetic showers in these absorbers. The ionization chamber must be capable of resolving individual bunch crossings at 40 MHz. The ionization chamber is segmented into quadrants; each quadrant consists of sixty (40/spl times/40) mm/sup 2/ Cu plates 1.0 mm thick, with 0.5 mm gaps. The 0.5 mm gap width has been chosen so that the time for the ionization electrons to drift across the gap, is short enough to produce at the output of the shaping amplifier, a signal that returns to the base line is less than the 25 ns bunch spacing of the LHC. From noise considerations in the presence of a cable the stack of plates are connected electrically 10 in parallel, 6 in series to achieve an equivalent detector capacitance C/sub d//spl sim/50 pF. This type connection forms an electrode inductive L/sub e/ and electrode capacitive C/sub e/ network that must be optimized to transfer charge from the chamber to the sensing amplifier. This paper describes the design of the collection electrodes optimized for 40 MHz operation.

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 µm process. The optimization of the collecting electrode geometry and the redesign of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from55Fe and electrons from90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

We developed monolithic active pixel detectors that exploit the triple well option of CMOS 130nm technology to implement analog and digital signal processing at the pixel level. The charge collecting element is realized using the deep N-well (DNW) and partially overlaps the analog circuit. With this scheme we were able to implement a full in-pixel signal processing chain, composed of a charge preamplifier, shaper, discriminator, and latch. This approach has been validated by a first prototype (APSEL0), and we report here on the extensive measurements performed on the second prototype (APSEL1), containing various single pixel structures with analog readout and an 8×8 matrix of 50 × 50 μm2 pixels with sequential digital readout. For 900 μm2 pixels the equivalent noise charge has been measured to be 40 e−, with a S/N ratio of about 30 for the 55Fe 5.9 keV signal. The matrix readout has been tested up to 30 MHz and the crosstalk between pixels characterized. The threshold dispersion and the noise of the pixels in the matrix have been measured through noise scans. These measurements confirm the viability of the triple well process for MAPS fabrication, and indicate the design improvements for the next prototype chip (APSEL2).