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To achieve high dynamic range and define parameter tradeoff of split photodiode pixel based on lateral overflow integration capacitor (LOFIC) technology, the mechanism of extending dynamic range with split photodiode, dual conversion gain and LOFIC technology was studied. A mathematical model of LOFIC technology combined with split photodiode at different pixel sizes is established, which describes responsivity ratio of dual photodiode, LOFIC, conversion gain, and voltage swing affecting dynamic range by equivalent number of random noise electrons and full-well-capacity (FWC) of pixel. Dynamic range of pixel increases from 131.1dB to 133.6dB as responsivity ratio rises from 12 to 16 with voltage swing of 1V and LOFIC node of 25fF, whereas signal-to-noise ratio (SNR) at dual photodiode signal switching point drops from 28.65dB to 27.23dB for $3~\mu \text{m}\,\,\times 3~\mu \text{m}$ pixel. And dynamic range can reach 141dB when LOFIC node rises to 50fF with responsivity ratio of 18 and SNR at small-size photodiode signal switching point decreased by 0.2dB for $10~\mu \text{m}\,\,\times 10~\mu \text{m}$ pixel. The model shows that dynamic range increases with responsivity ratio and LOFIC, whereas is restricted by SNR at signal switching points. This paper provides a design idea and data reference for the design of high dynamic range (HDR) CMOS image sensors based on split photodiode and LOFIC technology. [ABSTRACT FROM AUTHOR]

An analytical model for quantifying the charge transfer potential barrier (CTPB) in pinned photodiode (PPD) CMOS image sensors (CISs) is proposed. The model shows that the height of the CTPB decreases with higher transfer gate (TG) voltage and lighter P-type doping concentration. Based on the thermionic emission theory and the TG surface potential characterization, the potential barrier height dependence on the pinning voltage and the TG design parameters is analyzed. The model was verified with technology computer-aided design (TCAD) simulations and the test devices were fabricated in a $0.11 ~\mu \text{m}$ CIS dedicated process. The simulation and measurement results exhibit pretty good consistency with the proposed model. [ABSTRACT FROM AUTHOR]

In this paper, a $256 \times 128$ rolling shutter time of flight (ToF) CMOS image sensor (CIS) with a low kTC noise and low fixed pattern noise (FPN) reset method is presented. The pixel adopting the proposed reset method has two taps and three reset transistors. The two taps enable this ToF image sensor to capture depth image quickly and the three reset transistors ensure reduction of the kTC noise and FPN. This kind of ToF image sensor is implemented in a $0.13~\mu \text{m}$ one-poly four-metal CMOS technology. The physical size of the pixel with the proposed reset method is $10\,\,\mu \text{m}\,\,\times 10\,\,\mu \text{m}$ with a maximum fill factor of 69%. The chip size of the sensor is $4671\,\,\mu \text{m}\,\,\times 3406\,\,\mu \text{m}$. Measurement results show that the proposed reset method for ToF pixel can reduce the kTC noise and FPN at room temperature effectively. The maximum reduction of kTC noise is $394.9 ~\mu \text{V}$. The maximum reduction of FPN is $531.8 ~\mu \text{V}$. Therefore, ToF sensors with the proposed reset method can achieve low thermal noise and high spatial uniformity. [ABSTRACT FROM AUTHOR]

In order to eliminate the noise on the pulse interval of high-speed spike-based image sensor, a pulse interval compensation (PIC) algorithm is proposed. Based on the analysis of the principle of sensor noise generation, a pulse interval error model is constructed and the compensation algorithm is developed. First, raw pulse data is obtained from the sensor system, and then the coefficient matrix is used to compensate the non-uniform pulse interval caused by the dark current. Then, the guided filter separates high-frequency noise from scenes details and the pulse interval compensation matrix is obtained in the corresponding pulse interval. Finally, the pulse interval compensation is performed on the raw pulse data for correction. In static scene experiments, the proposed method is compared with the existing state-of-the-art methods and shows a clear advantage in denoising in both low texture and rich texture scenes. In the experiment to film a turntable at a rotation speed of 2000 r/min, 3000 r/min, 6000 r/min, the average roughness decreases from 0.2830 to 0.2034, 0.2937 to 0.2139 and 0.3252 to 0.2501 respectively. These experiments proved that the proposed method can effectively eliminate the noise of the spike-based image sensor. [ABSTRACT FROM AUTHOR]

Active image sensors can only record scenes at low frame rates. The dynamic vision sensor (DVS) can capture high-speed scenes under challenging lighting conditions. However, DVS discards absolute light intensity information. The dynamic and active pixel vision image sensor (DAVIS) can output events and low-frame-rate grayscale images simultaneously. This paper proposes a high frame rate video reconstruction and deblurring algorithm based on events and low-speed blurred image sequences from DAVIS. First, we visualized events as a sequence of event images and performed image denoising process. Then, we used the extended 3D partial recursive search (E-3DPRS) method to generate high-performance motion vector field (MVF) between adjacent denoising event images with low computational complexity. MVF reflects the object motion trajectory with high time resolution. Furthermore, MVF is used as a priori information to restore potentially sharp images, which alleviates the highly ill-posed deblurring process. At last, we reconstructed a high frame rate sharp video based on a sharp image sequence and MVFs. Extensive experiments show that our proposed algorithm outperforms the existing state-of-the-art methods and achieves better average feature similarity and structural similarity. [ABSTRACT FROM AUTHOR]

This brief presents a low-ripple, fully-integrated, linear-regulated charge pump with transient-response improvement for CMOS image sensors. A compensator is proposed to accelerate the recovery of the output when an undershoot occurs. The regulated charge pump is designed with 0.11 μm 1-poly 4-metal CMOS process and occupies an area of 0.073 mm2. According to the post-layout simulation, the worst steady-state ripple is 0.95 mVPP and the recovery time (99.9%) of the regulated output is 155 ns when the undershoot is 114 mV. The application of the compensator leads to a 78% decrease on the recovery time. When achieving similar recovery time, the area cost of the proposed topology is reduced by 49% compared to the traditional method of increasing filter capacitance. The total power dissipation of the charge pump is 1.476 mW, and the compensator only consumes 28 μW. [ABSTRACT FROM AUTHOR]

To improve charge transfer efficiency (CTE) and eliminate image lag, the impact of spill back effect on image lag is studied in CMOS image sensors (CISs), particularly in high illumination condition. By establishing a mathematical model based on the thermionic emission and drift-diffusion theory, the physical mechanism of spill back effect is described. This model shows that a lower transfer gate (TG) operating voltage and a higher reset voltage of Floating Diffusion (FD) node would mitigate spill back effect. In a $0.18\mu \text{m}$ CMOS process, by setting that the gate voltage of transfer transistor and the reset voltage of FD is 2.8 V and 3.8 V respectively, CTE of the proposed pixel is increased to 100%. The theoretical analysis and TCAD simulation results can explain spill back effect and offer a reference for designing a high CTE pixel in high illumination CISs. [ABSTRACT FROM AUTHOR]

Threshold temporal contrast (TTC), as a key feature of event-based signal encoding scheme, always fluctuates due to the various noise sources in circuit implementation. This fluctuation (or noise) distorts the information that each event contains, leading to the data quality degeneration. To avoid the errors that may appear in the subsequent signal processing, the degeneration needs to be within the limit demanded by the algorithm. Therefore, modeling the relationship between noise and data quality is important for the event-based hardware application. This paper focuses on analyzing the input-dependent noise on TTC caused by dark current and charge injection, which are labeled as $\delta \Theta _{\mathrm {dc}}$ and $\delta \Theta _{\mathrm {ci}}$ respectively, in self-timed reset dynamic vision sensors (STR-DVS), and evaluates the corresponding impacts on data quality. As for the theoretical derivation part, $\delta \Theta _{\mathrm {dc}}$ is calculated using a logarithmic photocurrent-to-voltage model with dark current taken into account, and $\delta \Theta _{\mathrm {ci}}$ is figured out with a three-phase on-to-off-transient switch model applied in differencing circuit. The data quality evaluation is implemented with event clusters generated from the nonideality-contained model, and the signal-to-distortion ratio (SDR) of the signal reconstructed by a perfect nonlinear recovery algorithm is taken as the metric. The analysis and simulation results are expected to offer a reference on assessing the applicability of STR-DVS for a specific application, or system parameter settings to make the data quality satisfy the requirement while using the sensor. [ABSTRACT FROM AUTHOR]

A method of biomimetic visual perception and image reconstruction based on pulse sequence of events is proposed, and the proposed method facilitates a behavioral model of vision image sensing. Based on the model, the relationship between light condition and quality of reconstructed videos is analyzed. In this sensing method, pulse sequence is defined as synchronous pulse sequence. The sensing method adopts a synchronous pulse sequence readout and asynchronous pixel level sensing mechanism. Light intensity can be calculated by pulse sequences and image or video can be further reconstructed. As the photocurrent increases, the real-time performance of reconstructed image increases, but the depth of the reconstructed image decreases. Experiments are performed on sensing models with two types of pulse sequence generating methods. Method 1 adopts 1-bit data for each pixel, and Method 2 adopts 1-bit data accompanied by 3-bit time label which enables a lower frame rate. In the experiment with static images, the reconstructed images show better image depth under lower photocurrent. The mean square error (MSE) of the reconstructed image with 450 fA maximum photocurrent on Method 1 is 0.0737, whereas the MSE in the same condition on Method 2 is 0.0083. In the experiment with high-speed videos of 20000 f/s, the reconstructed videos with various photocurrents are evaluated by MSE analysis. When maximum photocurrent is between 6750 and 8250 fA as well as between 11250 and 16500 fA, the reconstructed high-speed videos have good MSE results, where video real-time and image depth are balanced. [ABSTRACT FROM AUTHOR]

In this paper, a 120\,\times \, 45 global shutter high speed time delay integration (TDI) CMOS image sensor with pipelined charge transfer pixel (PCT-pixel) is presented. Offset free and low noise pipelined signal accumulation are achieved by the PCT-pixel, and a novel layout is also proposed to increase the equivalent photosensitive area’s fill factor of the proposed pixel. Due to the parallelism of the proposed PCT-pixel, global shutter exposure method is applied in this sensor, which can eliminate nonsynchronous signal capturing problem. The proposed TDI sensor is implemented in a 0.11- \mu \text{m} one-poly three-metal CMOS image sensor technology with a line rate of 100 KHz, a PCT-pixel size of 30\,\times \, 15 \,\,\mu \text{m}^{2}$ , and a fill factor of 43.5%. Measurement results show that the sensor can achieve a maximum sensitivity of 95 V/lux $\,\times \, $ sec and an energy consumption of 0.12 nJ/pixel. Measured signal-to-noise ratio boost value follows theoretical value well. The proposed sensor has the potential to achieve high scanning speed and high TDI stage while costing less power and silicon area. [ABSTRACT FROM PUBLISHER]

The full well capacity (FWC) of the four-transistor pixel in CMOS image sensors (CISs) should be a constant which is decided by photodiode structure, doping, and manufacturer, whereas the measured FWC in experiments varies with the incident light intensity. In this paper, a model for the light-dependent FWC is developed. The model includes two sources that contribute to the extra light-dependent charge. They are collected along with the intrinsic full well charge in the photodiode or the floating diffusion. The first source comes from the equilibrium between the photocurrent and the photodiode forward current. The other source is the extra collected charges during charge transfer. An analysis model is developed to describe these two light-dependent sources, and the saturated output shows logarithmic and linear relationship with light intensity at low- and high-light condition, respectively. A device level simulation using technology computer aided design software was performed to verify the proposed model. Furthermore, a prototype chip with 15- \mu \textm \times 15 - \mu \textm pixels fabricated in a 0.18- \mu \textm CIS process was tested. The simulation and measurement results exhibit fairly good consistency with the proposed model. The estimation of the intrinsic FWC is also discussed. [ABSTRACT FROM PUBLISHER]

A 128-stage CMOS time delay integration (TDI) image sensor with on-chip digital accumulator was presented in this paper. By using two sets of sampling capacitors and an optimized timing, the on-chip column parallel cyclic analog-to-digital converter (ADC) in the sensor conducts the correlated double sampling, digital program gain amplifying, and A/D conversion all altogether in one ADC’s conversion time simultaneously. An on-chip digital accumulator suitable for this sensor is also proposed. A prototype 1024 \times 128 CMOS TDI image sensor is fabricated in the 0.18- \mu \text{m} CMOS technology, and the measurement results proof that the pixels and readout circuits in the sensor work properly. With a line rate of 3875 lines/s, the sensor costs a power consumption of 290 mW and a silicon area of 18.2~\textrm {mm}\times 18.9$ mm. The estimated maximum sensitivity of the fabricated sensor is 2010 \textrm {V}/\textrm {lux}\cdot \textrm {sec} . This paper is suitable for applications in low-illumination, high scanning speed, and remote sensing systems. [ABSTRACT FROM PUBLISHER]

This paper presents an in-pixel dual exposure synthesis technique to extend dynamic range of CMOS image sensors (CISs). The transfer transistor of the 4-T pixel acts as an overflow transistor in this proposed method. The full well capacity of photodiode (PD) can be very well controlled by biasing the transfer gate at different states. The long and short time exposed signals can be both stored in PD by adjusting the transfer gate voltage, and such the wide dynamic range signal can be obtained without extra readout operation. A proto chip with $64 \times 48$ pixel array is fabricated in 0.18- $\mu $ m CIS process. The sensor structure is based on a typical 4-T pixel image sensor with modified transfer gate driver and timing. This structure not only maintains the good features of 4-T pixels, such as good fill factor and low noise, but also achieves a wide dynamic range. The dynamic range of the proto chip is extended from 51.59 to 90.53 dB. [ABSTRACT FROM PUBLISHER]