Search

Intracranial hematoma due to traumatic brain injury is a serious health concern with rates of morbidity and mortality that are increasing worldwide. Manual identification is slow, subject to observer variabilities, and the existing automated techniques for intracranial hematoma detection in non-contrast computed tomography images cannot effectively detect multiple lesions of irregular sizes and shapes. Therefore, a computer-aided system using different window settings, YOLOv5s, cascaded attention module, and spatial pyramid pooling-fast is proposed to detect hematoma types, namely acute intraparenchymal, intraventricular, subdural, epidural, subarachnoid, and chronic subdural. Firstly, the computed tomography images are pre-processed using a window-based stacking approach wherein a three-channel image is generated by stacking grayscale images obtained with the aid of multiple window settings, i.e, brain, bone, and subdural. Secondly, a cascaded attention module is constructed in the neck of the YOLOv5s model to improve its detection performance by placing the convolution block attention module in serial with the efficient channel attention module. The cascaded attention module enriches the feature representation of various hematoma types in complex backgrounds especially when they are small and inconspicuous. The spatial pyramid pooling is replaced by a spatial pyramid pooling-fast to reduce the computational parameters and accelerate the feature fusion ability. The proposed deep learning model is trained, validated, and tested with 15,921 images from the brain haemorrhage extended dataset and it achieved overall precision, recall, F1-score, and mean average precision at 0.5, and mean average precision at 0.5:0.95 of 0.935, 0.908, 0.921, 0.943 and 0.65 respectively. The experimental results show that in comparison to the original YOLOv5s model and state-of-the-art methods, the model was able to localize and classify the acute or chronic instances of five hematoma subtypes in an individual image with improved precision and recall values. Hence the proposed system can be used in hospitals for the early and accurate detection of hematoma.

Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the cornerstone in bringing large-scale quantum processors to reality. The major challenges are, however, the tight power budget (in the order of milliwatts) and small latency (in the order of microseconds) requirements that such circuits inevitably must fulfill when operating at cryogenic temperatures. In-memory computing (IMC) is rapidly emerging as an attractive paradigm that holds the promise of performing computations efficiently where the data does not need to move back and forth between the CPU and the memory. Hence, it overcomes the fundamental bottleneck in classical von Neumann architectures, which provides considerable savings in power and latency. In this work, for the first time, we propose and implement an end-to-end approach that investigates SRAM-based IMC for cryogenic CMOS. To achieve that, we first characterize commercial 5 nm FinFETs from 300 K down to 10 K. Then, we employ the first cryogenic-aware industry-standard compact model for the FinFET technology (BSIM-CMG) to empower SPICE to accurately capture how cryogenic temperatures alter the electrical characteristics of transistors (e.g., threshold voltage, carrier mobility, sub-threshold slope, etc.). Our key contributions span from (1) carefully calibrating the cryogenic-aware BSIM-CMG against commercial 5 nm FinFET measurements in which SPICE simulations come with an excellent agreement with the experimental data, (2) exploring how the robustness of SRAM cells against noise (during the hold, read, and write operations) changes at extremely low temperatures, (3) investigating how the behavior of SRAM-based IMC circuits changes at 10 K compared to 300 K, and (4) modeling the error probabilities of IMC circuits that are used to calculate the Hamming distance, which is one of the essential similarity calculations to perform classifications.

Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more quantum bits (qubits). One obstacle for scaling up quantum computers is the connection between their cryogenic qubits at temperatures between a few millikelvin and a few kelvin (depending on qubit type) and the classical processing system on chip (SoC) at room temperature ($300 \,\mathrm{K}$). Through this connection, outside heat leaks to the qubits and can disrupt their state. Hence, moving the SoC into the cryogenic part eliminates this heat leakage. However, the cooling capacity is limited, requiring a low-power SoC, which, at the same time, has to classify qubit measurements under a tight time constraint. In this work, we explore for the first time if an off-the-shelf SoC is a plausible option for such a task. Our analysis starts with measurements of state-of-the-art 5-nm fin-shaped field-effect transistors (FinFETs) at 10 and $300 \,\mathrm{K}$. Then, we calibrate a transistor compact model and create two standard cell libraries, one for each temperature. We perform synthesis and physical layout of a RISC-V SoC at $300 \,\mathrm{K}$ and analyze its performance at $10 \,\mathrm{K}$. Our simulations show that the SoC at $10 \,\mathrm{K}$ is plausible but lacks the performance to process more than a few thousand qubits under the time constraint.

This paper presents a method for increasing the operating frequency range of a sub-6 GHz transmitter to millimeter wave (mm-wave) using two cascaded frequency doublers. The usage of such a frequency up-conversion approach is constrained since applying the first frequency doubler’s generated harmonics to the second doubler for mm-wave signal creation results in severe distortions and bandwidth expansion of the transmitted signal, limiting the use of such frequency up-conversion method. We have proposed a combined gain and phase retarder and physically inspired cascaded feed-forward neural network (CFFNN) based digital predistortion to mitigate the bandwidth expansion and distortions. A comparative study of feed-forward neural networks (FFNN) and CFFNN has been carried out to establish CFFNN as a significant and less complex model for effective DPD of frequency quadrupler. For proof of concept, we have experimentally validated this method for Long-Term Evolution (LTE) 20 MHZ (64-QAM) signal at 24 GHz frequency band using commercially available frequency multipliers. The measurement results show the bandwidth expansion is reduced approximately 11–12 times, and the adjacent channel power ratio (ACPR) of around −45.1 dBc and error vector magnitude (EVM) of approximately 3.07% is achieved.

Retinal Fluids (fluid collections) develop because of the accumulation of fluid in the retina, which may be caused by several retinal disorders, and can lead to loss of vision. Optical coherence tomography (OCT) provides non-invasive cross-sectional images of the retina and enables the visualization of different retinal abnormalities. The identification and segmentation of retinal cysts from OCT scans is gaining immense attention since the manual analysis of OCT data is time consuming and requires an experienced ophthalmologist. Identification and categorization of the retinal cysts aids in establishing the pathophysiology of various retinal diseases, such as macular edema, diabetic macular edema, and age-related macular degeneration. Hence, an automatic algorithm for the segmentation and detection of retinal cysts would be of great value to the ophthalmologists. In this study, we have proposed a convolutional neural network-based deep ensemble architecture that can segment the three different types of retinal cysts from the retinal OCT images. The quantitative and qualitative performance of the model was evaluated using the publicly available RETOUCH challenge dataset. The proposed model outperformed the state-of-the-art methods, with an overall improvement of 1.8%.

This paper presents a new design of charge plasma junctionless tunnel field effect transistor (CP JLTFET) with improved ON current, surface potentials. For the ease of fabrication, source and drain regions are induced in intrinsic silicon material using proper metal workfunctions. The rate of tunneling of electrons is found more in case of proposed CP JLTFET. The cavity length is varied between 8 nm and 10 nm and different dielectric constants have been used. This increased the ON state performance of device i.e ON drive current, potential and electric field. The increase in tunneling of electrons is mainly due to high recombination of carriers in the channel region. The proposed device simulated their electrical parameters like drain current, surface potentials, electric field, and energy bands with different dielectric constants. These excellent performance parameters of the proposed device with an appropriate material can be used for sensing application of biomolecules by introducing a cavity in the device.

As the size of data is increasing exponentially, its security is a major concern. Emerging technology like blockchain is used to provide security to systems. Since the inception of blockchain, it has been adopted by researchers and industry both, however, it gained enormous attention after cryptocurrency. It can be defined as a means of storing information in such a way that modification and hacking the system is difficult or impossible. A blockchain is a decentralized ledger that is digital and public, consisting of records of transactions called blocks. A consensus technology assures that all nodes agree on a unique sequence for appending blocks. A comprehensive examination of these algorithms will aid in understanding how and why each blockchain operates in the manner that it does. In this study, we addressed extensively used consensus techniques in the blockchain and the importance of consensus protocol in blockchain technology. The underlying consensus algorithm is a critical component of every blockchain-based system which determine the performance and security of the system. Ensuring the correctness of consensus protocols is uttermost important to create trust in the blockchain-based systems and formal methods are the way to create that trust and develop correct and verified systems. Formal modeling is a method of writing a system mathematically and examining the correctness and verifying the developed system. This study analyzed the importance of consensus mechanisms and how formal methods are helping to develop a correct blockchain-based system. The current scenario of the application of formal methods in the consensus mechanism of blockchain for their verification is presented.

Ensuring women’s safety in smart cities is a need of the hour. Even though several legal and technological steps are adopted worldwide, women’s safety continues to be an international concern. Criminal records are maintained by law enforcement agencies and are most often not available to the public in an easily comprehensible form. While some wearable devices and mobile applications are available which are touted to aid in ensuring women’s safety, they utilize limited societal intervention and are not very efficient in ensuring the safety of the women as and when required. Most often the crime response, crime analysis, and crime prevention schemes are not integrated, leading to gaps in ensuring women’s safety. Our major contribution is in developing a holistic system encompassing the three crucial aspects, i.e crime analysis and mapping, crime prevention, and emergency response by leveraging societal participation for women safety management. This work applies the Geographic Information System (GIS) for the identification of hotspots and patterns of crime. The proposed system uses data generated from the mobile application and/or wearable gadget prototyped as a part of this work along with the criminal history records for crime response, analysis, and prevention. The system for the hotspot identification is demonstrated for the Pilani town in the Jhunjhunu district in the state of Rajasthan, India, and can be easily scaled up geographically and utilized as a safety strategy for smart cities. While the common man is provided a cost-effective solution via the developed mobile application or wearable gadget, the various components are integrated into a website for supervisory management and can be utilized by law enforcement agencies.

Monitoring of total suspended matter (TSM) concentration in the coastal waters is vital for water quality monitoring and coastal management. In this study, TSM over the highly dynamic Hooghly estuary region is derived using moderate resolution imaging spectroradiometer (MODIS) surface reflectances at 645 nm and in situ TSM observations. MODIS TSM products show a correlation of 0.95, root-mean-square error of 24.72 g/m3, and mean absolute and percentage errors of 18.25 g/m3 and 23.2%, respectively, when compared with in situ measurements. Subsequently, TSM variability in the Hooghly estuary from the derived TSM maps was analyzed during the period 2003–2018 on monthly and seasonal time scales. The annual cycle of TSM showed peak concentration (>250 g/m3) during the southwest monsoon season that could be attributed to large-scale river discharge as compared with the northeast and intermonsoon seasons (∼100–150 g/m3). Interannual variability showed higher TSM during the years 2004, 2012, and 2013 and low during 2005 and 2015. It could be concluded that the fine tuning of the existing TSM retrieval algorithm is essential based on the long-term earth observation data for monitoring the sediment distribution in the coastal and estuarine regions utilizing available satellite observations, particularly in the highly turbid estuaries, such as the Hooghly estuary.

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness ( $t_{FE}$ ) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a $14nm$ FDSOI technology node, exploring the impact of $t_{FE}$ on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., $I_{ON}$ , $SS$ , $I_{ON}/I_{OFF}$ and $C_{gg}$ ) by varying $t_{FE}$ up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum $t_{FE}$ . We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum $t_{FE}$ . Further, we analyze the impact of $t_{FE}$ on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with $t_{FE}$ . However, the WNM in general follows a non monotonic trend w.r.t $t_{FE}$ , and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized.

In this article, we propose a compact model for Negative Capacitance Nanosheet Field Effect Transistor (NC-NSFET) including quasi-ballistic transport for sub-7nm technology node. The model captures the electrical characteristics of NC-NSFET for different ferroelectric thicknesses. Further, it captures the reverse short channel effects of NCFET for different channel lengths with a single set of parameters. Also, we build a model for terminal charges of NC-NSFET using the core model and the earlier developed inner fringing charge model. Using our physics-based model, we find that quasi ballistic transport worsens the capacitance matching in NCFET compared to drift-diffusion only case. We validate the compact model for the drain current and the terminal charges with the TCAD results. The proposed compact model is computationally efficient and implemented in the Verilog-A code to enable SPICE circuit simulations. Finally, we demonstrate this by applying our model for NC-NSFET based CMOS inverter and SRAM circuit implementations in SPICE.

In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart - when both of these devices are operated at the same nominal supply voltage of the 14nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former's better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

This paper presents an adaptive neuro-fuzzy sliding mode control (ANFSMC) scheme for diving motion control of an autonomous underwater vehicle (AUV) in the presence of parameter perturbations and wave disturbances. In the derivation of diving motion equations of an AUV, the pitch angle of the vehicle is often assumed to be small in the vertical plane. This is a quite strong restricting condition in underwater operations and may cause serious modeling inaccuracies in AUV's dynamics. The problem of nonlinear uncertain diving behavior with restricting assumption on the pitch angle directly is resolved by a neural network (NN) based equivalent control. The online NN estimator is designed to approximate a part of the equivalent control term containing nonlinear unknown dynamics and external disturbances. Subsequently, corrective control based on an adaptive fuzzy proportional-integral control is applied to eliminate the chattering phenomenon by smoothing the switching signal and also compensate structured uncertainties. The weights of NN are updated such that the corrective control signal of the ANFSMC converges towards zero. The adaptive laws are developed to compute coefficients of PID sliding manifold and adjust the gain of fuzzy switching control. The simulation results are presented to shows the efficacy of the control performance.

Urbanization can change the local climate of an area, one manifestation of which is a rise in the local temperature of built-up areas, a phenomenon known as an urban heat island. The thermal response of built-up areas in comparison to natural areas is quantified in terms of surface urban heat island (SUHI) intensity. The work presented here evaluates the seasonal SUHI intensities in Delhi using local climate zones (LCZs) and conventional SUHI indicators in parallel. Statistical analyses are carried out to determine the relationship between them and to delineate heat stressed zones in the Delhi city region. The present study is the first one that utilizes LCZs for seasonal SUHI analysis in Delhi. The land surface temperature (LST) is assessed using a hundred and five night-time images from MODIS. Unambiguous night-time SUHI effect is seen for all seasons. The maximum night-time SUHI intensity is 3.5° C, between “compact low-rise” (LCZ 3) and “low plants” (LCZ D) in summer and winter. The conventional indicator “Inside urban-Inside rural” gives the highest night-time SUHI intensity of 3.3° C, in autumn. Statistical analyses show that “compact low-rise” (LCZ3) and “large low-rise” (LCZ8) are the most heat-stressed LCZs. The largest number of distinct thermal zones is created in the monsoon, followed by summer and winter. The results suggest that in order to minimize the UHI effect, further urban expansion in the Delhi region should be restricted to LCZ 5 (open mid-rise) and LCZ 6 (open low-rise).

Negative capacitance field-effect transistor (NCFET) addresses one of the key fundamental limits in technology scaling, akin to the non-scalable Boltzmann factor, by offering a sub-threshold swing below 60 mV/decade. In this paper, we investigate how the NCFET technology can open the doors not only for the continuation of Moore's law, which is approaching its end, but also for reviving Dennard's scaling, which stopped more than a decade ago. We study NCFET for the 7-nm FinFET technology node, from physics to processors and demonstrate that prior trends in processor design with respect to voltage and frequency can be revived with the NCFET technology. Our work focuses on answering the following three questions towards drawing the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors: 1) to operate at higher frequencies without increasing voltage; 2) to operate at higher frequencies without increasing power density, which is substantial, because maintaining on-chip power densities under tight constraints due to limited cooling capabilities is inevitable; and 3) to operate at lower voltages, while still fulfilling performance requirements, which is substantial for the emerging Internet of Things, in which available power budgets for such devices are typically very restricted.

Assessment of equipment trip is needed for proper estimation of interruption/disruption cost and voltage sag mitigation. The equipment trip depends on the severity of voltage sag and the tolerance of the equipment toward the sag. However, the occurrence of voltage tolerance of an equipment in between the two known bound levels is uncertain in nature. The existing evaluation methods for equipment trip analysis fail to properly assess this uncertain property of voltage tolerance curves. This paper presents a novel approach to assess the equipment trip by handling the uncertainties by using fuzzy probability and possibility distribution. A new method is proposed to transform a rigorously performed statistical data into a fuzzy possibility distribution function, which eliminates the ambiguity that comes with the non-standardized selection of membership function/possibility function. With the proposed method, the statistical data are used to extract the fuzzy probability distribution of voltage sag intensity, which is given by both the magnitude and time duration of voltage sags, while the concept of fuzzy probability is used to calculate the fuzzy trip probability or equipment failure probability. The proposed method is finally applied to estimate the number of trips for six different sensitive equipments connected to two practical Indian distribution systems.

Presents a study which described and compared some types of depressed-collector designs for the development of continuous-wave gyrotrons for heating fusion plasmas. Applications of gyrotrons and gyroklystrons; Summary.

Presents the designs of single-stage depressed collectors for high-power pulsed gyroklystron amplifiers. Description of the depressed collector design; Implementation of energy recovery in high-power pulsed devices; Conclusions.