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Heterogeneous Integration is evolving to acquire finer resolution and larger devices to leverage the advantages provided by More-than-Moore manufacturing and packaging technologies that can help maximize the efficiency and increase the bandwidth of high performance computing systems. Advanced Packaging with submicron Redistribution Layers (RDL) and large package sizes is one of solutions that can help enable complex Heterogeneous Integration designs for applications including Artificial Intelligence (AI), 5G communication and autonomous driving. For systems requiring large package sizes, Panel Level Packaging (PLP) can offer efficiency and cost advantages over Wafer Level Packaging (WLP). PLP however poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first patterning exposure tool or stepper that is capable of submicron resolution on 500 mm panels. This new panel exposure tool is equipped with wide-field projection optics that offer a large $\mathrm{52}\ \text{mm}\times \mathrm{68}\ \text{mm}$ image field and 0.24 NA that is optimum for submicron resolution. The stepper also features a newly developed panel handling system for processing up to $\mathrm{515}\times \mathrm{515}\ \text{mm}$ panels. In this paper, we will report on evaluation results of fine patterning for a mass-production panel level packaging process using the new submicron resolution panel stepper. We will also discuss current fine-PLP status, challenges and solutions. One topic of our study is patterning uniformity. In 2020, we reported patterning uniformity improvement technology using a glass substrate. This study attempts to apply the technology described in 2020 to improve pattern uniformity on Copper Clad Laminate (CCL) substrates that are widely used in printed circuit board (PCB) manufacturing. In addition, we will report on results of studies of stitching capability and alignment accuracy on substrates with die placement error. Our study also explored warped panel handling including the development of a multi-vacuum line chucking system.

High-Performance Computing (HPC) systems increasingly adopt Heterogeneous Integration (HI) technologies that utilize large substrates and high-resolution processes to facilitate die and chiplet. Fan-Out Wafer Level Packaging (FOWLP) and silicon interposers using high-density Redistribution Layers (RDL) can help maximize bandwidth and performance but HI roadmaps require improvements in resolution and lower costs to enable wide adoption of these More-than-Moore technologies. Panel based processes can provide cost advantages compared to wafer processes for fabrication of large interposers and Fan-Out packages. Panel based SiP processes however demand submicron resolution over a large field size and uniform exposure across large panels. To meet these challenges, Canon developed the first lithography exposure system capable of achieving submicron resolution on large panels. The new panel exposure tool targets 0.8 μm design rules and utilizes a new panel handling system and stage that allows processing of panels as large as 515 × 515 mm. The new panel exposure tool is equipped with a UL82 wide-field projection lens with a maximum Numerical Aperture (NA) of 0.24 and offers a 52 × 68 mm exposure field for large device fabrication without stitching adjacent shots. Fine-RDL lithography systems must provide a large Depth-of-Focus (DoF) to maintain pattern fidelity to maximize DoF, the new panel exposure tool applies die-by-die focus and tilt compensation and functions to compensate for panel warpage. Process factors related to DoF include panel flatness and photoresist materials and film uniformity. This paper details test results from a panel exposure system that confirms the feasibility and advantages of submicron panel processes. We also introduce additional challenges related to panel processes including slit-coater uniformity, photo resist materials and panel flatness. We will present data illustrating that new panel exposure tool can provide excellent resolution across large exposure fields on panels to enable HI innovation.

More-than-Moore approaches to improving system performance have been a hot topic for a decade, starting with 3D-integration using Through-Silicon Vias (TSV) and silicon interposers. Today, Heterogeneous Integration (HI) technologies including Fan-Out Wafer-Level Packaging (FOWLP) with fine Redistribution Layers (RDL) are promising technologies that can deliver benefits not possible with More-Moore scaling alone.Fan-Out devices are required to meet the demands of advanced Graphics Processing Unit (GPU) and Field-Programmable Gate Arrays (FPGA) that require wideband interconnection with memory for Artificial Intelligence (AI) and autonomous driving. Next-generation devices require submicron RDL and large die sizes to enable high-performance computing using GPU and FPGA designs.For large die-size devices, Fan-out Panel Level Packaging (FOPLP) can offer efficiency and cost advantages compared to FOWLP, however FOPLP poses unique technical challenges including the requirement to realize uniform submicron patterning across the entire rectangular panel. To meet this challenge, Canon developed the first 500 mm panel size patterning exposure tool capable of submicron resolution.The new panel exposure tool is equipped with a wide-field projection optics that offer a wide image field (52 mm x 68 mm) and optimum 0.24 NA for sub-micron resolution and a newly developed panel handling system that handles up to 515 mm x 515 mm panels.Die-by-die focus and tilt compensation are necessary to realize submicron patterning and Canon’s panel exposure tools adopt a front-end i-line stepper, on-axis optical focus, tilt system for die-by-die focus and tilt measurement. Canon also developed a new panel stage that executes die-by-die focus and tilt compensation.Canon manufactured a debug tool and confirmed the new panel exposure tool advantages for submicron FOPLP high volume manufacturing and in this paper, we will report on the performance of the new submicron patterning panel exposure tool and will introduce technology innovations supporting advanced heterogeneous integration technologies. We will also discuss current and future FOPLP advantages and challenges and will report on FOPLP resolution performance related to slit coater performance, photoresist materials and the flatness of panel substrates.

High-Performance Computing systems can employ leading-edge Heterogeneous Integration (HI) technology including Fan-Out Wafer Level Packaging (FOWLP) and high-density Redistribution Layers (RDL) to maximize system bandwidth and performance. These More-than-Moore strategies are growing in importance and present unique challenges that must be overcome to enable mainstream adoption. FOWLP roadmaps for interconnections between SoC (System on Chip) and DRAM (Dynamic Random Access Memory), split-die FPGA (Field-Programmable Gate Array) and image sensors and SoC are driving RDL scaling and aggressive FOWLP processes are targeting $0.8\ \mu \mathrm{m}$ design rules. High-resolution lithography is required for high-density, fine-RDL applications and the main lithography challenge is to provide a large Depth-of-Focus (DoF) to reliably pattern sub-micron RDL traces across a large exposure field. This paper details an analysis of candidate optical conditions for sub-micron imaging including data demonstrating the DoF performance of an optimized lithography system (stepper). To meet the high-resolution requirements of fine-RDL processes, Canon developed the FPA-5520iV-HR [20iV-HR] i-line stepper that employs a new projection optical system featuring a maximum 0.24 Numerical Aperture (NA) and a 52 x 34 mm field size. We will present data illustrating that 0.24 NA steppers can provide excellent resolution and pattern fidelity throughout each exposure field across the entire wafer. High-density FOWLP wafers can also display extreme die-shift, warpage and topography that must be addressed to enable high-yield and high-productivity processes. Die placement error in FOWLP wafers creates orders of magnitude more alignment error versus traditional silicon wafers and advanced alignment compensation is required to improve overlay matching. Alignment solutions for processing distorted FOWLP wafers include the Grid-PA system that automatically corrects the wafer loading position based on die-grid sampling, and Enhanced Advanced Global Alignment (EAGA) that allows the stepper to measure and compensate for shift, rotation and intra-field magnification errors on a die-by-die basis. FOWLP reconstituted wafers can also experience large warpage that can decrease productivity and DoF and to combat these challenges, our steppers have been designed to handle wafers with over 5 mm of warpage and are also based on a Front-End-Of-the-Line (FEOL) stepper platform that offers die-by-die tilt and focus measurement and compensation to maximize focus accuracy and DoF. This paper provides an analysis of key lithography challenges facing aggressive FOWLP and fine-RDL processes details of stepper technology that helps enable high-density integration in mass-production. We remain committed to enabling innovation through lithography system performance upgrades and development of original options supporting current and future FOWLP and fine-RDL processes.

In recent years, demand for high density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through Silicon Via (TSV) technology and 2.5D integration technology using silicon interposers, Fan-Out Wafer Level Packaging (FOWLP) using redistribution processes over chip size has become a hot topic these days.

In recent years, demand for high-density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through-Silicon Via (TSV) technology and 2.5D integration technology using silicon interposers, Fan-Out Wafer Level Packaging (FOWLP) using redistribution processes over chip size has become a hot topic these days. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies into mass production and to meet these challenges, Canon developed the FPA-5510iV i-line lithography tool which is now widely used at customer sites. In this paper, we will explain details of FPA-5510iV features that support high-density integration, additional challenges that must be solved for successful implementation of high-density integration technologies in mass production and Canon's efforts to solve the remaining challenges.