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In the 3D ferroelectric memory fabrication process, the outer Titanium nitride metal electrode and silicon doped hafnium-based ferroelectric layer will produce void defects at the interfaces, causing increased leakage and compromising device performance. These void defects are caused by the volume contraction during the phase transition process, which leads to tension at the outer interface of the 3D ferroelectric capacitor structure. Due to the unavoidable structural stress, it is necessary to optimize the interface bonding energy. First principles simulation revealed insufficient binding energy between titanium nitride and silicon doped hafnium oxide ferroelectric materials, while introducing an amorphous alumina interface layer can effectively improve the binding ability. Experimental verification has confirmed that using an amorphous alumina interface layer as an adhesive layer can successfully solve the interface void defects, thereby improving the ferroelectric properties in three-dimensional structures. [ABSTRACT FROM AUTHOR]

The 3-D TLC NAND flash memory significantly increases the storage capacity but makes data more prone to errors. To address the reliability problem, Polar Code is one coding method that can reach the channel capacity (Arikan 2009). However, the 3-D NAND flash memory channel is uncertain due to the variation of retention time and program/erase(P/E) cycle. So it is difficult to construct a Polar Code in the NAND flash memory. This letter proposes a new Polar Code construction method called dynamic merge Monte Carlo (DMMC). DMMC uses the Monte Carlo method to obtain the optimal Polar Code construction and then reduces the space overhead by combining similar construction so that it can be used in flash memory systems. Compared with the conventional method, the uncorrectable bit error rate (UBER) of the proposed method can reduce by up to 90.5%, and the read latency can reduce by more than 50%. [ABSTRACT FROM AUTHOR]

The high thermal budget of three-dimensional NAND Flash (3D NAND Flash) is the key issue limiting the increase in vertical integration. The main purpose of this article is to design a local and high temperature annealing function to reduce the thermal budget and gain a high activation rate without diffusion at a target depth to improve the performance of 3D NAND Flash devices by laser annealing with green wavelength. The method of nanosecond pulse laser annealing (ns-PLA) for amorphous silicon (a-Si) crystallization and activation has been proven, and this method has the benefits of a low thermal budget and controllable heating. According to previous experiments, one of the important results is that ns-PLA with high energy can provide a high temperature that reaches the melting point of a-Si and obtain a deep and monocrystal-like silicon channel through liquid phase crystallization in 3D NAND applications and obtain a higher activation rate. These results cast emerging light on low thermal budget processes based on ns-PLA in 3D NAND flash for future architecture such as Xtacking architecture, and have significant ramifications for impurity activation rates and reducing channel leakages. [ABSTRACT FROM AUTHOR]

As the storage density of 3-D NAND flash memory increases, reliability issues become a bottleneck. Among all reliability issues, decreased retention time is the dominant one. To extend the retention time, data refresh is a straightforward approach. However, refresh operations introduce redundant operations, which hurt the performance of the 3-D NAND flash system. With the observation that retention time can be extended by wordline (WL) interference, this letter first proposes to extend retention time with WL interference practically, and then presents a refresh scheme, which refreshes only one-third of pages in a block and postpones the refresh on the remaining two-thirds of pages with WI. The evaluation results show that the refresh operations are reduced by 40.7% at most. Compared with previous work, the read and write response times are decreased by 31.2% and 43.5%, respectively, with a 7-day refresh period. [ABSTRACT FROM AUTHOR]

The dual-deck architecture with aligned upper and lower decks is considered a promising technology to meet the demand of increasing word-line (WL) layers of 3D NAND flash. However, the relevant reliability studies are still lacking for the dual-deck 3D NAND array. In this work, it is reported an abnormal program disturbance phenomena of the bottom WLs in the upper-deck, and the physical mechanisms were studied. According to experimental analysis and TCAD simulations, the un-programmed dummy WLs at the joint region can introduce excessive joint residual electrons in the channel before the program, resulting in insufficient channel self-boosting potential, which is responsible for the degraded program disturbance. Thus, a novel program scheme is proposed to alleviate the program disturbance, which has been validated by experiments. [ABSTRACT FROM AUTHOR]

As an important constraint on the threshold voltage (Vt) distribution, the random telegraph noise (RTN) has attracted much attention due to the widely used multi-bit-per-cell technology in 3D NAND flash. This work investigated the physical mechanisms of RTN in charge- trap-based 3D NAND flash. According to statistical 3D TCAD simulation analysis, the fringing field from the control gate and the random discrete nitride trapped charges, two competitive mechanisms, are proposed to be responsible for the non-monotonic RTN behavior. As the programmed cell Vt level increases, the increasing fringing field from the control gate reduces the current-path percolation effect and the RTN amplitude. However, once the random discrete nitride trapped charges start to dominate the percolation current path, the RTN amplitude increases significantly. Instructively, the clarification of RTN competitive mechanisms contributes to compacting Vt distributions specifically in multi-level 3D NAND flash. [ABSTRACT FROM AUTHOR]

The detection of temporal correlations among event-driven data streams is widely demanded in data-intensive applications such as edge computing. In this work, temporal correlation detection is enabled by the combination of 3D NAND flash and in-memory computing. Different from mathematical scheme by covariance matrix calculation, here the detection is implemented by exploiting the physical process of charge tunneling and accumulation. Thus the intrinsic charge-trapping dynamics in 3D NAND flash can be leveraged to perform in-memory computing. The computing results are stored and imprinted in the threshold voltages of the 3D NAND device array, enabling co-existence of computation and storage in the same devices. On this basis, the validation of temporal correlation detection further paves the way for 3D NAND application in high-level non-von Neumann computing. [ABSTRACT FROM AUTHOR]

As the storage density of NAND flash increases, the reliability is significantly degraded, making NAND flash memory more sensitive to noise. Among all noise sources, retention noise is a major one. Error correction based on channel parameter estimation is an essential method to deal with retention noise. In this letter, a time-saving channel parameter estimation method for TLC NAND flash memory is proposed. The proposed method reduces estimation time by three improvements: 1) reducing fitted parameters in one iteration step; 2) using prederived values as initial guess values to decrease iteration steps; and 3) utilizing parallelism between data sensing operations and computation. Compared with the previous work, the proposed method estimates parameters with higher accuracy and lower time overhead which is verified by experimental results. [ABSTRACT FROM AUTHOR]

Experimental demonstration of unsupervised learning is realized with charge-trapping 3D NAND flash device array. The charge-trapping characteristic of the memory cell is leveraged so that the devices perform not only as non-volatile memory but also synaptic cells in hardware neural network. Experiments reveal that the 3D NAND flash devices hold good potential for neuromorphic computing because of its delicately modulated synaptic weight. Furthermore, differential pair scheme is employed to enable larger dynamic range and finer weight tunability as compared with previous works. And based on the 3D NAND array, unsupervised learning is implemented by experiments with a winner-takes-all neural network, which can achieve perfect clustering of stylized letters within tens of training epochs. Beyond that, the 3D NAND devices also exhibit highly robust reliability against various disturb during synaptic weight update. The excellent synaptic device performance and reliability altogether make solid foundation for the winner-takes-all update rule in unsupervised learning neural network. [ABSTRACT FROM AUTHOR]

This article presents a small ripple and high-efficiency wordline (WL) voltage generator to supply voltage to the selected/unselected WLs for program and read operation in 3-D NAND Flash memories. With the proposed scheme of dynamic pump clock voltage and frequency scaling, the output ripple voltage can be minimized to reduce the variation of threshold voltage of the memory cells and the efficiency can be improved to save power consumption at the same time. What is more, with the minimized ripple, the requirement for power supply rejection ratio (PSRR) of the high-voltage regulator used to provide low noise WL voltage can be reduced. The proposed WL voltage generator has been fabricated in a 0.18- $\mu \text{m}$ triple-well CMOS process and the core chip size is 0.53 mm2. While operating at a 1.8-V supply, the measurement results show that the ripple voltage is 5.5 mV at 12-V output voltage under the typical 50-pF cap load conditions of 3-D NAND Flash memories. Furthermore, the output ripple hardly varies with the increase of load current. In addition, the maximum power efficiency is 49% at 400 $\mu \text{A}$ and can be maintained over 30% in the 50–450- $\mu \text{A}$ current load range. [ABSTRACT FROM AUTHOR]

This brief presents a capacitance-less charge recycling scheme to reduce the programming power of 3D NAND Flash memory. The charge recycling is accomplished with boost capacitors inside the wordline voltage generator itself, so that no extra capacitance is required. In order to implement this scheme, a proposed multifunctional charge pump and clock control method are introduced. Besides, the multifunctional charge pump also supports stage control, which can further reduce the power consumption. A wordline voltage generator with this proposed scheme has been fabricated in a $0.18~\mu \text{m}$ BCD process, and the effective chip area is 2.4mm2. Measurement results show that the total power consumption of Incremental Step Pulse Programming (ISPP) is reduced by 18.7% compared with the conventional one. What’s more, the maximum peak current is reduced by 35%. [ABSTRACT FROM AUTHOR]

Temporary read errors (TRE) refers to the high temporary fail bit count (FBC) in the first read, when 3D NAND recovers froman idle state. This can seriously deteriorate the Quality of Service (QoS) of 3D NAND Flash-based storage devices. The characteristics and mechanism of the TRE issue of 3D NAND Flash are investigated in this work. Based on the experimental analysis, a physicalmodel is proposed to interpret the physical mechanism of TRE. When 3D NAND array recovers from an idle state, the grain boundary traps (GBTs) discharging during the idle time lead to the low GBTs occupancy, which is responsible for the high temporary FBC in the first read. Based on the physical model, a novel approach to alleviate TRE is proposed and has been validated by experiments. [ABSTRACT FROM AUTHOR]

This brief presents a programmable voltage generator with the scheme of separated dynamic clock voltage scaling for program operation in 3D NAND flash memories, where the ripple of program voltage can be minimized to reduce the variation of threshold voltage of the programmed cells. The proposed scheme drastically reduces the output ripple and improves the loop stability at the same time. What’s more, the high voltage regulator used in the conventional wordline voltage generator is not necessary anymore. The proposed generator has been implemented in a 0.18 $\mu \text{m}$ triple-well CMOS process, and the effective chip area is 0.55 mm2. Under the equivalent load conditions of 3D NAND flash, the measurement results show that the maximum ripple voltage is 2.06 mV, and the ripple is independent from clock frequency and output voltage. Moreover, the peak efficiency is about 36% at 23 V output voltage. [ABSTRACT FROM AUTHOR]

3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO2 (O1) layer thickness near poly Si channel in the tunnel layer based on SiO2/SiOxNy/SiO2 structure. The optimal thickness of O1 layer is found. Under the optimal condition, program speed increased by 19% compared with no O1 layer deposition, though erase speed is slightly decreased by about 7%, the initial threshold voltage shift is improved greatly. Experimental results demonstrate that there are complex mechanisms affected by the dielectric constant, band barrier and equivalent oxide thickness. The optimization of O1 layer is useful towards an understanding of program/erase speed and retention characteristics. [ABSTRACT FROM AUTHOR]

In this letter, threshold voltage shift model based on 3D Charge Trap NAND flash channel characteristics is built for analyzing the distribution shift and error source of algorithms at different storage time. Multi-Coding BCH based on Hot Region (MC-HR-BCH) is a scheme consists of 3 algorithms. It offers good correction capability (130 to 144 errors per 1276 bytes) based on BCH(n = 9200, k = 8192, t = 72). With the help of MC-HR-BCH, the diversity of data in storage time is well handled. [ABSTRACT FROM AUTHOR]

The mechanisms and characteristics of program noise (PN) in charge trap based 3D NAND flash memory are investigated in this work. Electron injection statistics is found to be primarily responsible for PN. Moreover, it is found that PN gets worse after program and erase (PE) cycling in 3D charge trapping memory devices. A physical model is proposed to explain the observations. After heavy cycling stress, new traps are generated in the tunnel oxide, and more charges can be trapped. As a result, program speed increases and charge centroid shifts towards the tunnel oxide, which lead to worse PN. Furthermore, the upper part of Vt distribution is broadened after heavy PE cycling. The contribution of the worse PN to the upper part broadening after cycling is studied through Monte Carlo simulation. [ABSTRACT FROM AUTHOR]

The impact of temperature on array Vth distribution was investigated in 3D NAND flash. Cell Vth distributions were obtained under different program and read temperature splits. After the page is programmed under high temperature, it is found that the high tail of Vth distribution exhibits a larger shift than the low tail, during read at different temperatures (85 °C and −25 °C). On the contrary, the low tail of Vth distribution shows a larger shift than the high tail during cross temperature read, after the page programmed under low temperature. The temperature coefficient (Tco) of cell Vth shows cell to cell variations, which can be categorized into two types. For type ①, the Tco is correlated with the selected cell Vth due to polysilicon channel. For type ②, the Tco is independent of the selected cell Vth. The corresponding impacts on Vth distribution are studied via array Monte Carlo simulation. Based on the simulation results, the above temperature dependent observations can be well modeled by the combination of both Tco variation type ① and ②. Furthermore, two optimization approaches are proposed to alleviate the Vth distribution broadening and are validated by experiments. [ABSTRACT FROM AUTHOR]

A new program scheme using an “erase-like” waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed program disturbance, and the ${V}_{\textsf {pass}}$ window can be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAD simulation and measurement in mini-array test-key device. [ABSTRACT FROM AUTHOR]

The disturbance mechanism of dummy cell during memory cell cycling has been investigated in 3D NAND flash. Edge dummy cell (DMY) threshold voltage increasing was observed during cell program and erase cycling, which leads to a reduced string current and read failure. According to experiment and TCAD analysis, two mechanisms were identified to contribute to the dummy disturbance: one is the tunneling of electrons from the adjacent gate to the trapping layer during cell erase condition, which was also observed in 2D NAND; the other one is the lateral charge spreading from the trapping layer of edge cell to DMY, which is a new observation for the junction-less 3D NAND with continuous nitride trapping layer. Furthermore, an optimal DMY bias scheme under erase operation is demonstrated to suppress the disturbance. [ABSTRACT FROM PUBLISHER]

A new read scheme is proposed to suppress read disturbance in unselected strings of three-dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppressed effectively by about 95%. Meanwhile, boosted channel potential during read operation has been preserved to improve soft programming read disturbance by more than 85% in non-adjacent unselected memory cells, owing to the reduced electric field across tunnel oxide. Compared with the conventional scheme, the proposed scheme leads to a significant improvement in read disturbance characteristics with a shorter read period as well as a simplified waveform of read operation. [ABSTRACT FROM AUTHOR]

Erase cycling induced Vt shift of top select gate transistor (TSG) and its physical mechanism are studied in 3D NAND flash memory. It is found that the distribution of TSG Vt shifts higher during memory cells erase cycling. Furthermore, the TSG Vt shift can recover after the removal of cycling stress. A physical model of trap generation induced by hot holes is proposed for above observations. It is considered that hot holes generated by high channel potential gradient during erase can break the $\equiv $ Si–H bonds at the poly-Si grain boundary and the poly-Si/SiO2 interface, causing TSG Vt tail shift and parallel shift, respectively. And the degradation can recover due to re-passivation of $\equiv $ Si–H bonds after stress removal. A TSG bias optimization scheme is demonstrated to reduce the hot holes generation and suppress the TSG abnormal Vt shift during cell erase cycling. [ABSTRACT FROM AUTHOR]