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Pedestrian Dead Reckoning (PDR) is a good alternative positioning method in Global Navigation Satellite Systems (GNSS)-challenged environments. It has the advantage in terms of infrastructure-independent, while the disadvantage is that, the estimated errors grow rapidly with time. The Digital Terrestrial Multimedia Broadcasting (DTMB) signals have strong transmission power, which contributes to better urban propagation and building penetration than GNSS signals. So, in this paper, an enhanced PDR algorithm aided with DTMB signals is proposed. In the study, a complete software-defined radio receiver is developed to estimate the Doppler speed and range information from DTMB signals. To reduce the accumulated errors of the PDR, the Extended Kalman Filter (EKF) algorithm is carried out to fuse the information of Doppler speed and ranging from the DTMB signals, as well as the information of walking speed and heading from the PDR. The results of the field tests showed that the 95% positioning error of the proposed algorithm is less than 3.94 m, while the PDR only is less than 9.19 m, which suggests the effectiveness of the proposed method to provide continuous positioning by fusing DTMB signals with PDR. [ABSTRACT FROM AUTHOR]

Online monitoring of pellet size distribution (PSD) of green pellets is an important work in product quality control of pelletization process. Conventionally, image segmentation technique is a preliminary step in computer vision-based PSD monitoring. However, haze, pellets overlapping, and uneven illumination contribute to the main challenges that severely impair the segmentation performance and PSD measurement accuracy. This article proposed a fully automatic online PSD monitoring method incorporating a K-means clustering-based haze judgment module, a lightweight U-net segmentation model with the fusion of none-weight VGG16 features (VGG16-LUnet), and a convex-hull detection and ellipse fitting model for adhesive pellet separation and contour fitting. The VGG16-LUnet model can accurately segment the pellets from both hazy and haze-free images with the help of haze judgment module. Thus, this model can be called VGG16-LUnet-TAdj. Then, a contour fitting model is applied to determine the pellets sizes based on the segmentation results, and the PSD is obtained as well. Extensive experiments on the segmentation of in situ captured green pellet images and the corresponding PSD curves demonstrate that our proposed method performs comparable or even favorable to the state-of-the-art methods. [ABSTRACT FROM AUTHOR]

Recently, sparse representation has been successfully used to identify brain networks from task-based fMRI dataset. However, when using the strategy to analyze resting-state fMRI dataset, it is still a challenge to automatically infer the group-wise brain networks under consideration of group commonalities and subject-specific characteristics. In the paper, a novel method based on dual temporal and spatial sparse representation (DTSSR) is proposed to meet this challenge. First, the brain functional networks with subject-specific characteristics are obtained via sparse representation with online dictionary learning for the fMRI time series (temporal domain) of each subject. Next, based on the current brain science knowledge, a simple mathematical model is proposed to describe the complex nonlinear dynamic coupling mechanism of the brain networks, with which the group-wise intrinsic connectivity networks (ICNs) can be inferred by sparse representation for these brain functional networks (spatial domain) of all subjects. Experiments on Leiden_2180 dataset show that most group-wise ICNs obtained by the proposed DTSSR are interpretable by current brain science knowledge and are consistent with previous literature reports. The robustness of DTSSR and the reproducibility of the results are demonstrated by experiments on three different datasets (Leiden_2180, Leiden_2200, and our own dataset). The present work also shed new light on exploring the coupling mechanism of brain networks from perspective of information science. [ABSTRACT FROM PUBLISHER]

Ballistic transport in III–V semiconductors-based p-channel double-gate MOSFETs is theoretically evaluated. The valence band structure is calculated by solving the eight-band k \cdot p Schrödinger and the Poisson equations self-consistently. A semiclassical ballistic model is employed to assess the hole transport properties. Ballistic characteristics are analyzed as a function of channel material, crystal orientation, and strain effect. The results indicate that Sb-based III–V materials can provide comparable drive current with the Ge counterpart. In addition, (110)/[ \overline 110 ] oriented devices exhibit better performance than other surface and transport directions whatever considered material. We also demonstrate that compressively strained GaSb devices outperform relaxed Ge in terms of ballistic current. According to our simulations, as effective oxide thickness scales down to 0.5 nm, both the group IV and III–V p-channel devices can be assumed to operate in the classical capacitance limits, where the ID – VG characteristics are basically governed by the transport effective mass. As a consequence, I \mathrm{\scriptscriptstyle ON} enhancement is owing to the reduced transport effective mass whether it results from alternative materials, optimized transport directions, and strain effects. [ABSTRACT FROM AUTHOR]

Hole mobility in strained ultrathin body InSb-on-insulator (InSb-OI) devices is calculated by a microscopic approach. The anisotropic valence band structures, in consideration of quantum confinement, are obtained via solving the six-band $k\cdot p$ Schrödinger and Poisson equations self-consistently. Hole mobility is calculated using the Kubo–Greenwood formula accounting for nonpolar acoustic and optical phonons, polar optical phonons, and surface roughness scatterings. The models are calibrated and verified with experimental data. The influences of body thickness and strain effect, including both biaxial and uniaxial strains, are investigated in InSb-OI devices. Our results indicate that mobility degradation occurs in both single-gate (SG) and double-gate (DG) mode when body thickness scales down below a certain range. Moreover, mobility in the DG mode outperforms that in the SG for thick body thickness, but loses its superiority over SG for extremely thin body. Compressive strain is favorable to hole mobility. Furthermore, more enhancement is achieved by uniaxial strain than biaxial strain. [ABSTRACT FROM AUTHOR]

Independent back bias in the ultrathin body and Box (UTBB) fully depleted silicon-on-insulator (FDSOI) serves as the critical knob for exploiting the performance and power tradeoffs and process/aging compensation. The effectiveness of back bias is one of the major metrics in the stages of circuit design and runtime feedback. In this article, new closed-form expressions accounting for the interface traps and short channel effects-dependent back gate capability in the UTBB FDSOI device are proposed. The developed model allows the accurate assessment of body factor (γ) with the dependence of front/back interface trap density in the ultrascaled FDSOI device, taking the impact of gate area scaling as well as quantum effects into account. It also facilitates the evaluation of back bias effectiveness variability induced by interface traps and benefits the dynamic threshold voltage strategy in terms of adaptive back-biasing for performance optimization, which is consistent with 3-D device simulations and measurements. Moreover, the results confirm that γ variability follows Pelgrom’s rule. [ABSTRACT FROM AUTHOR]

This article presents an evaluation of the photoelectric characteristic of different structured ultrathin body and buried oxide (UTBB) MOSFETs. The UTBB MOSFETs can achieve photoelectric conversion by integrating a doped well or photodiode beneath the BOX. With lightly doped well, the well-UTBB (W-UTBB) image sensor is more sensitive to illumination. On the other hand, the photodiode-UTBB (PD-UTBB) image sensor has a larger full well capacity. The influence of well doped concentration and interface traps at BOX/well on the photoelectric characteristics of both devices has been investigated. The well doped concentration has great impacts on the light sensitivity of the W-UTBB. The interface traps would increase the dark current of the W-UTBB and reduce the internal quantum efficiency (IQE) of the PD-UTBB. [ABSTRACT FROM AUTHOR]

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems. [ABSTRACT FROM AUTHOR]

Tunneling processes of ferroelectric tunnel junction (FTJ) based on metal-ferroelectric-insulator-semiconductor (MFIS) stack are studied for both n- and p-type semiconductor electrodes using experimentally calibrated model. In the model, the calculation of ON-(JON) and OFF-current (JOFF) in MFIS-FTJ considers the electron tunneling from both conduction (CBE) and valence band (VBE), and hole tunneling from the valence band (VBH). Depending on metal work function, doping concentration and remnant polarization, the conduction modes in both n- and p-type MFIS can respectively be classified according to the contribution of minority carriers in semiconductor. The optimal tunneling electroresistance (TER) (≅ JON/JOFF) for the n-type device is achieved, when semiconductor works under depletion/accumulation state driven by polarization reversal. With respect to its p-type counterpart, the accumulation/strong inversion state is preferable. The underlying physics are revealed, that if semiconductor goes into the strong inversion, the tunneling of VBH will increase the JOFF and decrease the TER ratio in n-type device, whereas the tunneling of CBE will increase the JON and thus TER ratio in p-type device. Guided by the model, the band structure engineering of MFIS structure is provided to design and optimization of FTJ performance. [ABSTRACT FROM AUTHOR]

As a typical cell structure, the cylindrical ferroelectric capacitor (CFE-cap) has been widely used in 3-D ferroelectric memories. Unlike planar ferroelectric capacitor, the CFE-cap has nonuniform electric field and polarization distribution. In this article, we investigate the impacts of the radius on the capacitance, field distribution, electrode charge densities of both the isotropic and anisotropic CFE-caps. As the inner radius increases, the CFE-cap behaves more like the planar capacitor with the same ferroelectric thickness. The results indicate that CFE-cap has an additional knob of inner radius Rin to tune its ferroelectric and electric characteristics. We have considered two kinds of CFE-caps, isotropic and anisotropic CFE-caps. The former is found to have stronger ferroelectric response than the latter, such as higher normalized capacitance and larger polarization. [ABSTRACT FROM AUTHOR]

In this article, we propose an efficient and robust spike-driven convolutional neural network (SCNN) based on the NOR flash computing array (NFCA), which is mapped by the pretrained convolutional neural network with the same structure. The spike-driven system eliminates the additional analog-to-digital/digital-to-analog (AD/DA) conversion in the NFCA-based CNN. To study the performance of the hardware implementation, an NFCA-based SCNN for the recognition of the Mixed National Institute of Standards and Technology (MNIST) data set is simulated. Simulation results illustrate that the system achieves 97.94% accuracy with the computing speed of 1 × 106 frame per second (fps). Compared with the typical mixed-signal NFCA-based CNN, the NFCA-based SCNN saves 97% area and 56% energy consumption. Moreover, the NFCA-based SCNN demonstrates great robustness to 30% image noise with less than 2% accuracy loss. The impact of random telegraph noise (RTN) is also greatly reduced in which less than 1% accuracy decrease can be achieved at the 32-nm technology node. [ABSTRACT FROM AUTHOR]

In this work, an evaluation methodology is proposed to study the impacts of state instability and retention failure of filamentary analog resistive random access memory (FA-RRAM) on the performance of deep neural networks (DNNs). Based on the methodology, an analytic model for the statistical state instability and retention behaviors is applied to evaluate the impacts of the reliability of FA-RRAM on an 11-layer FA-RRAM-based DNN for CIFAR-10 recognition. Simulations indicate that the recognition accuracy of the 11-layer DNN decreases rapidly with the increase of the baking time (t = 104s, 16.3% accuracy loss at 125 °C) due to the overlapping among neighboring resistance levels. To mitigate the accuracy loss caused by state instability and retention failure, the optimization method including the optimized synapse cell and the refresh operation scheme is developed. With the optimization method, the robustness of the FA-RRAM-based DNN is enhanced significantly in which no accuracy loss is observed even after 107s (at 125 °C, ${5} \times {10}^{{3}}$ s/refresh). [ABSTRACT FROM AUTHOR]

As a promising new generation of nonvolatile memory, HfO2-based resistive random-access memory (RRAM) has attracted extensive research. However, the problem of data retention has prevented its industrial production as embedded memory. In this paper, from the microscopic understanding, a Monte Carlo simulator is developed to investigate the effects of an oxygen reservoir layer (ORL) on the resistance instability of HfO2-based RRAM. The evolution of conductive filaments (CF) during the retention degradation is visualized by our simulation considering the physical mechanisms of oxygen ions absorbed and released by the ORL. The simulation results are further validated with experiments to provide the prediction of retention performance of RRAMs with different ORLs and operation schemes. [ABSTRACT FROM AUTHOR]

In this paper, we devise and optimize schemes for the resistive random-access memory (RRAM)-based hardware implementation of convolutional neural networks (CNNs). The key achievements are as follows: 1) a specific circuit for CNN and corresponding operation methods is presented; 2) quantization schemes for utilizing binary RRAM or RRAM with multilevel resistances as synapses are proposed, and simulations show that our CNN system percentage accuracy for the MNIST data set using multilevel RRAM and 97% accuracy using binary RRAM as synapses; 3) the influence of factors such as the number and size of kernels, as well as the device conductance variation, on the final recognition accuracy is discussed. Three ways to reduce the hardware cost are also analyzed; and 4) we implement the online learning function using the developed CNN system with a binary spike-time-dependent plasticity protocol and achieve up to 94% accuracy for the online learning tasks. [ABSTRACT FROM AUTHOR]

Aggressively scaled devices with high power density wrapped around the low thermal conductivity material in narrow space are susceptible to self-heating effect, which includes serious mutual-heating due to proximity effect in multifinger/fin FETs. Obtaining local temperature instead of equivalent lumped temperature at device/circuit level quickly is crucial for designers to accurately predict front-end-of-line reliability (i.e., hot carrier injection, bias temperature instability, and time dependent dielectric breakdown) and achieve better thermal management. In this paper, we: 1) first propose an analytical model based on multistage thermal network to address effectively the self- and mutual-heating within the device; 2) validate the multistage network and proposed analytical model by COMSOL and SPICE simulation, respectively; and 3) utilize the model to investigate local temperature rise in multifinger and multifin FETs-based inverter and ring oscillator as well as provide thermal-aware IC design guideline for self-heating and reliability optimization. The results show that the analytical multistage thermal model can predict local temperature rise and quantify nonuniform temperature difference in full-frequency range, superior to the lumped thermal model. Moreover, the model can offer quick thermal analysis at the pre-Si stage for reliability prediction and thermal-aware design. [ABSTRACT FROM AUTHOR]

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure. [ABSTRACT FROM AUTHOR]

HfOx-based resistive switching device has been explored as one of the promising candidates for the electronic synapses of neuromorphic computing systems due to its high performance, low cost, and compatibility with CMOS technology. To meet the codesign requirement of HfOx-based electronic synapses with CMOS neurons in the neuromorphic computing systems, a compact model that can capture the synaptic futures of HfOx-based resistive switching device is developed. The developed model can accurately describe the multilevel conductance transition behaviors during RESET process for depression learning as well as the binary stochastic transition behavior during SET process for potentiation learning. After the verification with experimental data, the model is used to simulate a winner-take-all neural network to classify patterns with unsupervised competitive learning algorithm. Simulation results imply that the average recognition accuracy would decrease with the increase of the resistance variation of low resistance state (LRS) due to the “trap” effect. Guided by the simulation, a synapse cell consisted of a HfOX-based device and a fixed resistor series connection is proposed to achieve almost 100% recognition accuracy even if the resistance variation of LRS is 50%. [ABSTRACT FROM PUBLISHER]

A high-K/metal gate (HKMG)-stack (TiN/Al-doped-HfOx/SiO2/Si)-based bipolar resistive random access memory (RRAM) cell is proposed and fabricated by 28/20-nm HKMG CMOS compatible technology. Robust reliability behaviors (retention at 200~ ^\circ \text C > 4 \times 10^4 s and endurance $> 10^{{{5^{\vphantom {\frac {}{,}}}}}} cycles) and ultralow switching current ( <0.1\mu \textA for RESET and <0.3\mu \textA for SET) are both demonstrated. The sub- \mu \textA switching current and self-selection nonlinear $I$ – V$ characteristics are attributed to the SiO2 interfacial layer rather than the decrease of conductive filament size and oxygen vacancy ( V_{O} ) density, which can be verified by HRTEM and measured conduction behavior. Therefore, robust reliability property is also achieved. The demonstrated excellent memory characteristics of HKMG stacked RRAM cell enable constituting 1-Mb workable crosspoint array even though the feature size scales down to 10 nm according to the HSPICE simulation. [ABSTRACT FROM AUTHOR]

A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions. [ABSTRACT FROM PUBLISHER]

3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/ $n$ architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance. [ABSTRACT FROM PUBLISHER]

A comprehensive array operation scheme for a multilayer stacked 3-D vertical resistive random access memory (RRAM) cross-point array architecture is developed. Based on the proposed READ/WRITE scheme, each memory cell in the 3-D array can be randomly accessed. The fabricated AlO\oldstyle{y}/HfO\oldstyle{x} -based bilayer vertical RRAM array with excellent device-to-device and layer-to-layer uniformity is applied to demonstrate the feasibility of the proposed operation scheme. [ABSTRACT FROM PUBLISHER]

A novel strategy based on defect engineering is proposed for high-performance multibit data storage in oxide-based resistive random access memory (RRAM). Key innovations are: 1) material-oriented cell engineering for desired modification of physical locations of generated oxygen vacancies in resistive switching layer; and 2) operation scheme to control the amount of oxygen vacancy generated in the conducting filament regions during switching. Proper doping approach is applied to suppress the formation of oxygen vacancy clusters due to the avalanching effect in the forming and set processes. Gradual resistive switching process is observed in the devices with proper doping at the proper switching operation modes. Multilevels of resistance states are measured by the optimized dc or ac switching mode. Excellent memory performance with four-level data storage (good resistance uniformity under pulse switching, retention > \10^4 s at 150 ^\circ \C, and endurance > \10^6 cycles) is successfully demonstrated in hafnium oxide-based RRAM devices, indicating the viability of the proposed engineering design strategy. The proposed methodology helps to understand the mechanism of multilevel switching and provides guidelines for the design of high-performance multibit resistive switching memory devices. [ABSTRACT FROM PUBLISHER]

The impact of back-gate bias on the statistical variability (SV) of FDSOI MOSFETs with thin buried oxide (BOX) is studied via 3-D “atomistic” drift-diffusion simulation. The impact of the principal sources of SV, i.e., random dopant fluctuations, line edge roughness, and metal gate granularity, on threshold voltage, drain-induced barrier lowering, and drive current is studied in detail. It is shown that reverse back-bias is beneficial in terms of reducing the dispersion of the off-current and the corresponding standby leakage power, whereas forward back-bias reduces the on -current variability. The correlation coefficients between relevant figures of merit and their trends against back-bias are also studied in detail, providing guidelines for the development of statistical compact models of thin-BOX FDSOI MOSFETs for low-standby-power circuit applications. [ABSTRACT FROM PUBLISHER]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]