Search

This paper describes a silicon carbide (SiC) Bipolar-CMOS-DMOS (BCD) process technology and presents the corresponding characterization results. The process enables the design of integrated circuits (ICs) capable of high temperature operation and heterogeneous integration into SiC power modules. The paper showcases the cross-section of the triple-well, single metal layer SiC BCD process and details the key process challenges. Characterization results for NMOS, PMOS, LDMOS, and BJT structures are presented. DC output characteristics of the standard 1.5 μm NMOS and PMOS are shown for temperatures of 25°C and 300°C. The drain-to-source breakdown voltages observed for the LDMOS (at 1 nA leakage) is 178 V at 25°C. The integrated passives available in the process include N-diffusion resistors with a sheet resistance of approximately 1.2 kΩ/□ and poly-to-N-diffusion capacitors with 0.612 fF/μm2 capacitance.

In order to develop electrostatic discharge (ESD) protection structures in Silicon Carbide (SiC) process, the ESD properties of SiC silicon-controlled rectifier (SCR), lateral-diffused MOS (LDMOS) and NMOS devices are reported in this paper. All devices were fabricated using Fraunhofer 4H-SiC Bipolar-CMOS-DMOS (BCD) process and characterized by transmission line pulse (TLP) system. The scalability of the failure current (I t2 ) of NMOS with multiple fingers is reported. The critical parameters (i.e. gate length and drift region) of LDMOS are varied to understand the effects on the triggering voltage and other ESD characteristics of the devices. The comparison of the I t2 between high voltage SCR (HV-SCR) and LDMOS has been investigated. TLP results show that HV-SCR structures have much higher I t2 than LDMOS structures. Cost-effective ESD protection structures can be designed by these HV-SCR devices. Furthermore, ESD characteristics of SiC HV-SCR and NMOS structures are simulated using Silvaco technology computer-aided design (TCAD) software.