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This brief gives an overview of recent advancements in CMOS automotive radar sensors, focusing on the most critical circuit design at mm-wave frequencies. Highly scaled CMOS technologies enable very low-power consumption, reduced costs, and higher data processing capacity and integration compared to state-of-the-art SiGe BiCMOS chip-set solutions commonly adopted in commercial products. The very bottleneck is still represented by the radio front-end due to the challenging requirements of long-range radars. Circuit topologies and design tradeoffs are here discussed with reference to critical building blocks of the mm-wave radar front-end, reporting circuit implementations for a 77-GHz long-range radar sensor in a 28-nm fully-depleted silicon-on-insulator CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents a 77-GHz automotive radar receiver in a 28-nm fully depleted silicon-on-insulator CMOS technology. It exploits a mixer-first direct-conversion architecture to trade-off noise and linearity performance. The receiver is composed of a 77-GHz downconverter, a variable-gain amplifier, and a switched-capacitor low-pass filter. It adopts an effective and robust approach for leakage suppression due to the TX to RX crosstalk, which overcomes both gain and linearity limitations. The receiver draws an overall quiescent current as low as 27 mA from a 1-V supply voltage and provides an overall gain up to 75 dB with a noise figure of 8.2 dB. Despite the low supply voltage, an excellent blocker immunity of −9.5 dBm is achieved along with an output 1-dB compression point as high as −1.5 dBV. [ABSTRACT FROM AUTHOR]

This article presents a $W$ -band power amplifier (PA) for automotive radar applications. It was designed in a 28-nm fully depleted silicon-on-insulator CMOS technology with a transition frequency of around 270 GHz and a standard back-end-of-line. The circuit adopts a pseudo-differential topology with coupling transformers, which allow both compact matching networks and layout-optimized interstage interconnections. The power stage exploits a transformer-based folded-cascode structure that is very suitable for low-voltage mm-wave power applications. The PA is able to deliver a saturated output power as high as 13.5 dBm at 77 GHz with a power-added efficiency of 14.5%, while using a power supply as low as 1 V. The linear power gain is 26.5 dB and the current consumption is 150 mA. The PA occupies a core die size of $700\,\,\mu \text{m}\,\,\times 200\,\,\mu \text{m}$. [ABSTRACT FROM AUTHOR]

An effective codesign approach for harvesting systems is described in this article, which is based on a CMOS differential-drive rectifier and an inductively coupled loop (ICL) antenna. The proposed approach acts on both the rectifier and the antenna and aims at optimizing the system performance in terms of efficiency and input sensitivity for a given load specification. Moreover, a rectifier solution is also proposed to enhance the circuit performance by properly driving the transistor bulks without additional components. An RF harvesting system operating at 868 MHz was implemented, which is made up of an ICL antenna on FR-4 substrate and a rectifier fabricated in the 0.13- $\mu \text{m}$ CMOS technology. Measurements in the anechoic chamber show an overall efficiency performance of 34% with an RF input power as low as −21.5 dBm while considering 2.4 V and 1 $\mu \text{A}$ as load specifications. [ABSTRACT FROM AUTHOR]

This brief presents a variable-gain amplifier (VGA) for automotive radar applications integrated in a 28-nm fully depleted (FD) silicon-on-insulator (SOI) CMOS technology. The amplifier operates at a power supply as low as 1 V and guarantees 30-dB linear-in-dB gain variation with a 3-dB step. The back-gate of the MOS transistors has been exploited to implement a back-gate control-based offset cancelation loop, thus avoiding the use of inter-stage coupling capacitors that introduce frequency limitations due to parasitic capacitances. The VGA exhibits a bandwidth from 100 kHz to 20 MHz, which is compliant with typical frequency-modulated continuous wave (FMCW) radars. It also guarantees a 1-dB compression point (${P} _{\mathrm{ 1dB}}$) better than −36 dBm and an input-referred noise (IRN) of 12.5 nV/ $\surd $ Hz and 7 nV/ $\surd $ Hz at 1 MHz and 10 MHz, respectively, with a power consumption as low as 1.7 mW. [ABSTRACT FROM AUTHOR]

This brief demonstrates a fully contactless wafer-level testing based on UHF radio identification (RFID) technology enriched by high-quality on-chip antenna. The antenna, which uses exactly the same tag IC area (i.e., 0.45 mm2), exploits a low-cost post-process consisting of a thick dielectric layer and a copper metal, thus significantly improving the quality factor with respect to a standard CMOS implementation. Contactless wafer-level testing of a tag array is performed by simultaneous inductive coupling with a customized near-field reader. With a 27-dBm standard UHF RFID reader, a reading range up to 2.5 mm is demonstrated at 865 MHz. Anti-collision algorithm and memorized x–y device coordinates allow IC identification on the wafer under test to be achieved. Thanks to its cost-effectiveness, the proposed approach can be easily extended to general purpose IC contactless testing. [ABSTRACT FROM AUTHOR]

This paper presents the design and experimental characterization of a power transfer system performing a dc–dc conversion with on-chip galvanic isolation. The converter is operated in the VHF band, which enables fully integration of all the required components in silicon technology. It consists of only two silicon dice, i.e., a power oscillator with an on-chip isolation transformer and a full-bridge rectifier, which are fabricated in 0.35–µm BCD and 0.13–µm CMOS technology, respectively. A thick SiO2 layer was used, which guarantees galvanic isolation between the transformer windings. A co-design procedure for the system building blocks is proposed, which aims at optimizing the dc–dc converter performance in terms of power efficiency at a given power density. Thanks to the adopted approach, a maximum output power up to 980 mW is demonstrated with a power efficiency of 29.6%. This paper outperforms previously reported integrated inductive step-up converters in terms of power per silicon area (up to 105 mW/mm2), while providing on-chip galvanic isolation without any discrete devices or post-processing steps. [ABSTRACT FROM PUBLISHER]

This brief presents a fully integrated dc–dc converter consisting of only two CMOS chips, which are a power oscillator with an integrated transformer and a full-bridge rectifier. A thick inter-metal oxide layer guarantees a galvanic isolation rating as high as 5 kV. A current-reuse hybrid-coupled oscillator is proposed, which is based on a three-winding tapped isolation transformer and improves both output power and silicon area occupation with respect to previous works. The converter is operated at 5-V power supply and is able to deliver up to 300-mW dc power at 10-V output voltage while exhibiting a power density and a power efficiency of 36 mW/mm2 and 24%, respectively. [ABSTRACT FROM PUBLISHER]

A high-performance ultrahigh-frequency amplitude shift keying (ASK) detector for low-power radio-frequency (RF) receivers is proposed. The circuit is based on a high-gain common-source topology with a feedback loop that provides adaptive biasing. Hence, high sensitivity and rail-to-rail input operation are achieved along with low power consumption. The detector was implemented in a standard 130-nm complementary metal–oxide–semiconductor technology. Sensitivity measurements demonstrate correct detection of a 2-Mb/s ASK-modulated 915-MHz signal with a peak level and a modulation index of around 200 mV and 5%, respectively, which means an envelope signal amplitude of as low as 5 mV. The circuit draws less than 3.4\ \mu\mboxA from a 1.2-V power supply while operating with rail-to-rail RF variations and modulation indexes from 5% to 100%. This performance makes the detector suitable for batteryless systems with RF energy harvesting. [ABSTRACT FROM AUTHOR]

This paper presents a Colpitts-based voltage-controlled oscillator (VCO) for W-band radar applications. In the proposed circuit, the oscillation signal is directly drawn from the switching transistor bases by means of the primary winding of a transformer tank, while the secondary winding drives the output buffer. This solution improves both tuning range and oscillation swing with respect to traditional millimeter-wave VCO topologies without increasing power supply. The oscillator is implemented in a 0.13-\mu\ m SiGe BiCMOS technology, along with high-frequency dividers to enable low-frequency testing. The VCO exhibits a phase noise of -\99.3 dBc/Hz at 1-MHz offset from an oscillation frequency of 76 GHz and a tuning range of 4.9% with a consumption of 65 mW at 2.5-V power supply. The VCO is also used to drive a two-stage power amplifier in a fully integrated W-band transmitter that is able to deliver an overall output power as high as 15 dBm at 76 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a pseudodifferential power amplifier for 77-GHz automotive radar. The circuit is fabricated in a SiGe HBT BiCMOS technology featuring bipolar transistors with fT/f\max of 230/280 GHz. The amplifier adopts a transformer-coupling current-reuse approach to improve both gain and efficiency. An interstacked transformer is also profitably adopted to reduce output losses due to the differential-to-single-ended conversion. The amplifier exhibits a saturated power, a peak power-added efficiency, and a gain of 14.5 dBm, 9%, and 25 dB, respectively, thus achieving a first-rate figure-of-merit as high as 4755. [ABSTRACT FROM PUBLISHER]

This paper presents a 15-dBm power amplifier for 77-GHz automotive radar applications, which is fabricated in a 0.13-\mu\ m SiGe:C BiCMOS process featuring bipolar transistors with f T / f\max of 230/280 GHz. The circuit consists of a two-stage pseudodifferential cascode with fully integrated input/output matching networks. State-of-art performance is achieved with the proposed design algorithm and layout optimization. The amplifier demonstrates a figure-of-merit of 2500 achieving a 22.5-dB power gain and a power-added efficiency of 7.5% at 77 GHz, while drawing 130 mA from a 2.5-V voltage supply. [ABSTRACT FROM AUTHOR]

The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this analysis, a wideband lumped model is developed, whose parameters are related to layout and technological data through closed-form expressions. Model accuracy is demonstrated by comparing simulated and measured S-parameters, coil inductance, magnetic coupling coefficient, and maximum available gain of several transformers with scaled layout geometry. The self-resonance frequency is also employed as a figure-of-merit to demonstrate model accuracy at very high frequency. [ABSTRACT FROM AUTHOR]

A 5-GHz transmitter front-end for 802.11a and HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-fT silicon bipolar technology. The transmitter includes a digitally controlled linear-in-dB variable-gain up-converter and a three-stage linear power amplifier. At a 3-V supply voltage, the front-end exhibits a 23.5-dBm output 1-dB compression point, 35-dB maximum power gain, and 30-dB dynamic range. The dB-linear gain error is lower than ±0.8 dB. The transmitter is able to comply with the stringent error vector magnitude requirement of the standard up to a 19-dBm output power level. [ABSTRACT FROM AUTHOR]