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Synthesizing general nonlinear sequential circuits in superconducting Single Flux Quantum (SFQ) technology is a challenging task involving the proper leveling of cyclic digraphs, handling nested feedback loops, and ensuring the full path balancing property throughout the synthesis process. This paper presents a precise definition of the level of a node in a cyclic digraph and a polynomial time algorithm for the corresponding level assignment and full path balancing in sequential SFQ circuits, including SFQ Finite State Machines (FSMs). A case study is conducted on a 3-bit counter, as an FSM, which has a power consumption of $44. 7 \mu W$ and $1. 4 \mu W$ using rapid SFQ and energy-efficient rapid RSFQ cells, respectively, with the local clock frequency of 55GHz (throughput of 11GHz) which is significantly higher than the typical CMOS clock frequencies. More results on larger SFQ circuits are also presented.

Rapid single flux quantum (RSFQ) technology promises high performance, energy efficient supercomputers to achieve DoE exascale computing. An important challenge in VLSI complexity RSFQ circuits is ultra-high speed clocking and synchronization. A methodology to support the automated design of clock distribution networks for SFQ circuits is the focus of this paper. Global clock synthesis of SFQ circuits is applied to produce a near zero skew clock network. An algorithm is presented that produces an SFQ H-tree network with asymmetric leaves to propagate the clock signal to all SFQ gates. A Python-based system with location information for the interconnects, splitters, and leaves is described. The algorithm determines the physical locations and connections within the SFQ clock network and is applicable to automated routing and clock tree synthesis.

Rapid single flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising beyond CMOS technology for exascale computing. Unlike conventional CMOS circuits, RSFQ circuits require a specific bias current delivered to each Josephson junction, making robust bias networks an issue of great importance for large scale integration. ERSFQ is an energy efficient, inductive bias scheme for RSFQ circuits, where power dissipation is drastically lowered by eliminating the bias resistors while the cell library remains unchanged. An ERSFQ bias scheme requires the introduction of multiple circuit elements — current limiting Josephson junctions, bias inductors, and Josephson transmission lines. Multiple guidelines exist for the effective design of these structures. In this paper, additional parameter guidelines and design techniques are presented to decrease physical area and dynamic power dissipation while improving bias margins. These guidelines and techniques are applicable to automating the synthesis of bias networks to enable large scale ERSFQ circuits.

RSFQ, a Josephson-junction based technology, is becoming attractive due to its low energy and high speed. Researchers have designed cells and built circuits via composition of cells. Some designs have been fabricated and their functionalities and performance verified. This hierarchical approach relies on an abstraction for characterization of cells and composition of cells to design circuits. Researchers have developed such abstractions and methods for characterization of RSFQ cells. However, some instances of cells that are certified as being robust during cell characterization fail when incorporated into circuits. This motivated this research, which we view as the first step in the development of a systematic methodology for verification of cells and circuits in emerging technologies (such as RSFQ) leading to development of more robust abstractions and methods. In this paper, we present a new method for characterization of RSFQ cells to expose a much larger set of vulnerabilities, a systematic approach for identifying the root causes of these vulnerabilities to guide the refinement of cells designs, and a new way to extend test generation approaches to perform design validation at the circuit level. We demonstrate that our new methods and tools expose a large number of vulnerabilities and help identify root causes leading to refined cell designs which almost completely eliminate these vulnerabilities. Finally, we describe our extensions of ATPG for circuit level verification and use it to verify that our refined cells can indeed be composed to create error-free circuits.

This paper presents the design of a one-bit full adder with sum and carry outputs as two single-stage gates, which could save the JJ count and the area compared with the conventional design of a full-adder. The schematics of both the Sum and Carry cells are shown in this paper along with their input and output waveforms of JSIM simulations in the time domain. The circuit cost is compared between the conventional full adder and the new single-stage adder design in terms of the area and the time. Integer dividers of several sizes are synthesized with conventional full-adder and the proposed single-stage adder to illustrate the advantages of the new design.

We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).

The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.

Historically one of the most challenging high-speed rapid single flux quantum circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums seven inputs has been designed and tested at the target clock frequency of 40 GHz and at frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output at the same target frequency was designed by combining 2 variants of 8-to-4 parallel counters. The first variant based on the 7-to-3 parallel counter, sums eight unweighted inputs, whereas the second variant sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.

The present work proposes an Automated Place and Route Methodology for asynchronous SFQ circuits using PTL lines and a commercial EDA tool, Cadence's Innovus. At the cell level, dual rail SFQ Asynchronous standard cells were developed for the MIT Lincoln Labs SFQ5ee Process to be implemented in the Place and Route methodology. Python Scripts were written that could convert single rail netlists, obtained through the synthesis tool Design Vision from Synopsys, into dual rail asynchronous cells. Automatic Place and Route of Verilog based designs using these standard cells produced layouts that passed checks for Layout vs Schematic (LVS) and Design Rule Check (DRC). Then, the transmission line lengths are back annotated from the placed and routed design into analog simulation to simulate propagation delay.

Logic design of a 16-bit bit-slice shifter for 64-bit superconducting rapid single-flux-quantum (RSFQ) microprocessors is proposed. The shifter supports three types of shift operations including logic shift, arithmetic shift and rotating shift. Each of 64-bit shift input operands is divided into four slices of 16-bit each. In order to simulate the digital function and timing of the proposed 16-bit bit-slice shifter, we design a logic-level simulation model based on the Open Dataset of CONNECT Cell Library for AIST ADP2. As the results of simulation, the information of RSFQ circuits, such as the number of Josephson junctions, area and latency of the 16-bit bit slice shifter can be obtained. The simulation results show that the proposed 16-bit bit-slice shifter can work correctly.

As the scale of RSFQ circuits increasing, signal integrity issues of interconnects become critical. It is necessary to analyze time-domain response of coupled passive transmission lines in RSFQ circuits. In this paper, a method based on finite-difference time-domain (FDTD) method and the Newton-Raphson iterative algorithm is proposed to co-analyze 2-coupled passive transmission lines and Josephson junctions. The FDTD method is used to solve the telegraph equations of coupled passive transmission lines. And the Newton-Raphson iterative algorithm is adopted to solve the nonlinear equations of the boundary conditions. The simulation and numerical results show that the proposed co-analysis method has the same accuracy as WRspice and higher efficiency than WRspice.

Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.

Josephson Junction (JJ) based superconductor logic families have been proposed and implemented to process analog and digital signals [1] for its low energy dissipation and ultrafast switching speed. Thanks to its construction of resistance-less wires and ultrafast switches, it can operate at clock frequencies of several tens of gigahertz and even hundreds of thousands of times as energy efficient as its CMOS counterparts. It has been perceived to be an important candidate to replace stateof-the-art CMOS due to the superior potential in operation speed and energy efficiency, as recognized by the U.S. IARPA C3 and SuperTools Programs and Japan MEXT-JSPS Project. The design and fabrication of superconducting circuits have already been established [2]-[4]. In addition, a prototype superconducting microprocessor "Core 1" has been demonstrated in 2004 [3], which is able to execute instructions at a high clock frequency of several tens of gigahertz, and with extremely low-power dissipation. These achievements make superconducting electronics highly promising for future high-performance computing applications. As one of the most matured superconducting technology, the Rapid-Single-Flux-Quantum (RSFQ) technology is proposed by K. Likharev, O. Mukhanoc, V. Semenov in 1985 [1]. Despite its capability to be operated at an ultra-high speed of hundreds of GHz while maintaining extremely low switching energy (10^-19 J), it suffers from an increasing static power due to on-chip resistors that are required for constant DC bias supply for the main RSFQ circuit. Numerous methods have been proposed to resolve the static power dissipation problem of RSFQ, including low-voltage RSFQ (LV-RSFQ) [5], reciprocal quantum logic (RQL) [6], LRbiased RSFQ [7] and energy-efficient single-flux quantum (eSFQ) [8]. The Adiabatic Quantum-Flux-Parametron (AQFP) technology, on the other hand, uses AC bias/excitation currents as both multiphase clock signal and power supply [9] to mitigate the power consumption overhead of DC bias while operating at a frequency of few GHz. Consequently, AQFP is remarkably energy efficient compared to RSFQ, albeit operating at a lower frequency. The energy-delay-product (EDP) of the AQFP circuits fabricated using processes such as the AIST standard process 2 (STP2) and the MIT-LL SFQ process [10], [11], is at least 200 times smaller than those of the other energy-efficient superconductor logics and is only three orders of magnitude larger than the quantum limit [9]. Physical testing results of an AQFP 8-bit carry-look-ahead adder and large scale circuits consisting up-to 10,000 AQFP logic gates have demonstrated the AQFP being a promising technology that is robust against circuit parameter variations [12]. Despite the high application potential of AQFP in VLSI circuits, a systematic, automatic synthesis framework for AQFP is imminent. There are two features of AQFP that restrict conventional CMOS synthesis methods being directly applied on AQFP. In spite of And-Or-Inverter(AOI) based representation, which conventional CMOS circuits highly relies on, AQFP circuits prefer majority gates. In fact, its two inputs AND and OR gates are also built with three inputs majority gate with one input being constant. In addition, given its clock-synchronized data propagation nature, AQFP technology requires all inputs to any gate having equal delay. In order to meet this balanced timing requirement, splitters and buffers need to be inserted to the circuit. As a matter of fact, some circuit size can be doubled even with optimum amount of buffers and splitters inserted. The buffer and splitter insertion method can have a huge impact on the overall resource consumption. As the design complexity increases, an unoptimized buffer and splitter insertion method could result in huge amount of unnecessary buffers and splitters added. In addition to a complete synthesis framework, an Integrated Development Environment (IDE) for AQFP design is also lacking. It is imminent to have an IDE for AQFP integrating tools that offer schematic and layout editor, simulation and analysis for better and more efficient AQFP design flow. In this paper, we propose a complete design tool for AQFP design including an Integrated Development Environment (IDE), a complete majority based synthesis framework and a buffer and splitter insertion framework. we propose a majority gates synthesis framework for AQFP circuits that is capable of converting any AOI netlist to its corresponding MAJ netlist by mapping all feasible three-input sub-netlists to corresponding MAJ based implementations. In addition, we also propose an automated buffer and splitter insertion method that is capable of adding the optimum amount of buffers and splitters to any given gate-level netlist. The proposed method can find the minimum amount of buffers and splitters to inserted to achieve equal delay with any library limitation on the size of splitters. Experimental results suggest that the proposed methods can deliver very optimized results. The majority conversion tool can reduce circuit size by an average of 16:47% and delay by 30:21% in average. The buffer and splitter insertion tool only introduces an average of 14:24% overhead in size and 4:70% delay with splitter fanout size limited to 4 compared to an unachievable ideal results with no limitations on splitter fan-out size. Overall, the balanced design in majority gates can be reduced by 23:85% and 29:54% in size and delay compared to its AND/OR/Inverter implemented counterpart.

Conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry, and converts them considering reduction of the number of clocked gates. It utilizes two characteristics of pulse logic for the reduction. One is utilizing confluence of pulses to realize logic-OR. The other is utilizing a small resettable DFF as an NIMPLY gate by tuning the order of pulse arrival. To minimize the number of clocked gates with minimum replacements of gates, the selection problem of gates for replacements utilizing those characteristics and assignment of logic level to each gate are formulated as an instance of integer linear programming.

In this work under the IARPA SuperTools program we developed a layout synthesis tool with scripting support. The user specifies the relative positions of Josephson junctions and inductances constrained by a user-defined cell height and cell width. Tight integration with the three-dimensional inductance extraction tool, InductEx, allows inductances to be automatically generated while meeting reasonable design values. Based on these user inputs, the tool can synthesize the physical layout of logic cells for multiple SFQ circuit technologies according to design rules and layer parameters. Furthermore, it enables the straightforward regeneration of entire cell libraries when design rules change or when libraries have to be redesigned for more advanced fabrication processes. We describe the methodology of our synthesis tool and show the results applied to both RSFQ and AQFP logic families.

An 8-bit bit-parallel RSFQ microprocessor, named HUTU, is proposed. It can execute 28 different instructions. Each instruction consists of eight bits. Harvard-type architecture is adopted for parallel processing between the control unit and the datapath. The control unit uses an asynchronous timing method to avoid pipeline flushing and to reduce the area. Concurrent-flow clocking is adopted in the datapath for high performance. The simulation result shows that the elements of HUTU run correctly.

RSFQ is an attractive technology due to its low energy and high speed. However, it is imperative to certify speed for each design (via timing verification) and each fabricated chip (via delay testing). In this paper, we describe completely new phenomena in RSFQ circuits that arise due to their unique characteristics and require the development of new concepts, methods, and tools for timing verification and delay testing. We show that single-pattern timing verification and delay testing is possible in RSFQ technology. We also show that due to the gate-level pipelined nature of RSFQ circuits, imposing a guard-band to resolve the setup time issue will reduce the performance dramatically and lose some of the speed benefits of RSFQ. More importantly, inserting scan logic for every pipelined gate in RSFQ will cause astronomical area overheads. Therefore, the increased clock-to-Q delay (i.e., timing bleed) must be allowed, and delay faults in fabricated chip must be tested for multi-cycle paths. Further, the polarity of the logic gate is an important determinant for selecting target multi-cycle path. Also, we have observed a completely new delay failure behavior in RSFQ. If the clock period is insufficient compared to circuit delays, in addition to a missing pulse at output in one clock cycle, an additional pulse can be generated in the next cycle. This provides additional opportunities to detect timing problems for timing verification and delay testing. In addition to describing above major differences from CMOS and their implications, we outline a completely new paradigm for Automatic Test Pattern Generation (ATPG) for timing verification and delay testing of RSFQ circuits.

We propose placement and routing methods integrated in automated layout design flow for rapid single-flux-quantum (RSFQ) circuits. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering proper use of JTLs and PTLs. The placement problem is divided into subproblems in order to reduce the computational cost. The placement method is composed of three steps, i.e., (i) Cell clustering, (ii) Cell placement and JTL routing in each cluster, and (iii) Cluster placement. Routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed with the proposed methods are smaller than those of the circuits designed manually.

An 8-bit bit-slice TEA-cryptographic accelerator for 64-bit RSFQ secure coprocessors is proposed. The accelerator is based on Tiny Encryption Algorithm (TEA) and mainly consists of bit-slice adders and bit-slice shifters. Synchronous concurrent-flow clocking is used to design a fully pipelined RSFQ logic design. For verifying the algorithm and the logic design, the RSFQ logic circuits of the proposed accelerator have been simulated with a target operating frequency of 50 GHz. It consists of 21 stages. The throughput is 7.672 × 107 64-bit TEA encryptions per second.

Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.

Presents a collection of slides covering the following topics: IC design; Moore's law; More than Moore; carbon nanoimprint; high-NA EUV; FinFET; CFET design; nanosheets; superconducting logic; rapid single flux quantum logic; efficient rapid single flux quantum logic; cryoCMOS; MOSFET; CMOS ME-MTJ hybrid design; ME-MTJ logic; VNAND; spintronics; and accelerator.

Rapid Single Quantum Flux (RSFQ) logic, based on Josephson Junctions (JJs), is seeing a resurgence as a way for providing high performance in the era beyond the end of physical scaling of CMOS. Since it uses fabrication processes with large feature sizes, the defect density for RSFQ is dramatically lower than its CMOS counterpart. Hence, process variations and other RSFQ-specific non-idealities become the major causes of chip failures. Because of the nature of its quantized pulse-based operation, even highly-distorted pulses are interpreted logically correctly by cells, but the timings is affected. Therefore, timing verification and delay testing increase in importance in RSFQ. In this paper, we address several radically new phenomena in RSFQ technology, especially the existence of single-pattern delay tests and the need to propagate delayed values via multiple pipeline stages. We then characterize cells under process variations and identify delay excitation conditions, sensitization conditions, and conditions for propagation of the logic errors caused by process variations. We then propose a completely new ATPG paradigm which utilizes these new phenomena to select target delay subpaths and generate test patterns that are guaranteed to excite the worst-case delay along each target delay sub-path. Finally, we present Monte Carlo simulation results for benchmark circuits with process variations to demonstrate the effectiveness of the vectors generated by our new ATPG.

Design and manufacturing of superconductive electronics have been evolving over the past three decades with significant progress made in related fields. Rapid single flux quantum (RSFQ) logic circuits have become popular among superconductive logic families and its energy-efficient variants (ERSFQ and eSFQ) have shown promise as an ultra lowpower and high-speed circuit fabric. SFQ circuits have been demonstrated at tens of GHz with an energy consumption of an attojoule per gate. There are many differences between SFQ and conventional CMOS circuits. SFQ logic circuits are based on the manipulation of the quantized magnetic flux pulses. Most of the logic gates are sequential in nature requiring the clock to be distributed to every logic gate. SFQ logic gates have no gain and hence splitters are needed to drive multiple fanouts. Design and successful demonstration of a controllable superconducting switch and a compact reliable memory element have evaded researchers so far. This paper starts by describing key differences between SFQ logic and conventional CMOS and concludes by listing key challenges that must be overcome to achieve the very large scale integration of SFQ circuits and make the demonstration of a superconductive CPU a reality.

In the beyond-CMOS era, many researchers are investigating technologies that have the potential of complementing, if not overtaking, silicon-based electronics. One of which is rapid single flux quantum (RSFQ) superconductive technology. Due to timing and uncertainties challenges, the promised benefits of three orders of magnitude lower power at an order of magnitude higher performance does not look attainable. In this paper, we propose an innovative self-adaptive clocking technique which is designed to be robust against an unprecedented variability. Whereas the traditional zero-skew clocking is not reliable for large scale RSFQ designs, our proposed hierarchical chains of homogeneous clover-leaves clocking inherits its robustness from spatially correlated cell delays and from the timing robustness of the RSFQ traditional counter-flow clocking. Our simulations on ISCAS'85 benchmark circuits show our robust clocking costs can be on average within 34% as fast as ideal zero-skew jitter-free clock trees with an average area overhead of 58%. Moreover, lower area overhead is also possible at the cost of performance, demonstrating the possible trade-off between performance and area. We assert that these overheads are acceptable given the benefits of much higher functionality and feasibility, as quantified by yield, as well as improved scalability. In particular, previous efforts [1] reported that a similar, but more limited, clocking structure leads to up to 93% higher yield than zero-skew trees.

This paper presents designs of rapid single flux quantum (RSFQ) logic cells comprising multiple (more than two) inputs and high-fanout splitters, which are subsequently utilized by an automated logic synthesis flow to reduce the area/power costs and logic depth of RSFQ logic circuits. The complex cells include multi-input AND and OR gates as well as specialized gates such as A+BC. The logic synthesis tool builds on the ABC tool, but adds features and capabilities that are unique to RSFQ circuits. Results show a sizeable reduction in the Area-Delay product of large multiplexer, decoder, and carrylook- ahead adder circuits while exhibiting small (manageable) degradation in margins.

A 4-bit bit-slice matrix multiplier for 32-bit rapid single-flux-quantum (RSFQ) artificial intelligence processors is proposed. The multiplier mainly consists of 4-bit bit-slice multipliers and 4-bit bit-slice adders. The multiplication of unsigned integer matrixes is implemented by control signals. The result shows our method simplifies the circuit complexity, reduces the hardware costs and allows extending the matrix multiplier to a smaller or larger number of bits.

RSFQ technology promises to achieve the ultra low power and high speed computing needed for future exascale supercomputing systems. One of the biggest challenges impeding the application of this technology, however, is the ultra-high-speed clocking of large scale RSFQ circuits. The clocking complexity is aggravated by algorithmic loops and generic complex pipelines, whose presence is inevitable in large scale systems. This paper presents a new clocking technique, comprised of synchronized hybrid clock loops, whose frequency is intrinsically determined by the clock architecture. This tree-free scheme reduces the area, power, and complexities associated with traditional clock distribution networks. A SystemVerilog model of the architecture is built to quantify the benefits and prove the feasibility of the proposed scheme. As an example, for a 32-gates circular shift register (CSR), under a model of moderate local and global variations, our experimental results show up to 93% yield improvement at the same cycle time compared to zero-skew tree clocking.

A test point insertion technique for enhanced testability in superconductive RSFQ logic is proposed here. Test point insertion reduces the overhead of a set/scan chain while maintaining most of the functionality. The SFQ multiplexers are replaced with mergers and blocking gates. The multiplexer control signals are replaced with a gated clock signal. Clocked blocking gates are used to disable undesired data input. The proposed technique requires 35% fewer Josephson junctions as compared to multiplexers when applied to a 64-bit register. This technique can be utilized to evaluate error prone SFQ circuits and for built-in self-test of SFQ compatible memory systems.

This paper gives a newfangled dimension to superconducting logic which is the successor of CMOS logic and other superconducting quantum logic. Reciprocal Quantum logic (RQL) is proposed to achieve the less memory capability. RQL is a modified version of Rapid Single Flux Quantum (RSFQ). We designed and analyzed different RQL logic like half adder, full adder, counter, and Carry Save Adder (CSA) and we achieved an increase in clock speed compared to RSFQ logic by 20%. The designs are made of AndOr and AnotB gate operation and analyzed using WRSPICE software.

Rapid Single Flux Quantum (RSFQ) logic cells have traditionally been limited to driving one fanout cell because of the difficulty in distributing the single flux quantum pulse to multiple fanouts. This paper presents a method to modify the standard RSFQ cells at their input/output interfaces to other cells in order to support a multiple-fanout drive capability. This capability is especially useful for clock distribution in RSFQ logic. This is because RSFQ logic is requires the clock signal to be provided to every logic gate. This is why this paper focuses on the clock signal driving more than one cell without the use of splitters. The potential tradeoff is in lower margins for the cells. However, by careful design of the RSFQ cells, the yield is not compromised by our proposed technique.

Superconductor electronics holds records for clock frequency and energy efficiency at the chip level, and is also projected to large systems that can absorb the cooling overhead. These advantages have nevertheless only managed to give this technology a back seat to CMOS digital circuits, which offer orders of magnitude more complexity. Furthermore, pursuing the CMOS paradigm with superconductor circuits would bring their clock frequency down to that of CMOS circuits. This makes superconductor technology much more open to risky innovations and even for paradigm changes. In the paper we point out that both (speed and energy efficiency) advantages of superconductor electronics could be preserved due to a unique composition of memory and logic functions of RSFQ cells. We propose to reorganize the original RSFQ cells into a new family of Memory And loGIC (MAGIC) gate/register objects that run arithmetic calculations as well as store results. The new MAGIC objects eliminate the time and energy overheads associated with the conventional transfer of computed data to memory by essentially reducing the transfer distance to zero. The new objects could serve as building blocks for distributed MAGIC-compatible architectures, differing from CMOS-like register files by processing as well as storing data. A simple Logic Unit (LU) would be sufficient to control the MAGIC registers, because the registers would provide most of the arithmetic functions and separate ALUs would not be needed. The reduction of the data exchange between logic and memory units leads to additional energy saving. Factorization of large integers is presented as an example illustrating the speed and density advantages of the new approach. The end result will be a superior technology which offers a combination of performance and energy efficiency unattainable by existing technologies or their possible extensions.

We report recent progress in the development of rapid single-flux-quantum (RSFQ) microprocessors integrated with random access memories (RAMs) based on bit-serial processing, called CORE e series. The bit-serial processing is an efficient, unique approach for RSFQ microprocessors that target ultrafast clock frequency with small hardware size. The CORE e series have a richer instruction set and RAMs integrated on the same die, and are capable of running small-scale benchmark programs. We are currently developing three microprocessors in parallel, CORE e2, e3, and e4, for different purposes including prototype demonstration, investigation on efficient use of hardware and energy, and full-function implementation. Here we describe design and implementation of the CORE e microprocessors together with a high-density shift-register-based RAM. The estimated performance of these microprocessors is 333 million instructions per second (MIPS) with 4.6-5.6 mW power.

A 4-bit bit-slice multiplier for a 32-bit rapid single-flux-quantum (RSFQ) microprocessor is proposed. It carries out both signed and unsigned integer multiplication. A fully pipelined RSFQ logic design of the multiplier using concurrent flow clocking consists of 33 stages and 17,551 Josephson junctions. The bit-slice approach simplifies the circuit complexity and reduces the hardware cost. For verification, an 8×8-bit 4-bit bit-slice multiplier based on the proposed algorithm has been designed and simulated using AIST 10-kA/cm2 1.0-μm fabrication technology. The simulation result shows correct operation at 62.5 GHz.

We designed and implemented an extremely energy- efficient hardware algorithm using adiabatic quantum- flux-parametron (AQFP) logic based on a hardware- algorithm known as the Collatz conjecture. The circuit is composed of mergers, odd- even check stages, path controllers, processing units, terminating stages, together with a feedback loop. This design is at least 3 orders of magnitude better in energy efficiency compared to rapid-single-flux-quantum (RSFQ) designs and is superior to semiconductor-based designs even when including the power dissipation of a cryocooler.

We present a simulation model for analyzing and predicting magnetic field patterns and their influence on superconductive digital circuits. Unwanted magnetic fields can cause these circuits to experience reductions in operating margins or fail completely. We use InductEx to simulate the effect of running current carrying conductors around and above the circuit under study. We also use coils to mimic ambient fields. As a test bed, D-flip flops from both RSFQ and eSFQ libraries were simulated in a roughly uniform magnetic field and the coupling to every circuit inductance is recorded. From these results we construct models that link circuit inductance and by association the bias current distribution, to applied magnetic fields.

We report an energy-efficient bit-serial microprocessor based on single-flux-quantum (SFQ) logic, called CORE e3, using a low-voltage bias technique. This microprocessor was designed for integrating memories, and we developed it to investigate the efficient use of hardware and energy, using the low-voltage rapid single-flux-quantum (LV-RSFQ) technique. We implemented the CORE e3 and its test circuit using a 10-kA/cm2 Nb process. We confirmed via logic simulations that all instructions were executed correctly with a 1-GHz system clock. We expect a 3.51 fold improvement in energy efficiency.

There are several limitations on RSFQ circuit parameters determining their margins in critical conditions. We thoroughly investigated the sequential operation of the basic RSFQ circuits and study the corresponding behavior by comparing the measurable variables such as current response while modifying the eligible circuit's parameters. We introduce some figures of merit such as current level stability, current fluctuation damping after each pulse and circuit sensitivity, leading to obtain optimized parameters. A NDRO, cell based on T Flip-Flop (TFF), is particularly selected to verify the procedure. The optimized parameters are achieved by software simulation, considering the figures of merit. We also calculated the critical margins for main parameters in which the circuit is still remain stable.

The integration of superconductor digital electronics together with superconducting sensors can enable smart multi-channel sensor arrays. Applications of such sensors range from basic astrophysical research to advanced security screening devices. The main advantage of superconducting sensor interfaces is the very low power consumption in combination with a very low noise level; both are required in order to keep the excellent superconducting sensor performance without distortions. The FLUXONICS Foundry technology has been optimized with respect to electronic interfaces circuits for analogue sensor readout and signal multiplexing. In this work, we describe this new interface technology and present a comparison with our standard RSFQ technology.

As a part of the 8-bit RSFQ processor datapath development, we have designed, fabricated, and experimentally demonstrated an 8×8-bit RSFQ multi-port register file. The register file provides input data operands and stores Arithmetic Logic Unit (ALU) results. It can perform two simultaneous non-destructive “read” operations and one “write” operation and is capable of storing eight 8-bit words. The distinct feature of the design is an extensive use of passive transmission lines (PTLs) for very complex interconnects inside the register file. The register file is designed for integration with recently demonstrated 20-GHz 8-bit RSFQ ALU. It is fabricated with the standard HYPRES's 1.0-um 4.5-kA/cm2 process. The circuit is placed on a 1 cm × 1 cm chip and consists of ~4,000 Josephson junctions.

A method has been developped to take into account the presence of a local external magnetic field in Superconducting Quantum Interference Devices (SQUIDs) loops composing Rapid Single-Flux-Quantum (RSFQ) circuits, through modifications of circuit inductances. A good agreement is observed between analytical formulas and simulations performed by time-domain softwares. The agreement with the first experiments is still only qualitative at this stage.

We present a new design technique of rapid single-flux-quantum (RSFQ) logic gates for low-noise, high-speed operation. In this study, we propose the use of a damping resistor shared with a junction pair composing a comparator, in addition to their individual shunt resistors increased from the standard values. We analyzed timing characteristics and bit error rates (BERs) of several RSFQ flip-flops composed of the proposed comparators using numerical simulation. The proposed comparator showed reduced timing jitter by ~5% in association with small delay time, sharpened BER curves, and improvement in operating margins by 2-3% compared to the standard design. We fabricated 2-bit shift registers using the noise reduction technique. We obtained sharp BER curves from the measurement. The proposed method indicated that it gave wide margins.

We report experimental results of bit-error-rate (BER) measurements in small-critical-current or lowered-biasvoltage rapid single-flux-quantum (RSFQ) circuits for power reduction. In such reduced-power RSFQ circuits, the BERs can be increased because of the reduced signal-to-noise ratio. We fabricated 2-bit shift registers using a 2.5-kA/cm2 niobium process, and measured BERs by low-frequency tests at 4.2 K. We obtained sufficiently wide bias margins when we reduced the critical currents in a range of 1/2 to 1/4 of the conventional design, while it narrowed as the critical currents reduced to 1/8. For low-voltage shift registers, the bias margins linearly decreased in width as bias voltages were lowered. We found that 0.25 mV, 1/10 of the conventional design, was a good bias voltage to balance competing power reduction and bias margin.

We develop an energy efficient digital data link connecting cryogenic superconducting single flux quantum (SFQ) circuits to room-temperature electronics. The design is based on low-temperature (4 K) superconductor ERSFQ SFQ/dc drivers, high-temperature superconductor data cables spanning 4 K to 70 K temperature stages, mid-temperature (70 K) polarization modulation vertical cavity surface emitting lasers (PM VCSELs), and fiber optic links to room temperature electronics. The Energy-efficient Cryogenic Optical (ECO) data link design is based on balancing power dissipation and signal gain at each temperature stage to maximize overall energy efficiency following the recently introduced Thermo-Gain Rule. To achieve VCSEL light emission with two switchable distinct polarization modes, a cruciform-shaped anisotropic optical cavity is formed by fabrication of a photonic crystal with etched periodic air holes surrounding the unetched cruciform region. In this report, we present the results of design, fabrication, and preliminary testing of the ECO data link components.

The development of an RSFQ cell library for the world's fastest superconducting digital family is hereby presented. Cells ranging from the basic JTL to the more complex NOR gate were laid out and are ready for fabrication. In addition, cell parameters were carefully estimated and inductance extracted using special software tools. To ensure that the cells work with known parameter margins, on-chip testing of these cells are done in the laboratory. Cells ready for fabrication include the JTL, Splitter, Merger, PTL Driver and Receiver, T-flip flop, D-flip flop, OR, NOR, AND, XOR and the NOT, with the XNOR and NAND to be developed next. We discuss test steps and verification of the cells

A wide variety of applications, ranging from radio-frequency (RF) receivers for broadband communications and signal detection, on earth and in space, would benefit from high-performance superconductor analog-to-digital converters (ADCs), based on magnetic flux quantization and fast switching Josephson junctions. Superconductor ADCs are capable of very high sample rates (100 GHz or more), very high linearity, and high sensitivity. Nyquist-rate ADCs use the high sample rate to digitize a wide instantaneous bandwidth (tens of GHz) and are useful for wideband spectrum monitoring as well as high-end scientific instrumentation. Delta and delta-sigma oversampling ADCs use the high linearity to achieve programmable trade-off between dynamic range and instantaneous bandwidth. These lowpass and bandpass ADCs have been used for direct digitization of narrower (tens to hundreds of MHz) RF bands in the 1–20 GHz range for a variety of communications, intelligence, electronic warfare, and radar applications. Another application area of these cryogenic ADCs is for outputs of cryogenic sensor arrays and terahertz mixers. Recent advances in various classes of ADCs for different applications are described.

The Rapid Single-Flux-Quantum logic (RSFQ) presents an efficient way to achieve ultra fast digital operations. This logic uses the macroscopic effects which can be found in nano-structured superconductor devices such as the Josephson AC and DC effects, and the magnetic flux quantization. As the typical time of the Josephson junction quantized phase leap 2π is in the order of picoseconds, the RSFQ circuits can operate with clock frequencies in the order of hundreds of GHz. This invited paper focuses on basic principles of superconducting RSFQ logic as well as on typical applications, such as the signal conversion or petaflops computing systems. In addition we point out the benefits of the semi-metallic NbN-Ta x N-NbN Josephson junction technology, which has been developed at CEA-INAC in Grenoble.

We report on the first direct detection of submillimeter waves emitted by small parallel tunnel junction arrays. The arrays made up of 10 and 20 Nb/Al-AlOx/Nb junctions of 6 µm2 is integrated and coupled in RF to Nb/Al-AlOx/Nb twin junction-based detector by a microstrip/slotline transition. The detector's I-V curve exhibits clearly photonassisted steps when the array is biased on the corresponding Josephson resonance at 390 and 480 GHz. These results are of particular significance in the light of previous work done on this type of devices. The arrays are specially suited for applications such as clock for RSFQ electronics or as local oscillator for THz superconducting integrated receivers.