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This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors. [ABSTRACT FROM AUTHOR]

This paper presents the effect of different elastic acoustic and inelastic optical electron–phonon interaction mechanisms on quantum transport and electrical characteristics of multigate silicon nanowire FETs. A 3-D quantum–mechanical device simulator based on the nonequilibrium Green's function formalism in the uncoupled mode space that can handle electron–phonon interactions has been developed to extract the physical parameters of the devices. The electron–phonon scattering has been treated by using the self-consistent Born approximation and deformation potential theory. Utilizing this simulator, we show that interaction of the carriers with optical phonons redistributes the energy and momentum of electrons in the transport direction, depending on the energy of the phonon. Optical phonons cause either a reduction of the electron density or an increase of the electron concentration in the channel region, depending on the phonon energy and coupling strength. Finally, we show that the critical length for carriers to get backscattered in the silicon nanowire is directly proportional to the phonon energy. [ABSTRACT FROM AUTHOR]

We investigate the effect of symmetrical geometrical constrictions on the electrical characteristics of ultrathin silicon-on-insulator nanowires with a trigate structure using a 3-D numerical quantum simulator. Introducing barriers at the source and drain junctions profoundly alter the device physics and a transition from 1-D to 0-D quantum behavior is observed. The constrictions create resonance levels in the channel region of nanowire due to confinement in the three directions of space, which, in turn, causes oscillation of the ID–VGS characteristic. Based on the observed characteristics, we derive a set of parameters that draws the line between 1-D and 0-D quantum behavior of silicon nanowire transistors. [ABSTRACT FROM AUTHOR]

We investigate planar fully depleted silicon-on-insulator (SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/ LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/ LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at Vdd = 1 V. The shift of the threshold voltage ΔVth with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported. [ABSTRACT FROM AUTHOR]

In this paper, we simulate quantum transport in trigate silicon-on-insulator (SOI) nanowire field-effect transistors using 3-D numerical simulations. The formation of 1-D subbands in SOI nanowire, which results in the oscillation of the current and transconductance characteristic at low temperatures, has been studied in detail. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased, thereby enabling the experimental evaluation of the subband energy spacing in nanowire structures (subband spectroscopy). [ABSTRACT FROM AUTHOR]

This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and ON--OFF current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation- mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased. [ABSTRACT FROM AUTHOR]