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The nanorod/nanowire arrays of narrow-bandgap semiconductors are a kind of great potential light-harvesting material for photovoltaic devices due to their excellent optoelectrical properties. Here, a $\gamma $ -butyrolactone (GBL) solution-processed inorganic Sb2S3 nanorods on the TiO2 film is developed to fabricate light-harvesting layer for efficient inorganic Sb2S3/TiO2 semiconductor heterojunction thin film solar cells. The morphology, absorption properties, crystallinity and grain orientation of the Sb2S3 nanorods heterojunction film is investigated by scanning electron microscopy (SEM), ultraviolet-visible spectroscopy (UV-vis), X-ray diffraction (XRD) techniques. The inorganic Sb2S3/TiO2 nanorods heterojunction thin film solar cells deliver a champion power conversion efficiency of 4.14%, which is a considerable efficiency for the solar cells based on GBL solution-processed inorganic Sb2S3 nanorods heterojunction thin film. [ABSTRACT FROM AUTHOR]

Lateral III–V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/ $\mu \text{m}$ , ON-resistance down to $265 \Omega \cdot \mu \text{m}$ , and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25% device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an inductive peaking output. The input stage shows up to 4-dB gain and 2.5-dB noise figure (NF), at 60 GHz. Utilizing gate-length scaling in the circuit environment, the obtained normalized intrinsic gate capacitance value of 0.34-aF/nm gate length, per NW, corresponds well to the predicted theoretical value, demonstrating the circuit’s ability to provide intrinsic device parameters. This is the first mm-wave validation of noise models for III–V LNW MOSFETs. The results demonstrate the potential for utilization of the technology platform for low-noise applications. [ABSTRACT FROM AUTHOR]

This paper presents a 1-2 K cryogenic system for cooling the superconducting nanowire single-photon detector (SNSPD). The system is based on the Stirling-type pulse tube cryocooler (SPTC) and the Joule-Thompson (JT) cryocooler technologies and thus named as the hybrid cryogenic system. It eliminates any moving component at the cold end which endows it with evident advantages over the Gifford-McMahon (GM) cryocooler in terms of low vibration, low electromagnetic interference (EMI) and long life. It can operate at 1-2 K and has an expected mean-time-to-failure of 10 years. The overall weight is below 30 kg, which makes it an attractive cryocooler candidate for the space applications. Furthermore, the operating temperature can be adjusted conveniently for the SNSPD other than being at a fixed temperature as the superfluid helium does. The design approaches and system integration are described in detail, and the performance characteristics presented and discussed. The cooling system has an experimental cooling temperature of 1.52 K. It is also expected to reach 1 K and below provided that the further performance improvement is conducted. [ABSTRACT FROM AUTHOR]

The near-infrared (NIR) polarized photodetector has wide range of applications including the object identification. Wavelength of 1550 nm is the least loss band for transmission communication, and the study of photodetectors working at 1550 nm demonstrate special scientific and applied significances. GaSb has attracted tremendous attention in the field of photoelectric detection due to its suitbale band gap, high mobility, sensitivity, and good compatibility with modern microelectronics technology. In this work, a highly polarization-sensitive GaSb nanowire-based photodetectors under short-wave near-infrared photoelectric detection is achieved. The device has a good optical detection ability in the near-infrared band, and showed the responsivity up to 77.3 A/W with the external quantum efficiency of 6.18 × 103 % (illumination intensity of 1.59 mW/mm2) under 1550 nm. Furthermore, obvious photocurrent anisotropy are investigated under the near-infrared band from 808 nm to 1550 nm. The largest dichroic ratio reaches 3.3 at 1550 nm. These results indicate that GaSb nanowire based photodetectors are not only promising candidates for NIR detection but also have promising potentials in polarization sensitive applications. [ABSTRACT FROM AUTHOR]

We investigated the effect of rare-earth (RE) element doping on magnetodynamic properties of 1D Ni80Fe20 (Py) nanowires. 5% of doping of RE element (La, Nd, and Sm) in Py nanowires was successfully done by electrodeposition technique in porous anodic alumina template. It is observed by the X-ray diffraction (XRD) measurements that the crystal structure of Py nanowires decreases from polycrystalline to amorphous phase with doping of RE element. The magnetic properties demonstrated that the saturation magnetization decreases upto 98% with the higher atomic number RE dopant. The ferromagnetic resonance measurements in field-sweep mode were done to analyze the magnetization dynamics of RE-doped nanowires. The fitting of resonance field and field linewidth was done by using the Landau–Lifshitz–Gilbert equation. It is observed that the resonance field increases with Sm doping as compared to La doping. The damping constants have been achieved by decocting the extrinsic linewidth and found to increase by ~12 times with RE doping. The increase of Gilbert damping emanates from the enhancement of L–S coupling in Py nanowires. [ABSTRACT FROM AUTHOR]

Happach, M., +, JQE Feb. 2020 2000107 InP Membrane on Silicon (IMOS) Photonics. van der Tol, J.J.G.M., +, JQE Feb. 2020 6300107 JQE Special Virtual Issue Dedicated to the 21 st European Conference on Integrated Optics (ECIO). Arefin, R., +, JQE Aug. 2020 6300309 InP Membrane on Silicon (IMOS) Photonics. van der Tol, J.J.G.M., +, JQE Feb. 2020 6300107 Sensitivity Enhancement Factor for Gain-Assisted Cavity Enhanced Spectroscopy. Tong, Y., +, JQE Feb. 2020 8400107 Special issues and sections JQE Special Virtual Issue Dedicated to the 21 st European Conference on Integrated Optics (ECIO). Arefin, R., +, JQE Aug. 2020 6300309 InP Membrane on Silicon (IMOS) Photonics. van der Tol, J.J.G.M., +, JQE Feb. 2020 6300107 Micron and Nano-Dimensioned Silicon LEDs Emitting at 650 and 750-850 nm Wavelengths in Standard Si Integrated Circuitry. Hamad, W., +, JQE Feb. 2020 2400111 InP Membrane on Silicon (IMOS) Photonics. van der Tol, J.J.G.M., +, JQE Feb. 2020 6300107 MEMS-Enabled Silicon Photonic Integrated Devices and Circuits. [Extracted from the article]

Although Ti3AlC2Tx has been widely studied in applications such as electrical storage devices, there are very few reports about the field emission properties of Ti3AlC2Tx. In this work, 2-D Ti3AlC2Tx MXene was fabricated by simple etching Al layer from Ti3AlC2 in hydrofluoric acid (HF) at room temperature and employed as a cold cathode for field emission devices. The device presents a high field emission performance with a low turn-on field of 2.7 V/μm and excellent stability, much lower than the reported value of the former work (around 5 V/μm), its relative 1-D TiC nanowires (7.1 V/μm), and most of other 2-D cathode materials, such as MoS2 and graphene, which is found due to its unique accordion structure with evenly distributed sharp edges and enlarged layer spacing reducing the field screening effect. The results confirmed by numerical simulation demonstrate that the local electric intensity at sharp edges indeed significantly higher than that of elsewhere. In other words, more sharp edges owning to the increased interlayer spacing exposed, which can considerably boost field emission performance. Based on experimental data and simulation analysis, the edge effect was found to correspond well with other former reports. Hence, 2-D MXene can be a promising candidate for vacuum electronic applications other than energy storage and conversion devices. [ABSTRACT FROM AUTHOR]

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer. [ABSTRACT FROM AUTHOR]

The number of interface traps (${N}_{\textit {it}}$) in a gate-all-around (GAA) MOSFET that harnesses an inherent floating body, was analyzed by using the synchronized optical charge pumping (SOCP) technique. By synchronizing control timing between the MOSFET operation and optical stimulation by light, holes generated by light illumination dominantly vanished, due to surface recombination with interface traps, rather than bulk recombination in a silicon nanowire and source/drain back-diffusion. This SOCP characterized the ${N}_{\textit {it}}$ without the aid of any additional specified test structure. To demonstrate an application, the amount of interface traps originating from off-state stress was quantitatively extracted by the SOCP. [ABSTRACT FROM AUTHOR]

III-V vertical nanowire MOSFETs (VNW-FETs) have the potential to extend Moore’s law owing to their excellent material properties. To integrate highly scaled memory cells coupled with high performance selectors at minimal memory cell area, it is attractive to integrate low-power resistive random access memory (RRAM) cells directly on to III-V VNW-FETs. In this work, we report the experimental demonstration of successful RRAM integration with III-V VNW-FETs. The combined use of VNW-FET drain metal electrode and the RRAM bottom electrode reduces the process complexity and maintains material compatibility. The vertical nanowire geometry allows the RRAM cell area to be aggressively scaled down to $0.01~\mu ^{m2}$ enabling realization of dense memory (1T1R) cross-point arrays on silicon. [ABSTRACT FROM AUTHOR]

Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high ${I}_{\text {on}}$. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable ${g}_{\text {m}}$ down to ${L}_{\text {g}} =25$ nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate ${g}_{m} =3.1$ mS/ $\mu \text{m}$ and ${R}_{\text {on}} = 190\,\,\Omega \mu \text{m}$. This is the highest ${g}_{\text {m}}$ demonstrated on Si. Transmission line measurement verifies a low contact resistance with ${R}_{\text {C}} = 115\,\,\Omega \mu \text{m}$ , demonstrating that most of the MOSFET access resistance is located in the contact regions. [ABSTRACT FROM AUTHOR]

Among the III-V semiconductor materials, indium arsenide (InAs) nanowire (NWs) with high carrier mobility are expected to be alternative channels for high-performance and low-power field-effect transistors (FETs). However, there is a challenge in enhancing the on-state current for the InAs NW-channel vertical gate-all-around (VGAA) structures on Si. We investigated vertical InAs/InP core-shell (CS) NW-channels to enhance the current and demonstrated InAs/InP CS NW VGAA FETs. The InAs/InP CS NW-channel enhanced the on-state current while maintaining a small off-leakage current. The devices showed an on-state current of 40 $\mu \text{A}/\mu \text{m}$ , off-leakage current of 1 pA/ $\mu \text{m}$ , and subthreshold slope of 111 mV/dec at $\text{V}_{\text {DS}} =0.50$ V. The origin of the current enhancement suggests that there is a formation of two-dimensional electron gas (2DEG) in the InAs/InP CS NW-channel, and the characteristics of the InAs/InP CS NW VGAA FET revealed that the InP interlayer at draian edge and low source resistivity are important parameters to take advantage of 2DEG for CS NW VGAA FET. [ABSTRACT FROM AUTHOR]

A series of highly ordered multilayer [FeCoCu/Cu(x)]30 ($0 \le x \le 40$ nm with FeCoCu layer thickness fixed 1000 ± 100 nm) nanowire arrays in alumina membrane (200 nm diameter) was fabricated by electrodeposition from a single electrolytic bath. The body-centered cubic (bcc) phase of FeCoCu-alloy separated by a well-defined face-centered cubic (fcc) phase of Cu spacer is confirmed by high-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) analysis. The objective of the present investigation is to tune the magnetic properties through inter- and intra-wire interactions between the FeCoCu layers separated by non-magnetic Cu(x) layers in the multilayer nanowire array. Ferromagnetic resonance (FMR) study was performed in a flip-chip geometry to explore the magnetization dynamics. FMR measurements confirm the decrease of resonance field ($H_{r}$), whereas resonance linewidth ($\Delta H$) and FMR absorption increase with the increase in the Cu layer thickness. It may be argued that through inter-/intra-nanowires interactions, the Landau–Lifshitz–Gilbert damping provides the most physically sensible magnetization relaxation in multi-layered nanowires system. The values of the Gilbert damping parameters (intrinsic and extrinsic), obtained from the FMR linewidth analysis, exhibit a decrease from FeCoCu nanowire to [FeCoCu/Cu(5 nm)] nanowire. With further increase in the Cu thickness, both these parameters were observed to have increased. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$. The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$. Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors. [ABSTRACT FROM AUTHOR]

In this article, we present a theoretical analysis of a junctionless (JL), ion-sensitive, field-effect-transistor (ISFET), self-consistently combining the electrochemical interaction between the semiconductor–insulator interface and the surrounding electrolyte medium. Incorporating charge-based core relationships for the nanowire (NW) and planar double gate (DG) JL FETs with basic relations governing the electrolyte–insulator proton exchanges, we predict the output characteristics of the NW and DG JL ISFETs with respect to pH for all the regions of operation. This hybrid charge-based approach of JL ISFETs is fully validated by COMSOL Multiphysics simulations without the need to introduce any fitting parameters. These developments are suitable for implementation in circuit simulators as well as for fast prototyping by tuning the technological parameters and estimate their impact on the device performances, including the electrolyte medium. [ABSTRACT FROM AUTHOR]

In the past couple of years, GaN-based vertical FETs have been explored to complement their potential logic applicability along with its well-known advantages in high-power and RF applications. In this article, the performances of short-channel gate-all-around (GAA) GaN vertical nanowire MOSFETs, fabricated for a possible low-voltage logic application, have been investigated via simulation, assuming the multilevel trapping effects at the gate interface and the self-heating effects. The simulation results reveal that shallow traps at the interface increase the OFF-state current, the subthreshold swing, and the drain-induced barrier lowering, while deep traps at the interface lower the ON-state current and cause the threshold voltage instability. When the gate voltage is higher than the flat-band voltage of the nanowire channel in the saturation region of operation, the mobility degradation, related to the self-heating, becomes significant due to the increased incorporation of the optical phonon scattering. [ABSTRACT FROM AUTHOR]

High-voltage thin-film transistors (HV-TFTs) based on amorphous InGaZnO (a-IGZO) are demonstrated to work in the range of kilo-voltage (kV). The devices feature a high breakdown voltage of over 1.1 kV, on-current of 10.8 $\mu \text{A}$ , and an on/off current ratio over 105. By integrating kV-TFTs with ZnO nanowires, actively controlled field emitters are obtained that exhibit extremely small current fluctuation in the emission current (2.4 % for 3600s). The operating mechanisms of the HV-TFTs are investigated by in-situ measurement of channel potentials and simple equations are derived to describe the current–voltage relations. This study demonstrates the feasibility of using a-IGZO in HV-TFTs that drive large-area field-emitter arrays and provide general understanding and design rules for HV-TFTs designed to drive nanowire field emitters. [ABSTRACT FROM AUTHOR]

In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges (ITCs) on dopingless (DL) NW-based device have been addressed for the first time. CP technique is used to induce charge carriers within the drain/source regions by depositing layers of metals with specific work function. Linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points are calculated including the effects of ITCs on the cylindrical channel–surround gate–oxide interface. This work shows that positive ITCs can help in improving the device characteristics, whereas negative ITCs degrade the device performance. The ON-state current to OFF-state current ratio decreases for either polarity of ITCs. The ON-state current has been improved by approximately 50% with higher positive ITCs. The presence of positive ITCs in DL NWTFET improves the driving capability to be used for analog applications. The linearity parameters tend to improve with positive ITCs and degrade with negative ITCs. The proposed device has reached the same cutoff frequency at lower operating gate bias (approximately 0.8 V) with half the threshold voltage for higher positive ITCs. [ABSTRACT FROM AUTHOR]

In this paper, we report the characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz. The self-heating effect (SHE) in NWFETs is investigated experimentally using the small-signal output conductance (${g}_{{\text {ds}}}$) technique. The frequency-dependent complex thermal impedance, ${Z}_{{\text {th}}}({f})$ , is extracted by fitting an ${n}$ th-order thermal network with the experimental data. We show that the temperature rise $\Delta {T}$ (=85 °C) due to SHE is significant in short-channel silicon on insulator (SOI) NWFETs. Finally, we have evaluated the RF figure of merit (FOM) for these NWFETs as ${f}_{T}$ (=70 GHz) and ${f}_{\text {max}}$ (=80 GHz). We also report the RF performance metric sensitivity on temperature, $\partial {f}_{\text {max}}/\partial {T}_{{\text {amb}}}$ ($\approx -0.104$ GHz/K). The reported BSIM-CMG compact model shows a good correlation with the measurement data. [ABSTRACT FROM AUTHOR]

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III–V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes. [ABSTRACT FROM AUTHOR]

This letter demonstrates a novel enhancement-mode (E-mode) tri-gate nanowire InAlN/GaN MOSHEMT with ultrasonic spray pyrolysis deposition (USPD) deposited Al2O3 as the gate dielectric layer. The proposed device reveals a threshold voltage (${V}_{\text {TH}}$) of +2.3 V and a maximum drain current (${I}_{D, \text {max}}$) of 705 mA/mm. It also exhibits superior electrical performances, including a high ON-state/ OFF-state current (${I}_{ {{ \scriptscriptstyle {\text {ON}}}}}/{I}_{ {{ \scriptscriptstyle {\text {OFF}}}}}$) ratio of 109–1010, a steep subthreshold swing (SS) of 65 mV/decade, and a large breakdown voltage (BV) of 800 V with a leakage current of 0.7 $\mu \text{A}$ /mm while keeping a low-specific ON-resistance (${R}_{ {{ \scriptscriptstyle {\text {ON}}}}, \text {sp}}$) of 1.04 $\text{m}\Omega \cdot \text {cm}^{\text {2}}$. This novel E-mode device presents a great potential for power device applications. [ABSTRACT FROM AUTHOR]

Nanowire transistors are typically undoped devices whose characteristics depend strongly on the injection of carriers from the electrical contacts. In this letter, we fabricate and characterize SiGe nanowire transistors with an n-p-n doping profile and with a top gate covering only the p-doped section of the nanowire. For each device, we locate the p-segment with scanning capacitance microscopy, where the p-segment position varies along the channel due to the stochastic nature of our dropcast fabrication technique. The current–voltage characteristics for a series of transistors with different gate positions reveal that the on/off ratios for electrons is the highest when the gated p-type section is closest to the source contact, whereas the on/off ratios for holes is the highest when the gated p-type section is closest to the drain contact. [ABSTRACT FROM AUTHOR]

Considering the demand of III–V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson–Schrödinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III–V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics-based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes and materials using the data from the 2-D PS solver and found to be accurate. [ABSTRACT FROM AUTHOR]

Majorana fermions are particles identical to their antiparticles proposed theoretically in 1937 by Ettore Majorana as real solutions of the Dirac equation. Alexei Kitaev suggested that Majorana particles should emerge in condensed matter systems as zero mode excitations in one-dimensional (1-D) p-wave superconductors, with possible applications in quantum computation due to their non-abelian statistics. The search for Majorana zero modes in condensed matter systems led to one of the first realistic models based in a semiconductor nanowire with high spin-orbit coupling, induced superconducting s-wave pairing, and Zeeman splitting. Soon, it was realized that size-quantization effects should generate subbands in these systems that could even allow the emergence of more than one Majorana mode at each edge, resulting in a zero bias peak on the differential conductance with a different shape from the predicted by simplified theoretical models. In this paper, we provide a connection between a finite-size nanowire with two occupied subbands and a 2-band Kitaev chain, and discuss the advantage of a 1-D model to understand the phenomenology of the system, including the presence of a hidden chiral symmetry and its similarity with a spinfull Kitaev chain under a magnetic field. [ABSTRACT FROM AUTHOR]

The space-charge region (SCR) in semiconductor bulk and nanoscale junctions is mostly analyzed using the differential equation, namely, Poisson's equation. We explore an alternate analysis using the integral equation, namely, Coulomb's law, and show its superiority to the differential equation approach in revealing the drastic change in SCR electrostatics from bulk to single nanofilm (NF) to single nanowire/nanotube(NW/NT) junction. The advantages of the integral equation approach are as follows. First, it helps us to view the junction SCR in bulk as a series of sheet charges, that in thin NFs as a series of line charges, and that in thin NWs/NTs as a series of point charges; such a view logically yields the different functional forms of the depletion width dependence on dielectric constant, potential drop, and inverse doping, namely, squareroot in bulk, linear in NFs, and exponential in NWs/NTs. Second, it shows that the partially depleted space-charge tails in NFs/NWs/NTs must extend to infinity, and that these tails rather than the completely depleted regions set up the required potential difference across the junction; it also reveals that for large distance, z away from the junction, the field varies as 1/z² in NF and 1/z³ in NW/NT, and the potential/charge vary as 1/z inNF and 1/z² in NW/NT. To ensure accuracy of the depletion width model, we capture the effect of space-charge tails in NFs/NWs/NTs by employing a periodic charge distribution. We also show how prior works overestimated the depletion width by orders of magnitude. [ABSTRACT FROM AUTHOR]

We study the performance of GaN nanowire n-MOSFETs (GaN-NW-nFETs) with a channel length, Lg = 5 nm based on fully ballistic quantum transport simulations. Our simulation results show high I ${} _{\textsf {ON}} = 1137 \mu \text{A}/\mu \text{m} and excellent on-off characteristics with Q = \,\, \textg\textsf {m} /SS = \,\, 188\mu \text{S} -decade/ \mu \textm -mV calculated for I ${} _{\mathrm{\scriptscriptstyle OFF}} = 1$ nA/ \mu \textm and V ${} _{\textsf {GS}} = \textsf {V}_{\textsf {DS}} = \textsf {V}_{\textsf {CC}} = 0.5$ V. These results represent: 1) ~ 15% higher \text{I}_{\mathrm{\scriptscriptstyle ON}} than Si-NW-nFET and 2) ~ 17% better Q than Si-NW-nFET, all with Lg = 5 nm, thus suggesting the GaN n-channel, an intriguing option for application in logic at sub-10-nm channel length. The superior performance of the GaN channel compared with Si and other semiconductors at this scaled dimension can be attributed to its relatively higher effective mass of electron and lower permittivity. [ABSTRACT FROM AUTHOR]

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage. [ABSTRACT FROM PUBLISHER]

This letter introduces a novel alcohol-based digital etch technique for III–V FinFET and nanowire MOSFET fabrication. The new technique addresses the limitations of the conventional water-based approach in enabling structures with sub-10-nm 3-D features. Using the same oxidation step, the new technique shows an etch rate of 1 nm/cycle, identical to the conventional approach. Sub-10 nm fins and nanowires with a high mechanical yield have been achieved. InGaAs nanowires with a diameter of 5 nm and an aspect ratio greater than 40 have been demonstrated. The new technique has also been successfully applied to InGaSb-based heterostructures, the first demonstration of digital etch in this material system. Vertical InGaAs nanowire gate-all-around MOSFETs with a subthreshold swing of 70 mV/decade at V \mathrm { {DS}}= 50 mV have been obtained at a nanowire diameter of 40 nm, demonstrating the good interfacial quality that the new technique provides. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) behaviors, characterized with an SONOS-based gate-all-around junctionless nanowire (JLNW), are investigated to determine the suitability of this type of NW as a memory cell structure. LFN exhibits a 1/ $f$ -shape and is described by a carrier number fluctuation noise model. It is found that the proposed device structure shows a low level of device-to-device variation and high immunity against Fowler–Nordheim tunneling stress. Due to the centered conduction path in the JLNW device, the impact of correlated mobility fluctuations on the LFN is insignificant. The trapped charge in the nitride layer of the Silicon(Poly-Si)-oxide(SiO2)-nitride(SiNx)-oxide(SiO2)-silicon(Single-crystalline) (SONOS) device also negligibly influences the LFN. The NW width-dependence is clarified in terms of the effects of the oxide trap density and source/drain series resistance under a fresh and a programmed state. [ABSTRACT FROM AUTHOR]

The main promise of tunnel FETs (TFETs) is to enable supply voltage ( V\mathrm{ DD} ) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing V\mathrm{ DD} and channel length ( L\mathrm{ ch} ) typically deteriorates the ON- and OFF-state performance of TFETs, respectively. Accordingly, there is not yet any report of a high-performance TFET with both low V\mathrm{ DD} ( \sim 0.2 V) and small L\mathrm{ ch} ( \sim 6 nm). In this letter, it is shown that scaling TFETs in general requires scaling down the bandgap Eg and scaling up the effective mass m^{*} for high performance. Quantitatively, a channel material with an optimized bandgap ( Eg\sim 1.2qV\mathrm{ DD} [eV]) and an engineered effective mass ( m^*^-1\sim 40 V\mathrm{ DD}^{2.5} [{\mathrm{ m}}0^-1] ) makes both V\mathrm{ DD} and L\mathrm{ ch} scaling feasible with the scaling rule of L\mathrm{ ch}/V\mathrm{ DD}=30 nm/V for L\mathrm{ ch} from 15 to 6 nm and the corresponding V\mathrm{ DD} from 0.5 to 0.2 V. [ABSTRACT FROM PUBLISHER]

An integrated device–fabric methodology for evaluating and validating nanoscale computing fabrics is presented. The methodology integrates physical layer assumptions for materials and device structures with accurate 3-D simulations of device electrostatics and operations and circuit-level noise and cascading validations. Electrical characteristics of six different crossed nanowire field-effect transistors (xnwFETs) are simulated and current and capacitance data are obtained. Behavioral models incorporating device data are generated and used in fabric level simulations to evaluate noise implications of devices and sequencing schemes. Device characteristics are found to have different implications for logic “1” and logic “0” noise with faster devices being more (less) resilient to logic “1” (logic “0”) noise. A new noise resilient dynamic sequencing scheme is presented which isolates logic “0” noise events and prevents them from propagating to cascaded circuit stages, thereby enabling faster devices. Performance implications and optimizations for fabrics incorporating the new noise resilient scheme are discussed. The scheme is also analyzed and validated against an external noise source (power supply drooping). These results show that noise resilient nanofabrics can be designed through a combination of device engineering and fabric-level optimizations of the sequencing scheme. Performance optimizations and implications of device and physical layer assumptions on manufacturing are discussed. [ABSTRACT FROM PUBLISHER]

GaAs, InAs, and InGaAs nanowires each exhibit significant potential to drive new applications in electronic and optoelectronic devices. Nevertheless, the development of these devices depends on our ability to fabricate these nanowires with tight control over critical properties, such as nanowire morphology, orientation, crystal structure, and chemical composition. Although GaAs and InAs are related material systems, GaAs and InAs nanowires exhibit very different growth behaviors. An understanding of these growth behaviors is imperative if high-quality ternary InGaAs nanowires are to be realized. This report examines GaAs, InAs, and InGaAs nanowires, and how their growth may be tailored to achieve desirable material properties. GaAs and InAs nanowire growth are compared, with a view toward the growth of high-quality InGaAs nanowires with device-accessible properties. [ABSTRACT FROM PUBLISHER]

Nanoelectronic devices based upon self-assembled semiconductor nanowires are excellent research tools for investigating the behavior of structures with sublithographic features as well as a promising basis for future information processing technologies. New test structures and associated electrical measurement methods are the primary metrology needs necessary to enable the development, assessment, and adoption of emerging nanowire electronics. We describe two unique approaches to successfully fabricate nanowire devices: one based upon harvesting and positioning nanowires and one based upon the direct growth of nanowires in predefined locations. Test structures are fabricated and electronically characterized to probe the fundamental properties of chemical-vapor-deposition-grown silicon nanowires. Important information about current transport and fluctuations in materials and devices can be derived from noise measurements, and low-frequency 1/f noise has traditionally been utilized as a quality and reliability indicator for semiconductor devices. Both low-frequency 1/f noise and random telegraph signals are shown here to be powerful methods for probing trapping defects in nanoelectronic devices. [ABSTRACT FROM AUTHOR]

A feasibility and performance study of electrically reconfigurable nanowire transistors with selectable pFET and nFET operations is presented. The challenges toward circuit implementation are evaluated based on transient simulations of logic circuits. A novel physical structure capable of computing a NAND as well as NOR function is introduced. The new approach provides a flexible platform to develop and test fine-grain reconfigurable circuits and systems. [ABSTRACT FROM PUBLISHER]

A novel type of hybrid plasmonic waveguiding structure that integrates semiconductor and metallic nanowires has been proposed and investigated at telecommunication wavelengths. Semiconductor nanowires symmetrically placed on both sides of a metallic nanowire provide an additional degree of freedom for tuning the characteristics of the plasmonic nanowire mode. Theoretical analysis reveals that at appropriate geometrical parameters, the symmetric hybrid plasmonic mode of the waveguide could achieve subwavelength mode confinement with ultra-long propagation distance (even exceeding the millimeter range). Such a hybrid plasmonic nanowire structure could facilitate ultra-strong light-matter interaction between semiconductor and metal materials, and enable important applications in nanolasers and nonlinear photonics. [ABSTRACT FROM PUBLISHER]

The Conference on Precision Electromagnetic Measurements (CPEM) was held in Paris, France, on July 8–13, 2018, at the historic Maison de la Chimie in Paris’s 7th arrondissement. It was hosted by the Laboratoire national de métrologie et d’essais (LNE), Trappes, France, in collaboration with the Centre national de la recherche scientifique (CNRS), Paris, and the Observatoire de Paris, Paris. [ABSTRACT FROM AUTHOR]