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The recent development of nanoscale materials and assembly techniques has resulting in the manufacturing of high-density computational systems. These systems consist of nanometer-scale elements and are likely to have many manufacturing imperfections (defects); thus, defect-tolerance is considered as one of the most some algorithms for repairing defective crosspoints in a nanoscale crossbar architecture; furthermore we estimate the efficiency and cost-effectiveness of each algorithm. Also, for a given design and manufacturing environment, we propose a cost-driven method to find a balanced solution by which figures of merit such as area, repair time and reconfiguration cost can be taken into account. Probabilistic parameters are utilized in the proposed cost-driven method for added flexibility.

Recent developments for biosensors have been mainly focused on miniaturization and exploratory use of new materials. It should be emphasized that the absence of a novel "in-situ self-calibration/diagnosis technique" that is not connected to an external apparatus is a key obstacle to the realization of a biosensor for continuous use with minimum attendance. In order to address this issue, a novel solid-state glucose oxidase-coupled amperometric biosensor with integrated electrochemical actuation system has been designed and validated. There are two key components of the proposed glucose biosensor: solid-state GOD-coupled thin-1m amperometric sensing element and O2 depleting/saturating built-in electrochemical actuator. The actuator can be used to accomplish in-situ 1-point self-calibration by depleting O2 (i.e., by simulating glucose-free environment). Also, it can be used at the same time to extend the proposed sensor's linear detection range by increasing O2 (i.e., by enhancing glucose sensitivity). A prototype sensor was fabricated and a series of lab experiments was conducted. Collected data assures that the proposed sensor effectively establishes the zero calibration point and significantly enhances its measurement sensitivity and confidence

With molecular-scale materials and fabrication techniques recently developed, high-density computing systems in nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs), silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered as one of the most significant challenges. In this paper, we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used 1) to accurately estimate the raw and net array densities, and 2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture.

As the design and fabrication complexities for the instrumentation-on-silicon systems intensify, optimization of combined Built-In Self-Test (BIST) and Automated Test Equipment (ATE) testing becomes more desirable to meet the required fault-coverage while maintaining acceptable cost overhead. The cost associated with combined BIST/ATE testing of such systems mainly consists of the following; (1) the cost induced by the BIST area overhead and (2) the cost induced by the overall testing time. In general, BIST has faster testing speed than ATE, while it can provide only limited fault-coverage and driving higher fault-coverage from BIST means additional area cost overhead. On the other hand, higher fault-coverage can be usually achieved from ATE, but excessive use of ATE results in additional test time cost. Fault-coverage of BIST and ATE plays a significant role since it can affect the area overhead in BIST and test time in BIST/ATE. This paper is to propose a novel numerical method to find an optimized fault-coverage implemented in BIST and ATE so that a minimum cost can be achieved. The proposed method. then, is applied to two parallel combined BIST/ATE testing schemes to assure its technical validity.

As design and test complexities of SoCs ever intensify, the balanced utilization of combined built-in self-test (BIST) and automated test equipment (ATE) testing becomes desirable to meet the required minimum-fault-coverage while maintaining an acceptable cost overhead. The cost associated with combined BIST/ATE testing of such systems mainly consists of 1) the cost induced by the BIST area overhead and 2) the cost induced by the overall testing time. In general, BIST is significantly faster than ATE, while it can provide only limited fault-coverage, and driving higher fault-coverage from BIST means additional area cost overhead. On the other hand, higher fault-coverage can be easily achieved from ATE, but excessive use of ATE results in additional test time. This paper proposes a novel probabilistic method to balance the fault-coverage and the test overhead costs in a combined BIST/ATE test environment. The proposed technique is then applied to two BIST/ATE test scenarios to find the optimal fault-coverage/cost combinations.

With molecular-scale materials, devices and fabrication techniques recently being developed, high-density computing systems in the nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs) and silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered one of the most significant challenges. In this paper we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used (1) to accurately estimate the raw and net array densities, and (2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture. As a case study, the proposed yield model is applied to the defect-tolerant addressing scheme called h-hot addressing and simulation results are discussed.