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In-band full duplex (IBFD) communication systems have attracted much interest due to their ability to double the spectrum efficiency by simultaneously transmitting and receiving (STAR) over the same bandwidth. Modern communication technologies have to adapt to be able to meet the ongoing high demand capacity over existing radio channels. This paper proposes a system-level approach based on physical symmetry to improve the electromagnetic performance of a 3-port circulator. A system-level design consisting of two matched circulators connected in a differential configuration is proposed to cancel out residual RF scattering and leakage that causes self-interference in a STAR front-end. The method is validated using a custom designed microwave circulator based on microstrip technology, which forms a building block that operates in the 3–8 GHz band with 20 dB isolation. The proposed RF front-end operates within an extended band of 3–8 GHz while simultaneously exhibiting improvement in isolation by about 10 dB (isolation $30\pm 4$ dB) between the transmitter and the receiver ports of the STAR system.

As the demand for medium-voltage power semiconductors continues to rise, the super-cascode switch has emerged as a promising solution. This paper presents the design, implementation, and experimental evaluation of a 6.5 kV, 400 A super-cascode power module. This treatment includes an in-depth analysis of the theory of operation for this topology, as well as a set of design guidelines to facilitate the realization of practical implementations. To validate the functionality and performance of the realized prototype module, double-pulse test experiments were conducted under a wide range of operating conditions, deploying metrics specially targeted for the super-cascode switch. These experimental results demonstrate that adherence to the design guidelines provided in this paper yields a super-cascode switch with exceptional performance. In fact, the super-cascode module evaluated in this paper achieves switching performance on par with that of medium voltage SiC MOSFET modules, and far beyond that of medium voltage Si IGBT modules. Overall, this investigation contributes to the understanding of the factors driving the operation and performance of the super-cascode switch, especially under high current conditions.

The requirement of the upcoming sixth-generation (6G) wireless communication systems to significantly elevate the services of enhanced mobile broadband (eMBB) and massive machine-type communications (mMTC) necessitates the design and investigation of appropriate multiple access schemes. This paper investigates the impact of random source deployment on the performance of uplink systems, emphasizing the implications of non-orthogonality in contention-free and contention-based access schemes. For the latter scheme, we combine the strengths of slotted ALOHA and successive interference cancellation. Considering the advantages of breaking orthogonality in scenarios with random source deployment, we propose distinct policies tailored for mMTC, eMBB, and hybrid mMTC-eMBB scenarios by splitting the cell into rings. Furthermore, we derive closed-form expressions for the outage probability, which play a pivotal role in extracting the throughput of the sources in the considered scenarios. The paper offers a comprehensive analysis of the proposed approach, corroborated through simulations, shedding light on the potential of such protocols in future 6G wireless communication systems.

The super-cascode switch (SCS) has gained significant attention in the last decade due to its ability to achieve medium-voltage ratings using low-voltage semiconductors. However, there exists a notable absence of quantitative metrics to effectively evaluate the performance of the SCS. This gap exists because the behavior of the SCS is different from that of a traditional semiconductor switch, and traditional semiconductor performance metrics are not adequate for its evaluation. The present manuscript addresses this gap by introducing new figures of merit that are designed to evaluate the unique characteristics of the SCS. The practical value of these metrics is also demonstrated through a set of experimental studies. By applying these new figures of merit to one of the best-performing SCS configurations described previously in the literature, several opportunities for improvement are revealed. The SCS prototype described in this paper is evaluated experimentally at bus voltage levels up to 3.5 kV and current levels up to 200 A, demonstrating substantial performance improvements relative to the baseline configuration from the literature. These improvements are the result of iterative refinements to the balancing network, which are selected through a process that is informed by the application of the proposed figures of merit.

Emerging terahertz (THz) communication will become the main way of wireless communication in the future, it will also use hybrid precoding which combines analog and digital hybrid precoding like millimeter wave communication systems, to reduce the system energy consumption. Indoor as a main scenario for communication, to better meet the demands for data transmission. In this paper, an improved hybrid precoding method based on successive interference cancelation and singular value decomposition (SIC-SVD) is proposed for indoor Sub-THz communication system with sub-connected structures. However, the introduction of phase shifters imposes constant modulus constraints, making the problem of hybrid precoding difficult to solve directly. The proposed method first decomposes the optimization problem of achievable rates for the system, based on the special structure of sub-connected, into a series of equivalent sub-problems. The algorithm first designs the analog precoding matrix according to the SIC method, after obtaining the designed analog precoding matrix, the algorithm defines an equivalent channel and employs singular value decomposition (SVD) to obtain the digital precoding matrix. The simulation results show that compared with the existing method based on SIC, the proposed algorithm has slightly higher achievable rate and is closer to the optimal full-digital precoding method. At the same time, this paper also presents a simple analysis of the proposed algorithm for imperfect channel state information (CSI) with different accuracy. Simulation results show that the spectral efficiency is also very near to the perfect CSI case when the accuracy of the CSI is 0.9.

Silicon Carbide MOSFETs have lower switching losses when compared to similarly rated Silicon IGBT, but exhibit faster switching edges, larger overshoots and increased oscillatory switching behaviour, resulting in greater electro-magnetic interference (EMI) generation. Active Gate Drivers (AGD) can help mitigate these issues while maintaining low switching losses. Numerous AGD topologies have been presented with varying capabilities in terms of timing resolution and output stage complexity. This paper presents an experimental investigation into the influence these capabilities have on the switching performance of an AGD driven high current module, with the goal of advising future AGD designers on the performance trade-offs between signal resolution and complexity. A 2.5 ns resolution 6-level AGD was utilised in combination with parameter sweeps and a genetic algorithm to determine gate voltage patterns that provided improved switching performance. Results indicate that higher resolution (2.5–5 ns) provided the greatest improvements in switching performance, even utilising the simplest considered gate driving patterns, with the use of more complex patterns offering minimal additional improvements. However, at lower timing resolutions (10–40 ns) a stronger set-point dependence degradation in switching performance is observed when using simpler gate patterns, which can be mitigated by utilising more complex patterns.

To improve the lightweight level of auxiliary converters for urban rail vehicles, full SiC intermediate frequency auxiliary converters have become a trend. Aiming at its core component, a full SiC intermediate frequency isolated DC-DC converter using Boost + LLC topology is studied in this paper. The working principle and characteristics of the converter are analyzed in detail. Based on the operating characteristics of the LLC resonant converter and the realization mechanism of soft switching, an optimization design method of the resonant parameters is proposed, which can make LLC resonant converters exhibit the characteristics of DC transformers and realize soft switching in the full load range. Considering the power losses of the converter and the voltage stress of SiC MOSFET, the intermediate bus voltage design method is given. Finally, the correctness of the parameter design method is verified by simulation and experiment, and the performance of the full SiC intermediate frequency isolated DC-DC converter is analyzed. When the input voltage is 1500V and the output power is 15kW, the efficiency of the converter reaches 96.21%. Compared with the Si intermediate frequency isolated DC-DC converter, the power density is improved by 80.62%.

Generalized frequency-division multiplexing (GFDM) is one of the promising multi-carrier modulation schemes suitable for next-generation wireless communication systems. The main characteristic of GFDM is the flexible time-frequency structure of data blocks. However, this degree of freedom is obtained at the cost of loss of sub-carrier orthogonality, which leads to self-interference. In this paper, we propose a new model that classifies the GFDM self-interferences into two independent categories as inband and adjacent sub-carriers interferences and show their corresponding mathematical formulations. Building on this model, we propose a successive interference cancellation (SIC) technique with low complexity to eliminate these self-interference effectively. The main distinct feature of our proposed technique is its low computational complexity compared to similar interference cancellation techniques. Our analytical findings and numerical experiments indicate that the proposed model and SIC technique considerably improve the system performance in terms of bit error rate (BER) and signal to interference ratio (SIR). We also show that the results of our analytical findings are in good agreement with those of computer simulations.

This paper proposes high sensitivity temperature sensors based on single port surface acoustic wave (SAW) devices with GHz resonance frequencies, developed on GaN/SiC and GaN/Sapphire, which permit wide range, accurate temperature determinations. In contrast with GaN/Si SAW based temperature sensors, SiC and Sapphire substrates enable the proper functionality of these devices up to 500°C (773 K), as the high resistivity Si substrate becomes conductive at temperatures exceeding 250°C (523 K) due to the relative low bandgap (and high intrinsic carrier concentrations). Low temperature measurements were carried out using a cryostat between -266°C (7 K) and room temperature (RT) while the high temperature measurements are made on a modified RF probe station. A polynomial fit was used below RT and a linear approximation was evidenced between RT and 500°C (773 K). The structures were simulated at different selected temperatures based on a method that couples Finite Element Method (FEM) and Coupling of Modes (COM). The measured temperature coefficient of frequency (TCF) is about 46 ppm/°C for GaN/SiC SAWs and reaches values of 96 ppm/°C for GaN/Sapphire SAW in the temperature range 25 – 500°C (298 K – 773 K).

An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ). Numerical Simulation results show that the ${R} _{\mathrm{ on,sp}}$ of the proposed SiC LDMOS is 3.5 $\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ with a breakdown voltage of ~1460V, which is reduced by more than 46% compared with the conventional field-plate SiC LDMOS with a ${R} _{\mathrm{ on,sp}}$ of 6.6 $\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ and a breakdown voltage of ~1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the ${R} _{\mathrm{ on,sp}}$ and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.

SiC Schottky Barrier Diodes (SBDs) have been used in parallel with SiC MOSFETs as a freewheeling diode in power converter applications because the inherent PN body diode of the MOSFET has relatively high forward voltage drop, considerable reverse recovery current, and suffers from the expansion of stacking faults over the lifetime of the device [1]. However, an additional external diode requires extra space within a multi-chip package or power module, and adds undesirable parasitic inductance to the power loop during commutation events of the power converter. Alternatively, when the unipolar diode structure is integrated within the MOSFET, a significant reduction in wafer area is achieved by sharing active and edge termination areas. Monolithic integration of Schottky or JBS diode in a SiC MOSFET structure (JBSFET) and SiC MOSFET integrating the unipolar internal inverse channel diode were reported earlier [2]–[5], respectively. However, JBSFET from [2] has higher specific on-resistance due to the larger cell pitch from the portion of JBS diode when compared with standalone MOSFET. For [5], the fabrication of the proposed MOSFET requires a very thin and heavily doped epitaxial regrowth process, which may result in a complicated process.

We address the lens optimization and signal processing for array-based multiple-input multiple-output (MIMO) visible light communication, especially under link misalignment. We employ one concave lens and one convex lens to separate the lights from different light-emitting diodes (LEDs), and optimize the lens structure to minimize the condition number of channel gain matrix. In this way, the light emitted by different LEDs can be separated well from each other. To further mitigate the interference under transmitter/receiver mobility, we propose two signal processing approaches based on successive interference cancellation (SIC) and multi-layer coding (MC), along with maximum ratio combining (MRC) for interference/signal decoding. It is demonstrated that the interference can be reconstructed and eliminated through SIC, and MC can partially decode the interference to better reconstruct the desirable message. The proposed signal processing approaches can significantly improve the sum rate in both link alignment and misalignment cases. Moreover, MC can achieve higher sum rate, especially in the case of link misalignment.

This article presents a PCB winding coupled inductor design for both high efficiency and effective common-mode (CM) noise reduction in a silicon carbide (SiC)-based soft-switching three-phase ac–dc converter. A balance technique is applied to reduce the CM noise, creating a return path with additional inductors. The inductors in the main circuit and return path are coupled in one core and implemented with PCB windings. A winding interleaving structure with strong coupling between the main inductors is selected to minimize the winding loss and to improve the converter efficiency; however, the interwinding capacitance brought on by the winding interleaving worsens the CM noise. An inductor model including the capacitance is introduced, and its impact on the CM noise is analyzed. A novel inductor structure is proposed to scale back the interwinding capacitance and to enhance the CM noise reduction capability. Experiments with a SiC-based 25-kW soft-switching three-phase ac–dc converter prototype validates the performances of the proposed PCB winding coupled inductors. [ABSTRACT FROM AUTHOR]

Conventional digital LLC synchronous rectifier (SR) control typically uses detection circuits to sense the drain-source voltage of SR MOSFET in low output voltage applications, or gives SR duty cycle only considering the switching frequency in the microcontroller. They are difficult to be applied to the applications of 700-V high voltage and 6.6-kW high power directly due to the high dv/dt and large SR duty cycle variations, which poses serious challenge for SRs control. A bidirectional impedance-based SR driving scheme is presented for high-voltage SiC LLC converter. Based on the LLC equivalent impedance, mathematical models are built to calculate the SR on-time in the forward and reverse modes, which can be tuned timely when the switching frequency and load vary. Thus, both bidirectional LLC performance with high efficiency and high immunity to the switching noise can be achieved without adding auxiliary circuits. A prototype of 300-kHz 6.6-kW SiC bidirectional LLC charger was built. Compared to the conventional SR method, the LLC efficiencies improve 0.3% in the forward and reverse modes at full load by using the proposed SR driving scheme. [ABSTRACT FROM AUTHOR]

Non-orthogonal communications are expected to play a key role in future wireless systems. In downlink transmissions, the data symbols are broadcast from a base station to different users, which are superimposed with different power to facilitate high-integrity detection using successive interference cancellation (SIC). However, SIC requires accurate knowledge of both the channel model and channel state information (CSI), which may be difficult to acquire. We propose a deep learning-aided SIC detector termed SICNet, which replaces the interference cancellation blocks of SIC by deep neural networks (DNNs). Explicitly, SICNet jointly trains its internal DNN-aided blocks for inferring the soft information representing the interfering symbols in a data-driven fashion, rather than using hard-decision decoders as in classical SIC. As a result, SICNet reliably detects the superimposed symbols in the downlink of non-orthogonal systems without requiring any prior knowledge of the channel model, while being less sensitive to CSI uncertainty than its model-based counterpart. SICNet is also robust to changes in the number of users and to their power allocation. Furthermore, SICNet learns to produce accurate soft outputs, which facilitates improved soft-input error correction decoding compared to model-based SIC. Finally, we propose an online training method for SICNet under block fading, which exploits the channel decoding for accurately recovering online data labels for retraining, hence, allowing it to smoothly track the fading envelope without requiring dedicated pilots. Our numerical results show that SICNet approaches the performance of classical SIC under perfect CSI, while outperforming it under realistic CSI uncertainty. [ABSTRACT FROM AUTHOR]

Several important aspects related to the phenomena of ac gate-bias stress-induced threshold-voltage degradation in SiC MOSFETs are presented. These include a detailed investigation of the particular sensitivity of trench-geometry devices when exposed to a negative gate-bias overstress, the specific conditions that drive this degradation, and its recovery by the application of a dc negative bias temperature stress. [ABSTRACT FROM AUTHOR]

Rapid widespread vehicle electrification has incentivized fast chargers to improve their performances. In this article, an integrated-magnetic-based differential-mode Ĉuk rectifier (IM-DMCR) as a universal battery supercharger is introduced. The design challenges associated with the high-power operation of IM-DMCR are outlined, and optimized solutions are presented. A SiC-based full-scale 60-kW experimental prototype for the IM-DMCR is built and tested to verify the design. [ABSTRACT FROM AUTHOR]

In this letter, a 1.2kV optically-controlled SiC transistor (OCT) is proposed and fabricated. A pin diode is monolithically integrated with the SiC OCT for reverse conducting and online junction temperature measurement capability. Field limiting rings are designed as terminal structure for forward blocking capability. The test results indicated that, besides full optical control and high blocking voltage performances, the fabricated transistor chip was also capable of reverse conducting and online junction temperature measurement. The forward breakdown voltage of the transistor was about 1400V and the leakage current at 1200V was ${2.5}\,\,\times \,\,{10}\,\,^{-{8}}\text{A}$. The reverse turn-on voltage was about 2.6V, while the temperature sensitivity of the integrated diode was 2.99mV/K at 5mA. Under 365nm ultraviolet (UV) light with 300mW/cm2 incident intensity, the forward current of the OCT chip was $203.2\mu \text{A}$ at 0.3V, which is about ${1.2}\,\,\times \,\,{10}\,\,^{{5}}$ times the corresponding dark current. The transient characteristic was tested at a 600V bias voltage in a resistive load circuit and the results indicate that the OCT can be switched using a 365nm UV light emitting diode. [ABSTRACT FROM AUTHOR]

Smooth and uniform epitaxial ultrathin MgB2 films are desired for various electronic applications including hot-electron bolometers and single-photon detectors. However, the growth of ultrathin MgB2 films on SiC substrates using the Hybrid Physical-Chemical Vapor Deposition was dominated by the Volmer-Weber or island growth mode, which limited the minimum thickness for a conductive MgB2 film. Here we show the results of a study on the very early stage of the MgB2 film growth. We find that the root-mean-squared roughness and grain connectivity of ultrathin MgB2 films grown on C-terminated 6H-SiC($000\bar{1}$) substrate is much better than those on Si-terminated substrate. The result provides a simple solution to growing high-quality ultrathin MgB2 films for applications. [ABSTRACT FROM AUTHOR]

This letter reports the demonstration of 1.2 kV 4H-SiC Schottky-integrated MOSFETs (JBSFETs) achieving the same specific on-resistance as the pure MOSFET by using an innovative layout approach as well as novel deep P-well structure. The proposed JBSFET significantly reduces the specific on-resistance accomplishing 2x reduction in the chip size, when compared with the traditional, chip-to-chip parallel connection of separate MOSFET and JBS diode. Moreover, the leakage current originated from the Schottky contact was successfully suppressed by adopting a $1.8~\mu \text{m}$ deep P-well structure implemented by channeling implantation. Device design strategy with layout approach, fabrication, and static and short-circuit characteristics are discussed in this letter. In order to understand and clarify the experimental results, 2D simulations were conducted. [ABSTRACT FROM AUTHOR]

The development of 5G has put forward a higher demand for filters, and the purpose of this work is fabricating surface acoustic wave (SAW) filters with excellent temperature stability and high power handling using LiTaO3/SiC bonded wafers. SAW resonators with different wavelengths are fabricated on LiTaO3/SiC, and LiTaO3/Si, bulk LiTaO3 as well. We evaluate these resonators, concluding that the bilayer substrates can enhance the performance. Subsequently, SAW filters are designed and fabricated. For the filters based on LiTaO3/SiC, the center frequency is around 2.62 GHz and the minimum insertion loss is 1.90 dB. The whole passband is flat and larger than 200 MHz, and the return loss is larger than 10 dB. SiC is more effective than Si in the enhancements of temperature stability and power handling. SiC reduces the temperature coefficient of the frequency at the left side of the passband to about half of that on LiTaO3/Si and one-sixth of that on bulk LiTaO3, and enlarges the peak power handling to 35.7 dBm. The time-to-failure of the filters on LiTaO3/SiC is 3.8 times as long as LiTaO3/Si and 11.3 times the level of bulk LiTaO3, when an input power of 30 dBm is applied ceaselessly. This work demonstrates the potential of SAW filters based on LiTaO3/SiC for RF filters in 5G. [2021-0233] [ABSTRACT FROM AUTHOR]

Active thermal control has been introduced to regulate the steady state and reduce the transient thermal-mechanical stress in power electronic modules. Specifically, it can equally distribute the temperature among the devices, thereby better distributing the stress among a set of devices and reducing the failure probability in the most thermally-stressed devices. This is of great importance for multilevel topologies and in particular for the Neutral Point Clamped (NPC) topologies, which have an inherent thermal unbalance among devices of the same phase. In hybrid structures, whereby Si and SiC devices are mixed to achieve a better trade-off between efficiency and cost, this problem is even worse due to technology differences. This paper investigates the advantages introduced by using Finite-Set Model Predictive Control (FS-MPC) algorithms designed for achieving a balanced device junction temperature in hybrid NPC and Active-NPC converters. Moreover, a novel setup composed by a hybrid ANPC based power modules is used to experimentally validate the presented FS-MPC algorithm. A lifetime estimation is performed for the two topologies to highlight the long-term benefits of FS-MPC algorithm in these hybrid topologies for UPS applications.

With the significant advantages of 5G technique such as higher transmission rate and lower transmission delay, it is more in line with the requirements of the connected vehicle scenario. In addition, the serial interference cancellation (SIC) technology in 5G technology can further improve the communication quality compared to a single one-to-one multiplexing method. Taking the dynamic communication characteristics of Internet of Vehicles into consideration, the robust optimization problem is formulated, which attempts to maximization the total throughput of vehicle users under the changing channel gains. The channel uncertainty is formulated as probability constraints, and they are transformed to the deterministic form to achieve a convex optimization problem. And the Hungarian algorithm is introduced to allocate the available channels to the V2V pairs. With the proposed joint resource allocation algorithm, the maximum throughput can be obtained with the lower algorithm complexity. Also, the robustness against the changing channel gains is guaranteed and the outage probability of users is kept below the pre-given outage threshold.

Silicon carbide (SiC) devices can exhibit simultaneously high electro-thermal conductivity and extremely fast switching. To perform optimal designs showing the benefits of SiC in achieving efficiency, size, weight, and cost objectives for electric converters design, it is necessary to establish better models for calculating device losses and an efficient thermal model that can be calibrated to consider the nuances of measurement based thermal equivalent circuits. This work's outputs can be used in a power converter multi-objective optimization process or real-time temperature prediction of drives to improve reliability and maximize performance. The proposed modified loss calculation and thermal model demonstrate the SiC power module's advantages to reduce peak junction temperature and power cycling effects. A detailed power loss calculation and thermal model is developed and tested on a 480 V, 186 A, 150 HP variable frequency drive (VFD) with SiC modules. A comparison between the SiC module and an equivalent rated Si module demonstrates the reduction in power cycling effects, particularly at low-speed operation. Infrared (IR) imaging results and analytical explanations of the phenomenon is provided. Power cycle tests show that higher thermal conductivity is not the only reason contributing to the lower temperature ripple in low-speed operation.

This paper proposes a co-design optimization procedure of a high-power off-board charger for electric vehicle (EV) applications. The primary purpose is to design a 175 kW SiC DC-charging system with high power density to achieve high efficiency at a wide operating range. For the active part of the DC off-board charger, a three-phase active front end (AFE) rectifier topology is considered in the design optimization and the modelling. The design methodology focuses on the optimal design of the passive filters, accurate electro-thermal modelling of the converter, inductor design, capacitor selection, loss and geometric modelling of the passive filters and control system design. The design optimization of the high-power charging system is performed in MATLAB Simulink using a closed-loop dynamic electro-thermal simulation of the off-board charger. The switching frequency, loss and temperature-dependent efficiency of the charger is investigated in parallel. Through this proposed technique, efficiency greater than 96% is achieved at a switching frequency of 40 kHz, along with a smaller size and lower weight of the system. Moreover, it operates with a current total harmonic distortion (THDi) below 3% and a power factor (PF) above 99% at rated power condition.

This article shows the use of a high-frequency Full-Bridge inverter to design an alternating magnetic field generator for experimental studies on anti-cancer treatment with magnetic nanoparticles. In magnetic hyperthermia, nanoparticles are used to raise the pathological cancerous cell’s temperature high enough to induce their death by apoptosis, but not as high as to destroy them by thermal ablation of the whole tissue volume, consequently leaving healthy cells alive. Conventionally, sinusoidal alternating magnetic fields are used to heat the nanoparticles, which can be more easily produced than other waveforms. However, there are no theoretical nor experimental reasons to choose the sinusoidal waveform. This work aims to develop an improved power system to study the effect of different waveforms of the magnetic field on heat production when exciting magnetic nanoparticles, aiming at demonstrating that other waveforms can be much more efficient in producing heat than conventional sinusoids. To prove our hypothesis, we designed an inverter able to generate four waveforms at high frequencies and a fifth sinusoidal signal derived by a resonant capacitor, in the range of 100 kHz to 1 MHz and up to 10 mT of peak intensity. Also, we used SiC devices to process high currents at high switching frequencies efficiently. Additionally, to enhance the system efficiency, Zero-Voltage Switching is used to reduce switching losses and minimize electromagnetic noise and interference. The experimental results obtained with non-sinusoidal waveforms have shown a remarkable performance improvement compared to classical sine wave excitation. The nanoparticles’ heat dissipation depends on the applied alternating magnetic field’s signal slope, signal frequency, and peak field intensity. We conclude that further work deserves to be done to find the optimum work conditions in function of the used particle and biological environment to test if this type of magnetic field generator could overcome the conventional system’s performance.

In traditional CSMA/CA-based MAC designs supporting successive interference cancellation (SIC), channel utilization is inefficient, because the inherited CSMA/CA-style contention approach often forces the whole channel to remain idle and the early released channel is not utilized. In this paper, we propose Multi-CQ, which is the first software-defined networking (SDN)-based MAC design for wireless LANs that supports SIC and significantly improves the channel utilization. Multi-CQ, adopting SDN’s functional separation idea and OFDMA, makes contention and data transmission be executed over two subchannels independently and concurrently, where the superposition coding are used for decoding combined signals, and multiple CQs (contention queues) are introduced to coordinate the concurrency. This concurrent execution greatly reduces the waste in channel contention. Next, adopting SDN’s central control idea, Multi-CQ controller selects nodes who can finish their frame transmissions in almost equal time, thereby improving the channel utilization. Finally, we develop a theoretical model to optimize bandwidth allocation for channel contention and data transmission. Extensive simulations verify the effectiveness of our design and the accuracy of our theoretical model. This study is also helpful to better design wireless MAC protocols supporting other advanced functionalities such as MU-MIMO.

The poor interface quality of the Silicon Carbide/oxide (SiC/SiO2) interface severely degrades the electron surface channel mobility in SiC-based power devices. Based on transfer characteristic simulations (with a deck calibrated to experimental data), this work predicts improved mobility with stress engineering, a well-established technique for performance enhancement in low power silicon (Si) transistor technology. Process simulation of Si and SiC-based devices with Silicon Nitride (Si3N4) stressor layer has been carried out to estimate the stress generated in the channel. SiC D-MOSFET we have also computed the effect of varying stress magnitude, direction, and position in the device.

The expansion of the electric vehicle market is driving the request for efficient and reliable power electronic systems for electric energy conversion and processing. The efficiency, size, and cost of a power system is strongly related to the performance of power semiconductor devices, where massive industrial investments and intense research efforts are being devoted to new wide bandgap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN). The electrical and thermal properties of SiC and GaN enable the fabrication of semiconductor power devices with performance well beyond the limits of silicon. However, a massive migration of the power electronics industry towards WBG materials can be obtained only once the corresponding fabrication technology reaches a sufficient maturity and a competitive cost. In this paper, we present a perspective of power electronics based on WBG semiconductors, from fundamental material characteristics of SiC and GaN to their potential impacts on the power semiconductor device market. Some application cases are also presented, with specific benchmarks against a corresponding implementation realized with silicon devices, focusing on both achievable performance and system cost.

Demand for small, multi-functional, high performance electronic product with less power consumption is increasing rapidly. To meet the demand, IC design has been shifted from two dimensional integrated circuit (2D-IC) to three dimensional integrated circuit (3D-IC), where multiple device layers are stacked together to create stacked integrated circuit (SIC). This results the complexity in 3D SIC architecture and increase in the number of fault-sites. Therefore, testing of SIC has become complicated. Consequently, the test data volume also grows in proportion to the number of cores in the SIC, since each core is associated with one or more tests, which leads to longer test times. Test cost of IC which depends on test time, associated hardware to test the cores and the power dissipated at the time of test, can be represented as a weighted sum of test time and the associated hardware to test the core with power considered as the test constraint. As a result an efficient test plan is required to co-optimize test time and hardware under certain power constraint. The objective of our work is to design an efficient test plan both for non-stacked IC (i.e. SIC with single chip) and 3D stacked IC (i.e. SIC with multiple chips) under a power constraint, where each chip is provided with IEEE 1149.1 architecture. An existing cost model is used for calculating the test cost. Initially we propose First fit based two dimensional (2D) Bin Packing optimization algorithm for minimizing the test cost of non-stacked IC. However, the method produces sub-optimal result in comparison to earlier reported work. Knowing the complexity of 3D SIC, Genetic algorithm based metaheuristic approach is next proposed in this paper. It is applied on several ITC02 benchmark circuits and the experimental result shows the efficacy of the proposed algorithm in comparison to earlier works.

Lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) are fabricated on 4H-SiC utilizing deposited high- ${k}$ gate dielectrics. The high- ${k}$ gate-stack consists of thin nitrided SiO2 and 40 nm of LaAlO3 covered with a thin Al2O3 cap. The high- ${k}$ gate MOSFET achieves a 40% reduction in channel resistance (at ${V}_{gs} = 15$ V) compared with that of the conventional SiO2 gate MOSFET. In addition, bidirectional transfer characteristics of the high- ${k}$ gate MOSFET indicate slight hysteresis and show a superior threshold voltage stability compared to that of competitors, in a range of −15 V $\le {V}_{gs} \le16$ V under room and elevated temperatures. Therefore, the Al2O3/LaAlO3/SiO2 gate-stack can provide both low on-resistance and good threshold voltage stability for SiC power MOSFETs. [ABSTRACT FROM AUTHOR]

Full Duplex (FD) in cellular networks is expected to increase the cell spectral efficiency. However, while the downlink (DL) spectral efficiency (SE) increases with FD, the uplink (UL) SE decreases because of the Base Station to Base Station (BS) interference. In this paper, assuming a three-node model, we propose a method based on Successive Interference Cancellation (SIC) to reduce the BS-to-BS interference present in FD cellular networks. The approach consists in coordinating BSs to enable the decoding and the suppression of undesired signals that impair uplink transmissions. We analyze both distributed and Centralized Radio Access Networks (CRAN) architectures. Stochastic geometry is used to derive the coverage probability and mean data rate of the proposed scheme. In the distributed scenario, the FD UL average data rate is increased by 25% with our solution compared to a classical FD network, while our FD scheme still outperforms Half-Duplex (HD) on the DL. In the centralized scenario, our solution outperforms HD by 10% and classical FD by 78% on the UL, while preserving classical FD gains on the DL. [ABSTRACT FROM AUTHOR]

In high dose per pulse charged particle beams, all online detectors saturate due to ion recombination. It is therefore impossible to count detector pulses separately. Silicon carbide due to its high bandgap, high thermal conductivity, and high displacement energy, is seen as an alternative. Analyzing waveforms in real-time is challenging in terms of bandwidth, measurable energy range, sensor size, data rate. In this context, an Analog Front-End (AFE) was designed for radiation signal processing. It is based on a Transimpedance Amplifier (TIA) and Charge Sensitive Amplifier (CSA) respectively, to analyze the shape of the generated signal. The methodology used to characterize AFE for large detector capacitance is described. The results obtained from simulations, experiments, and measurements in a radiative environment are also presented. [ABSTRACT FROM AUTHOR]

Silicon Carbide (SiC) Ultraviolet (UV) phototransistors with bidirectional bias response were fabricated and analyzed in this letter. The results showed that the fabricated UV phototransistor exhibited stable photoelectric response characteristics and transistor characteristics under both forward and reverse voltages, owing to the structure design of the epi-layers, while the mechanism of the bidirectional response was also studied. The difference in photocurrent under different bias voltages and wavelengths of UV illumination were mainly due to the variation of the absorption coefficient with wavelength and the change in the width of the space charge regions, which ultimately led to a difference in the number of photo-generated carriers. The time response characteristics of the detector showed that there were time delays when the detector was turned on and turned off, which was caused by the photo minority carriers in the depletion layer of the base-collector junction. [ABSTRACT FROM AUTHOR]

The performance of an unmanned aerial vehicle (UAV) assisted cooperative cognitive radio (CR) network is studied in this paper. The study is carried out for line-of-sight (LOS) links between UAV and a ground user and UAV aerodynamic power consumption of UAV. The UAV consists of an RF energy harvester and it is also a CR enabled device. It harvests energy from RF signal of source nodes. It rotates periodically over a circular region of interest (CROI) for finding the vacant primary user (PU) band. It uses a PU band to set a link between ground nodes, while the direct links between them suffer from severe fading. The decision about the status of a PU band is made cooperatively. In cooperative sensing, all the sources along with the UAV take sensing decisions and send them to fusion centre (FC). A two stage fusion scheme is proposed to take the overall decision. The considered network model uses non-orthogonal multiple access (NOMA) scheme to forward the information of a source to its corresponding destination. Analytical expressions of harvested energy, overall sensing decision and throughput are developed. The analytical expressions capture the effect of fading as well as change in distances (source-UAV and UAV-destination) due to the circular flight of the UAV. Impact of imperfect successive interference cancellation (SIC) on the system performance is also studied. Power allocation in the second hop link is optimized to maximize the network throughput. Energy-efficiency of the considered network is evaluated. For a given UAV flight period, radius of the circular trajectory, and the velocity of the UAV is optimized to maximize the energy-efficiency. Sensing performance of the considered system model is studied in terms of false alarm. Network throughput is investigated for several network parameters such as fading parameter, the number of sources, the number of UAV's sensing slots, the velocity of UAV, the radius of the UAV trajectory etc. Sensing angle and harvesting angle are optimized to maximize the throughput. Results show that the value of fading parameter, radius of UAV trajectory, and UAV velocity has significant impact on throughput. The performance of NOMA is compared with orthogonal multiple access (OMA). [ABSTRACT FROM AUTHOR]

In this letter, a sidewall-implanted trench termination for SiC devices is proposed and experimentally demonstrated. With the p-type sidewall region implemented by tilted ion implantation, the electric field crowding at the edge of the main junction can be alleviated. Compared with the conventional trench termination, devices with the fabricated sidewall-implanted trench termination exhibits a higher breakdown voltage (BV) exceeding 1800V, as well as lower leakage current. Moreover, the minimum trench width for over 1800V blocking is significantly reduced from $14~\mu \text{m}$ to $5~\mu \text{m}$. In addition, the sidewall-implanted trench termination shows stronger robustness as the dominant current path is relocated from the trench sidewall to the whole active region. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrated an approach to introduce a positive shift in transfer curves of lateral metal-oxide-semiconductor field-effect transistors (MOSFETs) on 4H-SiC (0001), without deterioration of channel conductance. With an additional Al2O3 thin film on thermally grown SiO2 after the nitridation process, a dipole layer was formed at the Al2O3/SiO2 interface, which induced the positive shift of flat-band voltage. The field-effect mobility of MOSFET was not changed after the Al2O3 fabrication process, which means that the quality of the nitrogen-passivated SiO2/SiC interface was not damaged by this process. [ABSTRACT FROM AUTHOR]

Surface charge accumulation under DC stress is a critical factor in reducing the insulation performance of epoxy-based nanocomposite. Surface coating has been used to inhibit the charge accumulation, but the inhibition mechanism of the coating material is still unclear. In this paper, graphene oxide (GO) and silicon carbide (SiC) have been selected as fillers to prepare the coating material with epoxy as the base material. The role of GO on surface charge inhibition performance of epoxy/SiC coating has been estimated. The test results showed that the charge inhibition performance and the flashover voltage increase with the growth of nano-SiC content from 1 wt% to 5 wt% in the epoxy/SiC coating. As regards the epoxy/(SiC+GO) coating, the charge inhibition performance and flashover voltage reduce as the SiC content increases. It is suggested that the charge inhibition performance of epoxy/SiC coating can be improved with a low content addition of GO. The variation of trap distribution in the coating material caused by the GO should be responsible for the enhanced charge inhibition behavior.

Full-duplex (FD) communication is capable of simultaneously transmitting and receiving data on the same frequency band. To effectively utilize FD in a wireless local area network (WLAN), one must use medium access control (MAC) protocols that consider the characteristics of FD. Many researchers have proposed and analyzed FD MAC protocols for WLANs. Most of this work revealed that as the number of nodes increases, the overall throughput decreases due to collisions. We have found, however, that with a smart MAC protocol, the throughput actually improves as the number of nodes increases. In this paper, we propose an asymmetric FD MAC protocol and then design an FD WLAN analytical model to evaluate saturation throughput. In our analytical model, we consider FD pair probability-the probability that a node capable of FD communication exists. To validate our model, we calculate FD pair probability values based on the modulation and coding scheme (MCS) levels and self-interference cancellation (SIC). We then analyze the effect of the FD pair probability on throughput. Simulation results verify the accuracy of our analytical model. Moreover, we compare the fairness of the proposed and conventional FD MAC protocols. As demonstrated through extensive evaluations, the fairness of the proposed FD MAC protocol is improved.

We studied the avalanche failure mechanism of a 1.2-kV 40-A monolithic junction barrier-controlled Schottky-diode-integrated SiC MOSFET (JMOS) using a single-pulse unclamped inductive switching (UIS) test to evaluate its avalanche ruggedness. The avalanche electro-thermal (AET) model was established to illustrate the transient electro-thermal behavior in single-pulse avalanche stress to present the thermal runaway failure process of the JMOS and obtain the dynamic temperature function during UIS. The AET model also proposes a critical failure temperature of 1240 K for determining the failure region. The electro-thermal TCAD mixed mode simulation study demonstrates that the critical temperature and failure area appear in the Schottky barrier diode (SBD) region, which is also verified by a focused-ion beam (FIB) microsection analysis. The enhancement of avalanche ruggedness of JMOS can be achieved by adjusting the properties of the SBD region. [ABSTRACT FROM AUTHOR]

The trade-off relationship between specific on-resistance and short-circuit withstand time in 1.2 kV 4H-SiC MOSFETs was drastically increased using a novel device structure. MOSFETs with deep P-well-formed using channeling implantation were firstly demonstrated to improve short-circuit ruggedness (~4 times longer than conventional MOSFET) with no negative impact on specific on-resistance. Proposed MOSFETs achieved short-circuit withstand time of $8~\mu \text{s}$. Channeling implant with low energy was conducted to form deep P-well junctions. Fabrication of a deep P-well using channeling implantation is demonstrated using no additional nor complicated processes when compared to the conventional MOSFET fabrication process. A comparison between the conventional and novel designs was performed in terms of the output characteristics, blocking behaviors, and short-circuit ruggedness. [ABSTRACT FROM AUTHOR]

In this letter, we modify the multi-threshold detector (MTD) for detection of downlink non-orthogonal multiple access (NOMA) signals in the Rician fading channel with statistical knowledge of channel state information (CSI). First, the error probability ($P_{e} $) for both MTD and successive interference cancellation (SIC) with statistical CSI is calculated. Then, we use the obtained $P_{e} $ expression to fairly allocate power to different users in the sense that the maximum $P_{e} $ of the users is minimized. Finally, computer simulations are performed, which show that MTD outperforms the SIC in the case that error propagation happens in the noise-free SIC. [ABSTRACT FROM AUTHOR]

It is highly desirable to monolithically integrate a high-performance freewheeling diode (FWD) in both Si and SiC power MOSFETs for power electronic applications. This is especially true for a SiC MOSFET since its inherent body diode has a very large turn-on knee voltage (~2.7 V). The purpose of this numerical study is to investigate a new 1200 V SiC MOSFET structure with an integrated heterojunction diode formed between n-type polysilicon and n-type SiC (termed HJD-MOSFET). The proposed HJD-MOSFET uses a mesa structure to accommodate the heterojunction FWD without sacrificing any active area while leaving the split-gate planar MOSFET cells in the trench. A p-shield region surrounding the heterojunction, along with the p-base of the MOS cells, shields high electric fields and maintains a high breakdown voltage. Three key HJD-MOSFET device parameters are identified and optimized in this article. The HJD-MOSFET offers a turn-on knee voltage of 0.5 V, roughly five times lower than the intrinsic SiC body diode or two times lower than a typical SiC Schottky barrier diode due to the low barrier height of the n/n heterojunction (~0.68 eV). Finally, the gate charge of HJD-MOSFET is reduced by 42% compared with conventional MOSFET since the poly-Si gate electrode is significantly reduced to accommodate the heterojunction FWD. [ABSTRACT FROM AUTHOR]

The ability of cubic phase (3C-) silicon carbide (SiC) to grow heteroepitaxially on silicon (Si) substrates (3C-SiC-on-Si) is an enabling feature for cost-effective wide bandgap devices and homogeneous integration with Si devices. In this article, the authors evaluated 3C-SiC-on-Si Schottky barrier contacts by fabricating and testing nonfreestanding lateral Schottky barrier diodes (LSBD). To gain a deep physical insight of the complex carrier transport phenomena that take place in this material, advanced technology computer aided design (TCAD) models were developed that allowed accurately matching of measurements with simulations. The models incorporate the device geometry, an accurate representation of the bulk material properties, and complex trapping/de-trapping and tunneling phenomena that appear to affect the device performance. The observed nonuniformities of the Schottky barrier height (SBH) were successfully modeled through the incorporation of interfacial traps. The combination of TCAD with fabrication and measurements enabled the identification of trap profiles and pin their influence on the electrical performance of 3C-SiC-on-Si LSBD. The effect of temperature was studied by engaging the identified trap profiles and calculating the occupation distribution of electrons in 3C-SiC at elevated temperature. The investigation constitutes an imperative knowledge step towards the development of devices that take advantage of 3C-SiC material properties. [ABSTRACT FROM AUTHOR]

The rapid development of the fifth-generation (5G) wireless system is driving strong demand for high-performance radio frequency filters. This work studies shear horizontal surface acoustic wave (SAW) devices using 15°-rotated Y-cut X-propagating (15°Y-X) LiNbO3/SiO2/SiC multilayered substrates. Single-crystalline 15°Y-X LiNbO3 films are bonded to SiO2/SiC handling substrates by the smart cut technology. On the basis of accurate finite-element-method simulations, LiNbO3/SiO2/SiC wafer configurations are optimized to suppress spurious resonance due to Rayleigh-mode and transverse-mode responses, and one-port resonators with a clean spectrum, a high electromechanical coupling coefficient of 22.00%, and an admittance ratio (impedance ratio) over 65 dB are successfully implemented. Based on the characteristics of the resonators, high-performance filters with a center frequency of 1.28 GHz, a large 3-dB fractional bandwidth of 16.65%, and a low minimum insertion loss of 1.02 dB are successfully designed and fabricated. Furthermore, no ripples in the passband of the filters are observed. Additionally, the filters exhibit a temperature coefficient of center frequency of −63.8 ppm/°C and a large power durability of 33.2 dBm. This work confirms the high performances of the SAW devices using the 15°Y-X LiNbO3/SiO2/SiC multilayered substrate, and this type of SAW device exhibits a prospect of commercial applications in the 5G wireless system. [ABSTRACT FROM AUTHOR]

This paper considers the power allocation for non-orthogonal multiple access (NOMA) users to enable using the successive interference cancellation (SIC) while providing reliable error performance. The derived closed-form expressions are applicable for arbitrary number of NOMA users each of which has a square or rectangular quadrature amplitude modulation (QAM) constellation with arbitrary order. The obtained numerical results show that power assignment process at the transmitter for the superposition process and at the receiver for the SIC process should be performed meticulously because the power difference between the weakest and strongest users can be tremendous when the number of users or the modulation orders increase. Moreover, the derived expressions can be used to reduce the computational complexity that is required to obtain the optimal power coefficients using brute force methods by significantly reducing the search space. [ABSTRACT FROM AUTHOR]

The Huang-Pair is a novel hybrid diode concept based on the integration of a low forward voltage drop, low voltage rating diode with a high voltage majority carrier switch, such as a silicon carbide (SiC) Junction gate field-effect transistor (JFET). A 1200 V Huang-Pair is developed to demonstrate the concept in which a low voltage Si diode is paired with a 1200 V SiC JEFT, resulting in a low-forward voltage, low reverse recovery high voltage diode. The Huang-Pair is a two terminal device and its performance tradeoff between forward voltage drop, leakage current, and reverse recovery can be conducted between two discrete devices, which is more flexible. The Huang-Pair concept can also be realized by SiC MOSFET and gallium nitride MOSFET, and it can be applied to different voltage classes. [ABSTRACT FROM AUTHOR]

We identify vector perturbation (VP) precoding as a special case of nested lattice coding where the fine/coding lattice is adopted from the channel matrices, and the coarse/shaping lattice is in the self-similar form of the fine lattice. Since we still have the freedom to optimize the shaping lattice, in this work, we design an efficient algorithm to construct a rectangular shaping lattice for VP. This design is especially well-suited to the low-complexity approximations of VP, i.e., zero forcing (ZF) and successive interference cancellation (SIC) precoders. Simulations show that rectangular shaping based ZF and SIC precoders exhibit significant performance gains compared with their self-similar shaping based counterparts. [ABSTRACT FROM AUTHOR]

In this letter, non-orthogonal multiple access based coded slotted ALOHA (NOMA-CSA) for machine-type communications (MTC) is proposed, in which encoded segments are transmitted with discrete power levels. Most collided segments can be successfully decoded by using the successive interference cancellation (SIC) and maximum-a-posteriori (MAP) erasure decoding. To further improve performance, the code degree distribution and the power distribution for the different number of power levels are jointly optimized, which leads to considerable performance improvement. Numerical results verify our analysis and show that the NOMA-CSA greatly outperforms conventional schemes in terms of throughput and packet loss rate (PLR). [ABSTRACT FROM AUTHOR]

Optical crosstalk is one of major problems limiting the performance of focal plane arrays based on single photon avalanche diodes (SPADs). In this work, for the first time the crosstalk characteristics of a 4H-SiC SPAD linear array are studied, which is based on a real-time dual channel data acquisition method. It is found that SiC SPAD array exhibits similar crosstalk probability compared with those of InGaAs-based SPAD arrays, which can be effectively reduced by trench isolation between adjacent pixels or by lowering overbias. The average time required for forming a crosstalk event is determined between 7 and 10 ns. As a result, active time-gated operation scheme can be applied for reducing crosstalk.