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Anisotropic etching of deep trench in bulk Si for isolating global buried collector in Si monolithic microwave integrated circuit has been successfully developed with SF/sub 6//C/sub 2/CIF/sub 3/ gas mixtures. Using photoresist as the etching mask, deposition of polymer thin film on the sidewalls of the trench occurred, hence inhibited lateral etching and made the process anisotropic. Under optimal process conditions, an etching anisotropy of 0.98 and an etching selectivity of silicon to photoresist higher than 28 were observed.

The self-planarization of deep trench with 2 micron thick field oxidation has been developed for Si monolithic microwave integrated circuit (Si MMIC). Trenches with geometry of 2 /spl mu/m wide by 6/spl mu/m deep can be filled and planarized simply by a local oxidation of silicon (LOCOS) without polysilicon re-filling or etching back, while maintained a collector-to-collector leakage of 5 /spl mu/a at 15 V.

A static divide-by-four frequency prescalar IC operating for input signals from 20 MHz to 5.5 GHz is presented. The circuit was fabricated using Avantek's f/sub T/=12 GHz f/sub max/=20 GHz non-polysilicon-emitter ISOSAT-I silicon bipolar process. The die fits in a standard microwave transistor package due to its small size and single-bias-supply requirement. An integrated input buffer was provided to obtain high sensitivity and to avoid self-oscillation in the absence of an input signal. This work presents an example of a medium-scale-integration silicon bipolar IC operating at GHz frequencies (or Gbit/s rates). >

Presents both electrical and optical simulations of Si guided-wave electro-optic modulators. The simulation starts with design of modulators using a 2D semiconductor process simulator. The electrical properties of the modulators are analyzed by a 2D device simulator. Thereafter, the simulated electrical parameters are converted into optical parameters by proper electro-optic coefficients. The optical simulations are performed with both finite-difference-time-domain (FDTD) and mode-propagation-by-Fourier-expansion (MPFE) methods. The advantages of combining and using these two algorithms together are better accuracy and capability of analyzing arbitrarily shaped and optically large structures. The technique is illustrated by simulation and analysis of a series of Si guided-wave electro-optic modulators. >

Silicon piezoresistive stress sensors are used to measure stress on a plastic-encapsulated silicon die. These sensors are conventionally fabricated onto the surface of silicon integrated circuit die as part of the normal processing procedure. Since they can also be used over a wide temperature range after calibration, thermally-induced stresses can be measured. A four-point bending (4PB) stress fixture was used in calibration experiments. The results between the four-point resistance measurement and two-point resistance measurement of the strain gauges were compared. The problem in the calibration process was discussed.

A sealed wedge-shaped silicon power triode has been fabricated by CMOS compatible technology. The fabricated field emitter has higher thermal and mechanical stability due to the Eiffel Tower shape. The sealed structure eliminates the needs for external vacuum pumping and improves the reliability and lifetime of the device. Anode currents were demonstrated at anode voltages less than 4 volts.

A planar Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with high aspect ratio were fabricated in an embedded structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed within the dielectric. This process can provide desired properties of conductor structures for Si LSI applications.

A leading-edge 0.13 /spl mu/m CMOS technology using 193 nm lithography and Cu/low-k interconnect is described in this paper. High performance 80 nm core devices use 17 /spl Aring/ nitrided oxide for 1.0-1.2 V operation. These devices deliver unloaded 8.5 ps gate delay @1.2 V. This technology also supports general ASIC applications with 20 /spl Aring/ oxide for 1.2-1.5 V operation and low-standby power applications with 26 /spl Aring/ for 1.5 V operation, respectively. Dual gate oxides of 50 or 65 /spl Aring/ are also supported for 2.5 V or 3.3 V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high density 1P3M 2.43 /spl mu/m/sup 2/ 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.