71 results on '"Thean, Aaron Voon-Yew"'
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2. First Demonstration of HZO-LNOI Integrated Ferroelectric Electro-Optic Modulator and Memory to Enable Reconfigurable Photonic Systems
3. Quantile Online Learning for Semiconductor Failure Analysis
4. BEOL Compatible Extremely Scaled Bilayer ITO/IGZO Channel FET with High Mobility 106 cm2/V.s
5. Back-End-of-Line-Compatible Anneal-Free Ferroelectric Field-Effect Transistor
6. First Demonstration of Ultra-low Dit Top-Gated Ferroelectric Oxide-Semiconductor Memtransistor with Record Performance by Channel Defect Self-Compensation Effect for BEOL-Compatible Non-Volatile Logic Switch
7. Anneal-Free HZO-Based Ferroelectric Field-Effect Transistor for Back-End-of-Line-Compatible Monolithic 3D Integration
8. Extremely- Scaled Channel Thickness ZnO FET with High Mobility 86 cm2/V-s, Low SS of 83mV/dec and Low Thermal Budget Process (<300°C)
9. A Simulation Approach to Analyze Bridge-Defects in a 6T-SRAM Bit Cell
10. Bridge-Defect Prediction in SRAM Circuits Using Random Forest, XGBoost, and LightGBM Learners
11. Seal Integrity Testing Utilizing Non-Destructive Capacitive Sensing for Product Packaging Assurance
12. Indium-Gallium-Zinc-Oxide (IGZO) Nanowire Transistors.
13. Amorphous IGZO TFTs Featuring Extremely-Scaled Channel Thickness and 38 nm Channel Length: Achieving Record High Gm,max of 125 μS/μm at VDS of 1 V and ION of 350 μA/μm
14. Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM
15. 23.2 A 70µW 1.19mm2 Wireless Sensor with 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver
16. Design and Study of an Artificial Spiking Neuron Enabled by Low-Voltage SiOx-based ReRAM
17. TCAD-Enabled Machine Learning Defect Prediction to Accelerate Advanced Semiconductor Device Failure Analysis
18. A 70-μW 1.35-mm2 Wireless Sensor With 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver.
19. Amorphous InGaZnO Thin-Film Transistors With Sub-10-nm Channel Thickness and Ultrascaled Channel Length.
20. Aerosol Jet Printed WSe2 Based RRAM on Kapton Suitable for Flexible Monolithic Memory Integration
21. Design of Artificial Spiking Neuron with SiO2 Memristive Synapse to Demonstrate Neuron-Level Spike Timing Dependent Plasticity
22. First Demonstration of a Fully-Printed Mos2Rram on Flexible Substrate with Ultra-Low Switching Voltage and its Application as Electronic Synapse
23. A 7×7×2mm3 8.6-μ 500-kb/s Transmitter with Robust Injection-Locking Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications
24. Design-Technology Co-optimization (DTCO) for Emerging Disruptive Logic & Embedded Memory Process Technologies
25. A Surface Potential- and Physics- Based Compact Model for 2D Polycrystalline-MoS2FET with Resistive Switching Behavior in Neuromorphic Computing
26. A Wireless Multi-Channel Capacitive Sensor System for Efficient Glove-Based Gesture Recognition With AI at the Edge.
27. Low Subthreshold Swing and High Mobility Amorphous Indium–Gallium–Zinc-Oxide Thin-Film Transistor With Thin HfO2 Gate Dielectric and Excellent Uniformity.
28. A $7\times7\times2$ mm3 8.6- $\mu$ W 500-kb/s Transmitter With Robust Injection-Locking-Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications.
29. An 8.2- $\mu$ W 0.14-mm2 16-Channel CDMA-Like Capacitance-to-Digital Converter.
30. A Compact Model for 2-D Poly-MoS2 FETs With Resistive Switching in Postsynaptic Simulation.
31. Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI.
32. MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond
33. A Physics-Based Compact Model for Transition-Metal Dichalcogenides Transistors With the Band-Tail Effect.
34. Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
35. FETs on 2-D Materials: Deconvolution of the Channel and Contact Characteristics by Four-Terminal Resistance Measurements on WSe2 Transistors.
36. Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.
37. Effects of Negative-Bias-Temperature-Instability on Low-Frequency Noise in SiGe p MOSFETs.
38. Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching 1 \times 10^-9 Ohm-cm2.
39. Calibration of the Effective Tunneling Bandgap in GaAsSb/InGaAs for Improved TFET Performance Prediction.
40. Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes.
41. Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO2/n-Si Contact.
42. Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source.
43. A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs.
44. Diffusion and Gate Replacement: A New Gate-First High- $k$ /Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry.
45. Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node.
46. Bendable and Stretchable Microfluidic Liquid Metal-Based Filter.
47. Low-Frequency Noise Characterization of GeOx Passivated Germanium MOSFETs.
48. Vertical GAAFETs for the Ultimate CMOS Scaling.
49. Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs.
50. Fabrication and Analysis of a Si/Si0.55Ge0.45 Heterojunction Line Tunnel FET.
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