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The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO2 and the impact of the defect layer on devices. The deep-level transient spectroscopy (DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N+/P-junction exhibits stronger temperature dependence than that of the P+/N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensive SiC N+/P-junction by 42 times at 150 °C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V. [ABSTRACT FROM AUTHOR]

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate CMOS integration that is fully compatible with a commercial double-implanted MOS (DMOS) process in 4H-SiC without requiring additional masks and cost. The characteristics of the NMOS, the PMOS, the CMOS inverter, and the ring oscillators are measured up to 175 °C. Propagation delay is reduced from 117 ns at room temperature to 17.8 ns at 175 °C, thanks to the increased current capability of both the NMOS and the PMOS. The body effect from the high substrate voltage on the PMOS is also investigated. The characteristics of the PMOS and the CMOS inverter are measured for a substrate voltage up to 800 V. The propagation delay for the ring oscillator is also measured when the substrate voltage is 300 V. [ABSTRACT FROM AUTHOR]

In this article, the degradation mechanism of the Ge N+-P junctions with a thin GeSn surface layer is investigated, aiming for source/drain (S/D) application in emerging field-effect transistors. GeSn is a promising channel material with high carrier mobility, which can offer a better performance of the field-effect transistors. By performing thermal annealing at different temperatures, the reverse-biased leakage current increases apparently when annealing temperature exceeds 550 °C. X-ray diffraction (XRD) analysis indicates most Sn atoms escape from lattice sites while secondary-ion mass spectroscopy (SIMS) analysis indicates enhanced Sn diffusion in Ge bulk after ion implantation. Therefore, a degradation model considering Sn-defects interaction is proposed to explain the degradation of junction leakage current and possible solution is proposed. [ABSTRACT FROM AUTHOR]

It has been reported that Ar plasma treatment on the n-type 4H-SiC surface before metal deposition can reduce the contact resistance. In that work, the n+ layer was formed by ion implantation at room temperature (RT). In this paper, it is found that Ar plasma treatment on the high-temperature (HT) implanted n+ layer degrades but not improves the contact resistance. A composition of RT/low-energy and HT/high-energy ion implantation can achieve low sheet resistance of the n+ layer and low contact resistance simultaneously. A twofold mechanism is proposed that the amorphous interfacial layer produced by Ar plasma treatment reduces the Schottky barrier height and the defects generated by RT ion implantation enhance current conduction by trap-assisted tunneling. [ABSTRACT FROM AUTHOR]

The effects of Ar inductively coupled plasma (ICP) treatment followed by a 600 °C–1000 °C rapid thermal annealing (RTA) on the n-type 4H-silicon carbide (SiC) Schottky-barrier diodes and n+-implanted ohmic contacts were investigated. The ICP treatment created a 3-nm-thick, sp2–C-rich, and amorphous layer at the SiC surface. The RTA repaired the bombardment-induced damages before metal deposition to avoid current degradation. This ICP + RTA-treated surface strongly pinned the Schottky-barrier height (SBH) at a minimum of 0.88 eV. In theory, the low SBH is beneficial to decrease the specific contact resistance ($\rho _{C}$). $\rho _{C}$ of the ICP + RTA-treated Ti ohmic contacts decreased to lower than $10^{-{5}} \,\,\Omega \cdot \text {cm}^{{2}}$ after 400 °C postmetal deposition annealing (PMDA). However, the additional O atoms, fixed in the amorphous layer by RTA, affected the $\rho _{C}$ reduction. Fortunately, due to the chemical affinity for O of Ti, the in-diffused Ti could contend for the O atoms against the Si–O bonds during the PMDA. Therefore, the oxidized barricade was decomposed gradually, leading to the lowest $\rho _{C}$ , $1.3\times 10^{-{6}} \,\,\Omega \cdot \text {cm}^{{2}}$ , after 600 °C PMDA. The lowest $\rho _{C}$ is $25\times $ and $8\times $ lower than that of the Ni silicide and the nontreated Ti contacts, respectively, at the same doping concentration. [ABSTRACT FROM AUTHOR]

The effects of Ar inductively coupled plasma (ICP) treatment on the Ohmic contact on n+-implanted SiC were investigated in this letter. The effects of ICP treatment were negligible on the Ni-silicide contact, because the treated surface layer was consumed during silicide formation. However, for the Ti contact, as the annealing temperature increased, the ion-bombardment-induced damage layer transformed to a uniform amorphous C-rich layer, and the specific contact resistance of the ICP-treated Ti contact decreased to 8.3\times 10^-7~\Omega -cm2 after 600 °C annealing. This is the lowest value achieved at such a low process temperature. Thus, appropriate ICP treatment and annealing can be used to form low-resistivity Ohmic contacts with a lower thermal budget that are comparable with Ni-based silicide Ohmic contacts. [ABSTRACT FROM AUTHOR]

Effects of hot phosphorus (P) implantation on the NiGe-contacted Ge n+/p junction are studied in this work. At an adequately high ion-implantation temperature (150°C), the P depth profiles of the hot-implanted samples are similar to that of the room-temperature implanted ones. Hot P implantation is demonstrated effectively in reducing ion implantation induced defect formation and suppressing nickel atoms diffusion. Therefore, hot P implantation is efficient in lowering junction leakage and excellent junction characteristics exhibiting \sim 1\times 10^6~J \mathrm{\scriptscriptstyle ON}/J \mathrm{\scriptscriptstyle OFF} ratio is achieved. [ABSTRACT FROM PUBLISHER]

In this letter, the electrical properties of local oxidation of silicon (LOCOS) field oxide formed on 4H-SiC are reported. Moreover, unlike the conventional Si LOCOS process, a simpler method based on Ar preamorphization implantation is proposed. In addition to direct characterization of the field oxide, device properties achieved using LOCOS isolation are compared with those achieved using the conventional chemical vapor deposition oxide isolation to clarify the impact of isolation technology. The results of this letter would be insightful for silicon-carbide-based very-large-scale integration technology. [ABSTRACT FROM PUBLISHER]

Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications. [ABSTRACT FROM PUBLISHER]