86 results on '"Tsui, Bing-Yue"'
Search Results
2. A 4H-SiC Trench MOS Capacitor Structure for Sidewall Oxide Characteristics Measurement
3. A Study on the Impact of Gamma Rays Irradiation on 4H-SiC CMOSFETs
4. Investigation of Positive Bias Temperature Instability of 4H-SiC MOS Capacitors and Deep Interface States Extraction at 300°C
5. Characterization of 4H-SiC PMOSFET with P+ Poly-Si Gate
6. A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact
7. Investigation of Safe Operating Area on 4H-SiC 600V VDMOSFET with TLP and UIS Test Methods
8. Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C
9. Dual Gate Oxide CMOS Process on 4H-SiC
10. An Evaluation for Quality Inspection of Epitaxial Layer and Heavily-doped 4H-SiC Substrate by Simple Schottky Barrier Diode and MOS Capacitor
11. Device isolation process for 4H-SiC CMOS ICs
12. High Voltage Gain 4H-SIC CMOS Technology Featuring LOCal Oxidation of SiC (LOCOSiC) Isolation and Balanced Gate Dielectric
13. A Study on the Isolation Ability of LOC al O xidation of SiC (LOCOSiC) for 4H-SiC CMOS Process.
14. Mechanism of Degradation of Ge NMOSFET with Channel Ion Implantation and Its Recovery
15. Time-Dependent Dielectric Breakdown of Gate Oxide on 4H-SiC with Different Oxidation and Isolation Processes
16. Extraction of Ultra-Low Contact Resistivity by End-Resistance Method
17. 1100 V, 22.9 mΩcm 2 4H-SiC RESURF Lateral Double-Implanted MOSFET With Trench Isolation.
18. Failure Analysis on TiAl Metallization Process for Ohmic Contact on 4H-SiC pMOSFET
19. Thermal Stability of Shallow Ge N+-P Junction with Thin GeSn Top Layer
20. Demonstration of CMOS Integration With High-Voltage Double-Implanted MOS in 4H-SiC.
21. Degradation Mechanism of Ge N+-P Shallow Junction With Thin GeSn Surface Layer.
22. Effects of vanadium incorporation on the electron schottky barrier height reduction of NiGe/Ge
23. A comprehensive evaluation of the performance of fin-type epitaxial tunnel layer (ETL) tunnel FET
24. Scaling of gate dielectric on Ge substrate
25. Effect of Ion-Implantation Temperature on Contact Resistance of Metal/n-Type 4H-SiC With Ar Plasma Treatment.
26. Effects of Rapid Thermal Annealing on Ar Inductively Coupled Plasma-Treated n-Type 4H-SiC Schottky and Ohmic Contacts.
27. Effect of formation temperature on quality of gate dielectric on germanium substrate
28. Re-examination the effects of selenium segregation on the Schottky barrier height reduction of the NiGe/Ge contact
29. A reliable Schottky barrier height extraction procedure
30. Session 9: Process and device characterization
31. Reduction of Specific Contact Resistance on n-Type Implanted 4H-SiC Through Argon Inductively Coupled Plasma Treatment and Post-Metal Deposition Annealing.
32. Reduced Junction Leakage by Hot Phosphorus Ion Implantation of NiGe-Contacted Germanium n+/p Shallow Junction.
33. Evaluation of electrical performance of various tunnel TFETs
34. Thin effective oxide thickness (∼0.5 nm) and low leakage current gate dielectric for Ge MOS devices by plasma nitrided Al2O3 intermediate layer
35. Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation.
36. Simulation of grain-boundary traps effect for 3D vertical gate NAND flash memory cell : From structure geometry to trap description
37. First-principles calculations on the schottky barrier height of the NiGe/N-type Ge contact with dopant segregation
38. Evaluation of ultra-low specific contact resistance extraction by cross-bridge Kelvin resistor structure and transmission line method structure
39. A comparison study on the Al-based interfacial layers for Ge MIS devices.
40. Investigation into the performance of CNT-interconnects by spin coating technique
41. Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure.
42. Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device
43. A new procedure to extract ultra-low specific contact resistivity
44. A study on poly-Si thin-film transistor (TFT) SONOS memory cells with source/drain engineering
45. Low-temperature wafer-scale fabrication of carbon nanotube network TFT: Geometry effect and transport mechanism
46. Achieving high-performance poly-Si TFTs by structural engineering
47. A quantum approach to nanocrystal nonvolatile memory
48. Extreme ultra-violate exposure induced damages on non-volatile memories
49. A 30 nm gate-all-around poly-Si nano wire thin-film transistor
50. Low Threshold Voltage CMOSFETs with NiSi Fully Silicided Gate and Modified Schottky Barrier Source/Drain Junction
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.