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3.3 kV Schottky barrier diodes and Junction Barrier Schottky diodes have been fabricated, employing a phosphorous pentoxide $\left(P_{2}O_{5}\right)$ surface treatment prior to metal deposition in an attempt to further condition the power device’s interface. For SBD structures, the treatment consistently reduces the leakage current in molybdenum, tungsten and niobium SBDs, for the tungsten treatment by more than four orders of magnitude. X-ray photoelectron spectroscopy (XPS) analysis on the treated SBD interface revealed formation of a metal phosphate between $P_{2}O_{5}$ and the metal. When compared to an untreated sample, the $P_{2}O_{5}$ treatment has increased the valence band to fermi level offset by 0.2 eV to 3.25 eV, indicating that the treatment results in a degenerately n-doped SiC surface. When applied to fully optimised 3.3 kV JBS power structures utilizing a hybrid JTE design, $P_{2}O_{5}$ treatments improved blocking capabilities across the entire dataset by as much as 1,000 V.

A class of vertical 1700-V 4H-SiC superjunction (SJ) Schottky diodes have been simulated and optimized, producing results that are below the unipolar limit, while also ensuring practical and costeffective realization. A conventional vertical SJ is obtained in T-CAD software, using an n-type drift region of 9- $\mu \text{m}$ and etching trenches through this region to the substrate to leave isolated mesa structures. P-columns are then created through implantation into the trench sidewalls. The charge-balanced SJ diode maximizes the breakdown voltage ( ${V}_{\text {BD}}$ ) and minimizes the specific ON-resistance ( ${R}_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ ). However, a narrow implantation window would make the vertical structure hard to fabricate. Therefore, by introducing an angled trench sidewall ( $\alpha $ ), 10° off vertical, a graded charge profile is introduced reducing ${V}_{\text {BD}}$ by 2.5% and increasing ${R}_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ by 9%. However, the implantation window is widened by 20% compared with the vertical device, making the successful production of the devices more likely. To rebalance the 10° structure, a 1- $\mu \text{m}$ region of increased n-type doping is introduced at the top of the n-pillar. This partially recovers the lost ${V}_{\text {BD}}$ and ${R}_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ while maintaining an implantation window wider than the vertical SJ. The balance between ${R}_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ and implantation window can be tuned depending on the doping of the 1- $\mu \text{m}$ top region. The 10° structure can also be rebalanced by introducing a second 4- $\mu \text{m}$ region of intermediate n-type doping, underneath the 1- $\mu \text{m}$ surface region. This recovers $R_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ , while maintaining an implantation window that is 7% wider.

We have experimentally verified a compact trench-assisted space-modulated junction termination extension (TSM-JTE) structure which has been designed for high voltage SiC devices. The proposed termination design introduces shallow trench structures into the conventional JTE implanted region, effectively creating a multi-zone JTE with a single implant, and hence greatly broadens the process window for a JTE termination. The TSM-JTE structure is compact and cost effective especially at higher voltages (≥ 10 kV) as it consumes less chip area while requiring only a single implant for the termination region. In this paper, 5 kV and 10 kV SiC PiN diodes have been fabricated and characterized.

Knowledge of the mechanical properties and stability of thin film structures is important for device operation. Potential failures related to crack initiation and growth must be identified early, to enable healing through e.g. annealing. Here, three square suspended membranes, formed from a thin layer of cubic silicon carbide (3C-SiC) or germanium (Ge) on a silicon substrate, were characterised by their response to ultrasonic excitation. The resonant frequencies and mode shapes were measured during thermal cycling over a temperature range of 20–100 °C. The influence of temperature on the stress was explored by comparison with predictions from a model of thermal expansion of the combined membrane and substrate. For an ideal, non-cracked sample the stress and Q-factor behaved as predicted. In contrast, for a 3C-SiC and a Ge membrane that had undergone vibration and thermal cycling to simulate extended use, measurements of the stress and Q-factor showed the presence of damage, with the 3C-SiC membrane subsequently breaking. However, the damaged Ge sample showed an improvement to the resonant behaviour on subsequent heating. Scanning electron microscopy showed that this was due to a self-healing of sub-micrometer cracks, caused by expansion of the germanium layer to form bridges over the cracked regions, with the effect also observable in the ultrasonic inspection. [2020-0017]

Malware is one of the major issues regarding the operating system or in the software world. The android system is also going through the same problems. We have seen other Signature-based malware detection techniques were used to detect malware. But the techniques were not able to detect unknown malware. Despite numerous detection and analysis techniques are there, the detection accuracy of new malware is still a crucial issue. In this paper, we study and highlight the existing detection and analysis methods used for the android malicious code. Along with studying, we propose Machine learning algorithms that will be used to analyze such malware and also we will be doing semantic analysis. We will be having a data set of permissions for malicious applications. Which will be compared with the permissions extracted from the application which we want to analyze. In the end, the user will be able to see how much malicious permission is there in the application and also we analyze the application through comments.

The intentional non-use of technology has become an increasingly popular practice, yet the scholarly literature on this topic is limited, being largely been framed as the lack of something rather than a phenomenon in itself. This paper reports on the analysis of over 300 disconnection narratives, the texts of which were analyzed by means of R software. Expected terms associated with phones and social media were identified, but descriptions of the assumed benefits of disconnecting, such as higher quality relationships, more productive work, and better sleep, were not found. However, overall sentiment was positive. This study will ground further research on a large scale, using big data sets drawn from social media platforms.

This study deals with the formulation of a technology-based solution to the problem of unemployment in underserved communities. Jobs for low-skilled and unskilled labor in the informal economy are acquired by means of referrals and contacts, but this approach suffers from making employment related information privileged only to a few individuals. In order to gauge the feasibility of a technology solution, the employment seeking process was studied through interviews conducted with all stakeholders - employers, candidates and intermediaries like NGOs and employment agencies. The studies were conducted at slum communities in Ahmedabad, India. After the interviews, two questionnaires were developed that drew from the interviews, one for the members of the community and the other for employers who recruited from the community. The employers also went through a semi-structured interview in order to capture any pertinent data that was not represented in the questionnaire. Based on the responses to the surveys a preliminary version of the system was constructed.

Germanium membranes of 50–1000 nm thickness have been fabricated by a combination of epitaxial growth on a Si substrate and simple etching processes. The biaxial tensile strain in these membranes has been measured by high-resolution X-ray diffraction and by ultrasonic vibrational spectroscopy. The later technique also shows that membranes have a Q-factor of ∼3000 at low temperature. The stain in these membranes is extremely isotropic and the surface is observed to be very smooth, with an rms roughness of below 2 nm. The process of membrane fabrication also serves to remove the misfit dislocation network that originally forms at the Si/Ge interface, with benefits for the mechanical, optical and electrical properties of the crystalline membranes.

Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of crystalline planes that have different etch resistance. The structures are aligned to avoid etch-resistive planes in making the suspended regions and to take advantage of these planes to retain the underlying Si to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and van der Pauw cross structures. We finally report on the low-temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the Ge resistivity to 280 Ω cm at 10 K, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.

We present magneto-transport properties of the two dimensional hole gas (2DHG) in fully strained Ge quantum wells grown on Si0.2Ge0.8/Si (100) substrates. Comparison is made between heterostructures that are modulation doped in both normal and inverted configurations. Using Shubnikov de Haas oscillations at temperatures down to 90 mK (inverted structure) and to 1.5K (normal structure), an extremely high hole mobility (0.51-1.34) × 106 cm2/Vs has been observed, along with the lowest value of effective mass (0.063-0.070) m0 to date. The 2DHG is confirmed to be in a pure Ge channel, with low background impurity scattering that improves the 2DHG transport.

The effect of the phonon confinement on the acoustic dispersion relation is studied in 60 nm thick free-standing germanium membranes. The detection of phonon modes is observed by Brillouin Light scattering spectroscopy. The quadratic behavior of fundamental flexural wave is detected. The theoretical dispersion relation is also determinate using elastic continuum model.

We show good quality (GeO2) layer grown on epitaxial germanium on a Si substrate. The oxidation was done at two temperatures, 450°C and 475°C. The oxidation at 475°C was done for 30min and 60min. It was found that the layers growth at 475°C show higher quality.

It has been observed that at lower growth temperatures, epitaxial layers of Si1-xGex on Si(001) can be grown beyond the predicted critical thickness[1] for plastic relaxation [2]. These layers are known as metastable, since if raised to a temperature higher than their growth temperature, relaxation will occur. A number of comprehensive studies have been published for Si1-xGex epilayers with a low Ge composition, including the recent work with a Ge content up to 52% [2]. However, no work has been carried out on higher Ge composition layers i.e. above 60% . Since the strain in the layer is proportional to its lattice mismatch with the Si substrate, layers with higher Ge composition will exhibit a higher degree of compressive strain. This higher strain ought to enhance a room-temperature two-dimensional hole gas (2DHG) mobility in a Si0.4Ge0.6 quantum well (QW) grown pseudomorphically on a Si(001) substrate. This property is very important for application of such materials in electronic devices like Field Effect Transistors (FETs) and others. It is also very important to maintain the SiGe QW thickness around or above 10 nm in order to minimize negative effect of interface scattering on 2DHG mobility. In this work, we demonstrate that highly strained epilayers of Si0.4Ge0.6 can be grown pseudomorphically on a Si (001) substrate with thicknesses up to ~25 nm, which is is significantly above the thickness usually accepted as being stable or even metastable. Epitaxial layers were grown in an industrial reduced pressure chemical vapour deposition (RP-CVD) system. Standard, commercial available disilane and germane precursors were used. The epilayer thicknesses were obtained by XTEM analysis and high resolution X-ray diffraction HR-XRD. The epilayer surface morphology was analyzed by atomic force microscopy (AFM) and defects observed in the relaxed epilayers were analyzed by combination of plan view transmission electron microscopy PV-TEM and AFM. We report that it was possible to grow up to 24nm of Si0.4Ge0.6 before strain relaxation occurred. For epilayers thinner than 24 nm a surface roughness comparable to that of the Si substrate was observed, for example the 21 nm layer showed an RMS roughness of 0.08 nm (Figure 2). These thin layers produced rocking curves with clearly defined thickness fringes (Figure 1) that indicate no relaxation by defect formation. Above 24 nm, the layers showed a high surface roughness with the characteristic crosshatch pattern (Figure 3). This indicates non-uniform elastic strain fields from dislocations [3] , suggesting strain relaxation. Above 24 nm the thickness fringes seen in the rocking curves rapidly reduced in intensity compared to the thinner layers, which is also indicative of strain relaxation. A thickness of 24 nm of strained Si0.4Ge0.6 on Si (001) is higher than any attempts at growth of this strained alloy directly on Si reported previously. The results obtained show very high potential for application of highly strained Si0.4Ge0.6/Si(001) structures in a variety of electronic and photonic Si based devices. Detailed characterisation will be presented along with growth details. [1]R. People and J. C. Bean,'Calculation of critical layer thickness versus lattice mismatch for GexSi1−x/Si strained-layer heterostructures', Appl. Phys. Lett., vol. 47, no. 3, p. 322, 1985. [2] J. M. Hartmann, A. Abbadie, and S. Favier,'Critical thickness for plastic relaxation of SiGe on Si(001) revisited', Journal of Applied Physics, vol. 110, no. 8, p. 083529, 2011. [3] H. Chen, Y. Li, C. Peng, H. Liu, Y. Liu, Q. Huang, J. Zhou, and Q.-K. Xue,'Crosshatching on a SiGe film grown on a Si(001) substrate studied by Raman mapping and atomic force microscopy',Physical Review B, vol. 65, no. 23, May 2002.

In this work, we report a hole mobility of one million in germanium. This extremely high value of 1.1 x 106 cm2V-1s-1 at a carrier sheet density of 3.0 x 1011 cm-2 was observed in a strained Ge quantum well structure grown by reduced-pressure chemical vapor deposition (RP-CVD) and is nearly an order of magnitude higher than previously reported values [1]. Compressively strained Ge offers considerable promise as an alternative channel conduction material to Si because of its previously reported high hole mobility of 120,000 cm2V-1s-1 (at 2 K) [1] in two-dimensional hole gases (2DHG) in modulation-doped SiGe heterostructures [2-4]. Previous studies have used growth techniques such as molecular beam epitaxy (MBE) and low energy plasma enhanced chemical vapor deposition (LEPE-CVD), or a combination of these techniques to take advantage of their low growth rates for accurate control of the epitaxial layer properties. However, recent developments in low temperature epitaxy using reduced-pressure CVD (RP-CVD) now makes it possible using an industrially compatible process to control the thickness of strained epitaxial layers to within a few monolayers [5] and achieve very high levels of purity. The heterostructure studied in this work is shown in Fig. 1. All layers were grown by reduced pressure CVD (RP-CVD) using an ASM Epsilon 2000 reactor and employed a reverse-linearly graded Si0.2Ge0.8 relaxed buffer with low surface roughness (rms value ~ 2 nm, crosshatch spatial wavelength ~ 2 m) and threading dislocation density (≤ 4 x 106 cm-2) [6-7]. The active region included a 20 nm biaxial compressively strained Ge QW, that was grown at low temperature to prevent any relaxation [8]. High resolution x-ray diffraction (HR-XRD) confirmed that the Si0.2Ge0.8 buffer was slightly over-relaxed with respect to the Si substrate and that the Ge channel was fully strained with respect to the buffer. The B-doping density was determined as ~ 1 x 1018 cm-3 using ultra low energy secondary ion mass spectrometry (uleSIMS). Hall bars were fabricated using standard lithography and wet chemical etching while Al contacts were deposited by thermal evaporation and annealed at 425 °C for 20 mins in N2 to ensure ohmic behavior. Resistivity and Hall effect measurements were performed in the temperature range 12 K - 300 K with Fig. 2 showing the Hall mobility and carrier sheet density as a function of temperature. The room temperature Hall mobility was 1200 cm2V-1s-1 and is believed to be dominated by parallel conduction through the MOD heterostructure [2]. However, at 12 K the measured Hall mobility and carrier sheet density were 1.0 x 106 cm2V-1s-1 and 3.0 x 1011 cm-2, respectively and represents the highest hole mobility observed for a 2DHG in strained Ge. Fig. 2 shows that whilst the carrier sheet density saturates, the Hall mobility continues to increase for temperatures below 60 K. Additional experiments at 0.4 K found that the Hall mobility saturated at a value of ~ 1.1 x 106 cm2V-1s-1. At low temperatures, we expect the mobility to be limited by ionized impurity scattering [1]. Our results suggest that the RP-CVD growth process has resulted in both a very low impurity and extremely pure Ge layer, so that even at 12 K ionized impurity scattering is very weak [9] and demonstrates that RP-CVD can be used to grow strained Ge QWs with exceptionally high hole mobilities.

Germanium is a logical supplement to enhance existing semiconductor technologies, as its material behavior is very similar to silicon, and allows new functional devices that cannot be fabricated from silicon alone [1]. Germanium wafers are, however, both expensive and less durable than their silicon counterparts. High quality Ge layers epitaxially grown on a Si(001) substrate can be fully relaxed, with sub-nm roughness, yet still have threading dislocation densities (TDD) down to 107cm-2. Although this is an impressively low level, it still presents major problems of dislocation leakage [2, 3] and carrier scattering that reduces the carrier lifetime [4]. Conduction along a dislocation occurs when it locally modifies the bandstructure, creating extended states in the semiconductor bandgap which allows minority carriers to be trapped [5]. This effect has previously been demonstrated at low temperatures, where the parallel conduction path of the bulk semiconductor is frozen out. The arrangement of dislocations within a relaxed, or partially relaxed, Ge layer allows carriers to be transported from the surface, via a threading dislocation, to the misfit dislocation network at the Ge/Si interface and then, potentially, to any other threading dislocation within the layer and thus back to a different point on the surface. This effect could potentially short a device's channel, wells and/or metal contacts at room temperature. In this work, we present a method to isolate this dislocation conduction within a Ge on Si layer at low temperatures through removing the Ge/Si interface to reduce dislocation leakage. We first describe a simple and extremely fast technique to create suspended Ge structures that are entirely IC clean. These suspended structures include, but are not limited to, micro/nanowires, bridge structures, Van-der Pauw cross structures, Hall-bar and spiderweb structures. The vertical dimensions of these structures are only limited by the epitaxial thickness of the layers and can potentially be fabricated using multilayered heterostructures. Examples of lateral dimensions for a 200 nm thick Ge micro/nanowire are currently a length of 200 μm with a minimum width of 2 μm, at present, limited by optical lithography. Secondly, we report on the electrical effect of removing the Ge/Si interface by fabricating Van- der Pauw cross structures which are either suspended or epitaxially still connected to the bulk substrate. Overall, we show an increase in the resistivity of the Ge epilayer by over an order of magnitude, at a temperature of 15K for a high quality 104 % relaxed layer with TDD of 107 cm-2 and a surface roughness of 0.7 nm, for both an intrinsic and a heavily phosphorous doped (>1019 cm-3) Ge epilayer.

Silicon (Si) is still the main material for mass production of a large variety of electronic and photonic semiconductor devices, whilst Boron (B) is still its primary p-type dopant. B-doping in Si has been systematically studied and continues to attract interest. In particular, ultrahigh B doping of silicon, i.e. incorporation of B at concentrations well over an order of magnitude higher than its equilibrium solubility limit, became an issue of primary importance in order to minimize contact resistance in low-dimensional devices. Unfortunately, the B solubility in Si of ~2×1019 atoms/cm3 at 700 °C is quite low and its implantation in Si is accompanied by detrimental effects like clustering and anomalous diffusion. Whilst this is the widely used non-equilibrium strategy for p-type doping of Si, it substantially limits the electrical activity and the sharpness of the B implanted profile. Alternative approaches, such as epitaxy, to incorporate B into substitutional sites have been investigated, mainly with a view to reaching high metastable incorporation during phase transformation. Attempts to incorporate a higher concentration of B in Si during epitaxial growth and to create a SiB alloy were performed in the past. The concentration level of substitutional B that can be usually reached in strained SiB epilayers is below 1 % [1]. There has been a report of B content as high as 24 % in a SiB alloy layer grown by Gas Source Molecular Beam Epitaxy (GS-MBE) [2], but until recently, there was no clear agreement on how to calculate the B content of a SiB alloy, even at the few percent level [1]. Relaxed SiB can also be formed via B ion implantation and subsequent annealing, or via surface diffusion, but such layers unavoidably contain defects that will at least degrade the electrical properties of the alloy. By contrast, epitaxy opens the possibility to grow not only relaxed SiB alloys on Si but also strained ones that are defect free and has enormous possibilities for further research and applications. In addition, epilayers can be grown selectively on pre-patterned wafers by Chemical Vapour Deposition (CVD) or GS-MBE techniques. In particular, epitaxial growth of such layers by Reduced Pressure CVD (RP-CVD) is of great importance, since it is the main technique utilized by the semiconductor industry to grow Si based structures. In this work, we present the first results of successful epitaxial growth of fully strained SiB alloy epilayers by RP-CVD. The epilayers were grown using standard and widely used Si and B gaseous precursors, diborane and disilane. Figure 1 shows a schematic cross section of the structures grown, which consist of a SiB epilayer grown directly on a Si (100) substrate. The thickness of SiB was varied from ~10 up to ~100 nm and the boron concentration was also varied. Comprehensive structural characterization was carried out using Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM), Secondary Ion Mass Spectrometry (SIMS) and high resolution X-ray diffraction (HR-XRD). Figure 2 shows typical HR-XRD (004) rocking curves measured on two samples containing fully strained ~ 100 nm thick SiB epilayers of different B content. The peak positions, and presence of fringes, indicates tensile strain in the SiB alloy epilayers and a B content above 1 %. The results obtained open wide the possibilities for further research and applications. One of which is very low-resistivity SiB contacts with potential exhibition of superconductivity at low-temperature [3].

We report on our progress towards the development of a miniature cold atom frequency standard (MCAFS). The ultimate program objective is a chip-scale atomic clock (CSAC) with performance comparable to a bench top Cesium beam primary standard. We have addressed many of the critical hurdles of this project and demonstrated its feasibility with a compact and fully integrated prototype.

We summarize recent results at NIST to develop high-performance yet highly miniaturized magnetic sensors based on atomic vapors confined in microfabricated alkali vapor cells. These sensors currently achieve sensitivities in the range of a few tens of femtotesla in a 1 Hz bandwidth in detection volumes of about 1 mm3. They require no cooling and only a small amount of heating, making them ideal for deployment in remote, power starved locations.

The physical and electrical properties of silicon layers grown by molecular beam epitaxy (MBE) on commercial 4H-SiC substrates are reported. We investigate the effect of the Si doping type, Si doping concentration, Si temperature deposition and SiC surface cleaning procedure. Si/SiC monolithic integration of Si circuits with SiC power devices can be considered as an attractive proposition and has the potential to be applied to a broad range of applications. X-ray diffraction (XRD) and scanning electron microscopy (SEM) are used to determine the Si crystal structure (cubic silicon) and morphology. I-V and C-V measurements are performed to evaluate the rectifying diode characteristics along with the Si/SiC built-in potential and energy band offsets. In the last section, we propose that our n-n Si/SiC heterojunction diode current characteristics can be explained by an isojunction drift-diffusion and thermoionic emission model where the effect of doping concentration of the silicon layer and its conduction band offset with SiC is analysed.

We demonstrate self-injection locking of a low-power, compact microwave oscillator by use of feedback generated from four-wave mixing in an atomic vapor. The four-wave mixing process creates an effective microwave filter with extremely high off-resonant signal suppression. This type of locking results in a shorter locking time, increased short-term stability, improved close-in phase noise, and reduced spurious signals as compared to current techniques used in miniature atomic clocks. Other possible benefits and drawbacks are mentioned.

We describe the first local oscillator (LO) that demonstrates viability in terms of performance, size, and power, for chip-scale atomic clocks (CSAC) and has been integrated with the physics package at the National Institute of Standards and Technology (NIST) in Boulder, CO. This voltage-controlled oscillator (VCO) achieves the lowest combined size, DC power consumption, phase noise, and thermal frequency drift among those previously reported, while achieving a tuning range large enough to compensate for part tolerances but small enough to permit precision locking to an atomic resonance. We discuss the design of the LO and the integration with the NIST physics package.

An optically pumped magnetometer was drastically miniaturized, by taking advantage of MEMS techniques, producing the chip-scale atomic magnetometers (CSAM) physics package. The key component of the package is an alkali vapor cell. To probe the magnetic field experienced by the atoms, the injection current to the VCSEL was modulated at 3.4 GHz near half the hyperfine frequency of 87Rb. Lock-in detection is used to determine the center of the resonance, and the magnetic field is determined by counting the modulation frequency, which is related to the Larmor precession frequency under these locked conditions. The ITO heaters create a large magnetic field gradient, which broadens the resonance and reduces the sensitivity.

We demonstrate component-level functionality of the three critical subsystems for a miniature atomic clock based on microfabrication techniques: the physics package, the local oscillator and the control electronics. In addition, we demonstrate that these three components operating together achieve a short-term frequency instability of 6times10-10/radictau, with a total volume below 10 cm 3 and a power dissipation below 200 mW

In the submillimeter (SMM) region of electro-magnetic spectrum, heterodyne techniques are widely used to achieve high spectral resolution. The SMM source signal and a known local oscillator signal are mixed in a nonlinear device in order to generate an intermediate frequency (IF), which retains the spectrum of SMM source. The IF1 thus obtained from first mixer stage is down converted to required frequency of 1250 MHz to make it suitable for further processing in spectrometer. To extract the spectral information of source signal various spectrometers are used. The chirp transform spectrometer (CTS) is the state-of-the-art spectrometer (Hartogh and Hartmann, 1990) to achieve very high frequency resolution. The key element of CTS is a surface acoustic wave (SAW) based chirp filter capable of providing desired frequency resolution. We present the details of system design of the spectrometer, digital generation of expander chirp signal and the reflective array compressor (RAC) type SAW chirp filter.

Limitations imposed by the atmosphere at terahertz (THz) frequencies have restricted researchers from retrieving crucial information regarding astronomical sources. With the availability of sensitive detectors and new generation of telescopes, the terahertz instrumentation has improved drastically over the past two decades. High spectral resolution information retrieved from star forming molecular system is very essential in understanding the model of evolution process of stars and galaxies. In this paper, we will present the development of a submillimeter wave (300-3000 GHz) receiver system to study interstellar molecular clouds dynamics and chemistry.

We report recent improvements on our microfabricated atom-optical magnetometer. Using a semiconductor laser and 1 mm3 alkali vapor cell, our magnetometer detects a magnetic field at 50 pT / Hz1/2 sensitivity in a 12 mm3 package.

We compare the performance of two chip-scale atomic clock physics packages, one based on excitation using the D/sub 2/ line of Cs and the other using the D/sub 1/ line of /sup 87/Rb.

The physics package of a vertically integrated chip-scale atomic clock, based on cesium, has recently been demonstrated at NIST. This device requires 69 mW of electrical power to maintain the vapor cell 34 K above the temperature of the baseplate. The physics package structure is analyzed by use of analytical thermal modeling and finite-element calculation. Improvements to the design are proposed to reduce the power consumption of the physics package alone to near 15 mW and of a full chip-scale atomic clock to below approximately 30 mW. Power consumption at this level will open the door to the use of atomic frequency references in portable, battery-operated applications such as wireless communications and global positioning.