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In this paper, a fuel-based distributed generator (DG) allocation strategy is proposed to enhance the distribution system resilience against extreme weather. The long-term planning problem is formulated as a two-stage stochastic mixed-integer programming (SMIP). The first stage is to make decisions of DG siting and sizing under the given budget constraint. In the second stage, a post-extreme-event-restoration (PEER) is employed to minimize the operating cost in an uncertain fault scenario. In particular, this study proposes a method to select the most representative scenarios for the SMIP. First, a Monte Carlo Simulation (MCS) is introduced to generate sufficient scenarios considering random fault locations and load profiles. Then, the number of scenarios is reduced by the K-means clustering algorithm. The advantage of scenario reduction is to make a trade-off between accuracy and computational efficiency. Finally, the SMIP is solved by the progressive hedging algorithm. The case studies of the IEEE 33-bus and 123-bus test systems demonstrate the effectiveness of the proposed algorithm in reducing the expected energy not served (EENS), which is a critical criterion of resilience. [ABSTRACT FROM AUTHOR]

In this paper, we present friendly jamming for secure location verification of vehicles in Intelligent Transportation Systems (ITS). In friendly jamming confidential information is obscured from eavesdroppers through the use of opportunistic jamming on the part of the parties engaged in communication. Secure location verification enables the infrastructure in an ITS to verify the position claims of a vehicle in an adversarial setting. We present a method for effectively using friendly jamming and distance bounding together to verify the location and velocity of vehicles, and detect any deviation of claims by a “prover” vehicle that is trying to prove its position and velocity to the infrastructure. The technique can be used to verify velocity and position claim of a vehicle, while keeping the feasible velocity and position lie by an attacker in a negligible range. Our analysis shows that in realistic traffic, friendly jamming is an improvement over comparable work, reducing position falsification by 86.66% to 92% for a typical attacker. The proposed technique also outperforms existing localization techniques for multiple colluding attackers, providing security against up to three colluding attackers, where colluders coordinate their movement and report information to help a single attacker achieve its goal. [ABSTRACT FROM AUTHOR]

A new low-complexity message passing algorithm is described for decoding low-density parity-check (LDPC) codes by exchanging binary messages. The algorithm computes the local maximum-likelihood binary message (LMLBM) at each symbol node, given the combination of local channel information and partial syndrome components from adjacent parity check nodes. When channel information is quantized, the locally ML messages are pre-computed and stored in a dynamic global lookup table. The proposed algorithm uses memoryless extrinsic messages so that density evolution thresholds can be directly computed. Thresholds are obtained for regular ensembles, predicting good performance on quantized binary-input additive white Gaussian noise (biAWGN) channels. [ABSTRACT FROM PUBLISHER]

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed. [ABSTRACT FROM AUTHOR]

Techniques are evaluated for implementing error correction codes in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed, and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub-VT implementation is predicted to offer 29\times gain in power consumption for a (3,6) low-density parity-check decoder of length N = 512 operating at a throughput of 200 Mb/s, compared to standard digital implementation of the same design. [ABSTRACT FROM AUTHOR]

Editors' notes: [ABSTRACT FROM AUTHOR]

Stochastic decoding is a recently proposed approach for graph-based iterative error control decoding. We present and investigate three hysteresis methods for stochastic decoding on graphs with cycles and show their close relationship with the successive relaxation method. Implementation results demonstrate the tradeoff in bit error rate performance with circuit complexity. [ABSTRACT FROM PUBLISHER]

A method is proposed for computing with unreliable nanoscale devices that have a high rate of transient errors. Errors are corrected using a probabilistic circuit in which device noise is leveraged as a computational asset. Example designs that achieve a low output bit error probability are presented. The effect of permanent defects is also evaluated, and transient device noise is found to be beneficial for correcting hard defects for defect rates of as high as 0.1% and transient fault rates above 1%. When compared with existing fault-tolerant methods, the sample design requires considerably fewer redundant gates to achieve reliable operation. These results predict that some degree of engineered randomness may prove to be a useful signal-processing feature in future nanoelectronic systems. [ABSTRACT FROM AUTHOR]

A built-in self-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation. [ABSTRACT FROM AUTHOR]

Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as TUrbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5-µm process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm², and typical power consumption is 1 mW at 1 Mb/s. Index Terms—Analog decoding; error-control codes; iterative decoders; maximum a posteriori (MAP) decoding; translinear circuits. [ABSTRACT FROM AUTHOR]