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Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse ID – VG technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated. [ABSTRACT FROM AUTHOR]

The recently discovered ferroelectric behavior of HfO2-based dielectrics yields the potential to overcome the main challenges of the ferroelectric field-effect transistors (FeFETs)—CMOS compatibility as well as scalability to the state-of-the-art technology nodes of logic transistors. In this paper, we study the impact of scaling on the memory performance of FeFET devices employing Si:HfO2 ferroelectric films. The operation capability was proven down to a gate length of 28 nm. Program/erase characteristics, endurance behavior, and retention properties were analyzed for FeFETs with gate lengths scaled down to 32 nm. The detected difference in the performance between the long and short channel devices could be for the most part attributed to transistor short channel effects. In addition, the effect of temperature on the device properties of Si:HfO2-based FeFETs was investigated in detail. The program/erase speed was ascertained to be independent of temperature. On the other hand, increase in temperature resulted in reduced initial memory window accompanied by its slightly accelerated decay with time. [ABSTRACT FROM AUTHOR]

Ferroelectric Si:HfO2 has been investigated starting from metal–ferroelectric–metal (MFM) capacitors over metal–ferroelectric–insulator–semiconductor (MFIS) and finally ferroelectric field-effect-transistor (FeFET) devices. Endurance characteristics and field cycling effects recognized for the material itself are shown to also translate to highly scaled 30-nm FeFET devices. Positive-up negative-down as well as pulsed Id{-}Vg measurements illustrate how ferroelectric material characteristics of MFM capacitors can also be identified in more complex MFIS and FeFET structures. Antiferroelectric-like characteristics observed for relatively high Si dopant concentration reveal significant trapping superimposed onto the ferroelectric memory window limiting the general program/erase endurance of the devices to 10^4 cycles. In addition, worst case disturb scenarios for a VDD/2 and VDD/3 scheme are evaluated to prove the viability of one-transistor memory cell concepts. The ability to tailor the ferroelectric properties by appropriate dopant concentration reveals disturb resilience up to 10^6 disturb cycles while maintaining an ION to IOFF ratio of more than four orders of magnitude. [ABSTRACT FROM PUBLISHER]