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The increasing complexity of real-life applications demands constant improvements of microprocessor systems. One of the most frequently adopted microprocessor design scheme is the von Neumann architecture. Central Processing Unit (CPU) performs computations and communicates with memory in a constant exchange of information. This unceasing motion of data between these two components became a significant performance bottleneck. A lot of power, energy, and computational time are wasted in this communication. With Beyond von Neumann Computing (BvNC) paradigms, calculations are performed inside or very close to a memory array. BvNC approaches are proposed in the literature, mainly based on modifications of existing memories, enabling simple computations. Others exploit emerging technologies to both store and compute data, using analog operations. In this work we follow a different approach, where computational units are placed close to memory cells, improving versatility and performance. We propose a Hybrid-SIMD architecture made of memory and computing elements in an interleaved structure. Hybrid-SIMD can be used both as a low density memory and as SIMD accelerator. We insert our design in a classical von Neumann system based on a RISC-V processor, and we estimate its impact, demonstrating its capability to improve speed reducing at the same time energy consumption. [ABSTRACT FROM AUTHOR]

Nanomagnet logic (NML) is one of the most novel solutions studied as complementary technology to CMOS transistors. Information propagation involves only a change in spin orientation, no charge movement is present. Since the basic element is a nanomagnet, NML circuits have no stand-by power consumption and the ability to mix logic and memory in the same device. While CMOS is a multilayer technology, until now NML is confined to one single physical layer. The consequence is that circuit area grows exponentially due to interconnections overhead. In this paper, we present an innovative solution that drastically reduces the area wasted for interconnection wires relying on the properties of domain walls (DWs). We mix DWs and NML technologies in a unique DW logic (DWL) solution that exploits the advantages of both technologies. The proposed solution is technologically compatible with up-to-date fabrication processes. All the results here presented for the NML logic blocks and the DWs interconnections and their combination are obtained through rigorous micromagnetic simulations. Moreover, we implemented as a case study an high performance adder (Pentium 4 adder) and evaluated its features with increasing parallelism and compared with the simple NML implementation in order to explore the potential of DWL technology at circuit and architectural level. The reduction in circuit area corresponds to a notable reduction in both the latency and power consumption. The improvements in NML technology are shown by both the remarkable performance improvement and new possibilities offered by this novel solution. [ABSTRACT FROM AUTHOR]

Emerging technologies are gaining an increasing attention due to the slowdown of CMOS development. NanoMagnet Logic (NML), among emerging technologies, increases the potentials for developing fully magnetic circuits. Using a magnet as a building block for logic circuits has the advantage to merge logic and memory in the same device. Moreover, circuits have low dynamic and no stand-by power consumption. Even though demonstrations exist for small circuits, the experimental feasibility of complex NML circuits still represents a critical point for this technology. In this paper, we outline the possibility to design NML circuits based on the technological structure of magnetic RAMs (MRAMs). NML circuits based on MRAMs rely on a well-developed technology that provides a natural interface with CMOS world. To study this new NML implementation a novel tool, NANOcom, was developed to easily design complex circuits. Simulations were then performed using an high-level behavioral model described using VHDL language. Two types of circuit layouts, based on different technological constraints, are investigated. To evaluate the performance of this new NML implementation, a 4-bit Galois multiplier is used as a testbench. The Galois multiplier is the basic block of cryptographic circuits, an ideal target for this technology. Results obtained are encouraging and can unlock interesting options for the future development of NML technology. [ABSTRACT FROM PUBLISHER]

In the post-CMOS scenario, field coupled nanotechnologies represent an innovative and interesting new direction for electronic nanocomputing. Among these technologies, nanomagnet logic (NML) makes it possible to finally embed logic and memory in the same device. To fully analyze the potential of NML circuits, design tools that mimic the CMOS design-flow should be used for circuit design. We present, in this paper, the latest and improved version of Torino Politecnico Nanotechnology (ToPoliNano), our design and simulation framework for field coupled nanotechnologies. ToPoliNano emulates the top-down design process of CMOS technology. Circuits are described with a VHSIC hardware description language netlist and layout is then automatically generated considering in-plane NML (iNML) technology. The resulting circuits can be simulated and performance can be analyzed. In this paper, we describe several enhancements to the tool itself, like a circuit editor for custom design of field coupled nanodevices, improved algorithms for netlist optimization and new algorithms for the place and route of iNML circuits. We have validated and analyzed the tool by using extensive metrics, both by using standard circuits and ISCAS’85 benchmarks. This contribution highlights the improvements of ToPoliNano, which is now a innovative and complete tool for the development of iNML technology. [ABSTRACT FROM AUTHOR]

NanoMagnet logic (NML) is among the emerging technologies that might replace CMOS in the next decades. According to its physical characteristics, to better exploit the potential of this technology—and of other similar ones—the use of parallel architectures with regular layout that avoid long interconnection signals is advised. Systolic arrays (SAs) are among these architectures, being composed of a grid of equal processing elements that are locally interconnected. However, they are usually implemented to execute only a small set of algorithms, and for this reason, throughout the years, they have not been an appealing solution for CMOS. To seriously analyze the potentials of NML, complex architectures must be conceived, and their physical implementation explored considering realistic technological constraints. With the increasing complexity of NML circuits, two issues, then, are noticed: 1) the need for a regular structure arises, that at the same time helps to reduce the intrinsic pipelining nature of NML and can be configured to be used for several applications without developing a dedicated design for each algorithm and 2) the capability to synthesize, place and route NML circuits is fundamental to demonstrate the feasibility of the architecture in two important conditions: efficiently managing the complexity of the design and sticking to the characteristics that are technologically feasible at the time of writing. In this paper, we address these issues presenting a new reconfigurable SA that can be programmed to execute different algorithms, and we provide two examples to show its working principle. Moreover, the array is synthesized and simulated with the aid of the first real tool for nanotechnology circuits that we have conceived, Torino Politecnico Nanotechnology tool. The joint contribution at both the architectural and physical design levels gives a relevant step forward to the state of the art in the demonstration of this emerging technology potential. [ABSTRACT FROM AUTHOR]

With the predicted end of CMOS scaling process, researchers started to study several alternative technologies. Among them NanoMagnet Logic (NML) offers advantages complementary to MOS transistors especially for its magnetic nature. Its intrinsic memory capability makes it suitable for zero stand-by power and logic-in-memory applications. NML requires a clock system that, if based on a magnetic field, highly increases the circuit dynamic power consumption. We have recently proposed a solution based on the magnetoelastic effect (ME-NML) [1] and on currently available fabrication processes, which drastically reduces dynamic power consumption. However, many questions still remain unanswered. Which kind of applications are best suited for this technology? How can we effectively design, analyze, and compare ME-NML circuits? Does it really offer advantages over state-of-the-art CMOS transistors? In this paper, we provide answers to all these questions and the results prove that this technology offers indeed extremely good performance. We have designed a Galois field multiplier with a systolic array structure to reduce interconnection overhead. We developed a new RTL model that allows us to easily describe and simulate circuits of any complexity, evaluating at the same time the performance and keeping into account technology constraints. We approach for the first time in the NML scenario the design of ME-NML circuits adopting the standard-cell method used in standard technologies and fulfill the design down to the physical level. The same circuit is designed also with NML technology based on magnetic fields and with a 28 nm low power CMOS bulk technology for comparison. The CMOS circuit is obtained through physical place&route with a commercial tool, providing, therefore, the most accurate comparison ever presented in literature. Power analysis shows that ME-NML circuits have a considerable advantage over both NML and state-of-the-art CMOS bulk technology. As a further by-product results clearly highlight which kind of architectures can better exploit the true potential of NML technology. [ABSTRACT FROM PUBLISHER]

Among emerging technologies nanomagnet logic (NML) has recently received particular attention. NML uses magnets as constitutive elements, and this leads to logic circuits where there is no need of an external power supply to maintain their logic state. As a consequence, a system with intrinsic memory and zero stand-by power consumption can be envisioned. Despite the interesting nature of NML, a fundamental open problem still calls for a solution that could really boost the NML technology: the clock system. It constrains the layout of circuits and leads to a potentially high dynamic power consumption if not carefully conceived. The first clock system developed was based on the generation of a magnetic field through an on-chip current. After that other types of NML, based on several different types of clock systems, were proposed to improve clocking. We present here our proposal for a new clock delivery method. We named this system “virtual clock.” It offers several important advantages over previous solutions. First, it notably simplifies the clock generation network, reducing the complexity of the fabrication process. It improves the efficiency of circuits layout, substantially reducing interconnections overhead and boosting the reliability of the majority voter. It enables the fabrication of in-plane NML circuits with two layers, while they were confined to one single layer up to now. Finally, it allows to globally reduce dynamic power consumption by considerably shrinking circuits area. Overall the “virtual clock” system that we propose represents an important step forward in the development of the NML technology. [ABSTRACT FROM PUBLISHER]

In the post-CMOS scenario a primary role is played by the quantum-dot cellular automata (QCA) technology. Irrespective of the specific implementation principle (e.g., either molecular, or magnetic or semiconductive in the current scenario) the intrinsic deep-level pipelined behavior is the dominant issue. It has important consequences on circuit design and performance, especially in the presence of feedbacks in sequential circuits. Though partially already addressed in literature, these consequences still must be fully understood and solutions thoroughly approached to allow this technology any further advancement. This paper conducts an exhaustive analysis of the effects and the consequences derived by the presence of loops in QCA circuits. For each problem arisen, a solution is presented. The analysis is performed using as a test architecture, a complex systolic array circuit for biosequences analysis (Smith-Waterman algorithm), which represents one of the most promising application for QCA technology. The circuit is based on nanomagnetic logic as QCA implementation, is designed down to the layout level considering technological constraints and experimentally validated structures, counts up to approximately 2.3 milion nanomagnets, and is described and simulated with HDL language using as a testbench realistic protein alignment sequences. The results here presented constitute a fundamental advancement in the emerging technologies field since: 1) they are based on a quantitative approach relying on a realistic and complex circuit involving a large variety of QCA blocks; 2) they strictly are reckoned starting from current technological limits without relying on unrealistic assumptions; 3) they provide general rules to design complex sequential circuits with intrinsically pipelined technologies, like QCA; and 4) they prove with a real application benchmark how to maximize the circuits performance. [ABSTRACT FROM PUBLISHER]

In past years the most common way to improve computers performance was to increase the clock frequency. In recent years this approach suffered the limits of technology scaling, therefore computers architectures are shifting toward the direction of parallel computing to further improve circuits performance. Not only GPU based architectures are spreading in consideration, but also Systolic Arrays are particularly suited for certain classes of algorithms. An important point in favor of Systolic Arrays is that, due to the regularity of their circuit layout, they are appealing when applied to many emerging and very promising technologies, like Quantum-dot Cellular Automata and nanoarrays based on Silicon NanoWire or on Carbon nanotube Field Effect Transistors. In this work we present a systematic method to improve Systolic Arrays performance exploiting Pipelining and Input Data Interleaving. We tackle the problem from a theoretical point of view first, and then we apply it to both CMOS technology and emerging technologies. On CMOS we demonstrate that it is possible to vastly improve the overall throughput of the circuit. By applying this technique to emerging technologies we show that it is possible to overcome some of their limitations greatly improving the throughput, making a considerable step forward toward the post-CMOS era. [ABSTRACT FROM AUTHOR]

Protein comparison is gaining importance year after year since it has been demonstrated that biologists can find correlation between different species, or genetic mutations that can lead to cancer and genetic diseases. Protein sequence alignment is the most computational intensive task when performing protein comparison. To speed-up alignment, dedicated processors that can perform different computations in parallel have been designed. Among them, the best performance has been achieved using systolic arrays (SAs). However, when the processing elements of the SA have an internal loop, performance could be highly reduced. In this paper, we present an architectural strategy to address this problem applying pipeline interleaving; this strategy is applied to an SA for Smith Waterman algorithm that we designed. Results encourage the adoption of pipeline interleaving for parallel circuits with loop-based processing elements. We demonstrate that important benefits in terms of higher operating frequency can be derived without so relevant costs as increased complexity, area, and power required. [ABSTRACT FROM PUBLISHER]

Reconfigurable embedded systems can take advantage of programmable devices, such as microprocessors and field-programmable gate arrays (FPGAs), to achieve high performance and flexibility. Support to flexibility often comes at the expense of large amounts of nonvolatile memories. Unfortunately, nonvolatile memories, such as multilevel-cell (MLC) NAND flash, exhibit a high raw bit error rate that is mitigated by employing different techniques, including error correcting codes. Recent results show that low-density-parity-check (LDPC) codes are good candidates to improve the reliability of MLC NAND flash memories especially when page size increases. This letter proposes to use a joint source/channel approach, based on a modified arithmetic code and LDPC codes, to achieve both data compression and improved system reliability. The proposed technique is then applied to the configuration data of FPGAs and experimental results show the superior performance of the proposed system with respect to state of the art. Indeed, the proposed system can achieve bit-error-rates as low as about 10^ - 8 for cell-to-cell coupling strength factors well higher than 1.0. [ABSTRACT FROM PUBLISHER]

In recent years, magnetic-based technologies, like nanomagnet logic (NML), are gaining increasing interest as possible substitutes of CMOS transistors. The possibility to mix logic and memory in the same device, coupled with a potential low power consumption, opens up completely new ways of developing circuits. The major issue of this technology is the necessity to use an external magnetic field as clock signal to drive the information through the circuit. The power losses due to the magnetic field generation potentially wipe out any advantages of NML. To solve this problem, new clock mechanisms were developed, based on spin transfer torque current and on voltage-controlled multiferroic structures that use magnetoelastic properties of magnetic materials, i.e., exploiting the possibility of influencing magnetization dynamics by means of the elastic tensor. In particular, the latter shows an extremely low power consumption. In this paper, we propose an innovative voltage-controlled magnetoelastic clock system aware of the technological constraints risen by modern fabrication processes. We show how circuits can be fabricated taking into account technological limitations, and we evaluate the performance of the proposed system. Results show that the proposed solution promises remarkable improvements over other NML approaches, even though state-of-the-art ideal multiferroic logic has in theory better performance. Moreover, since the proposed approach is technology-friendly, it gives a substantial contribution toward the fabrication of a full magnetic circuit and represents an optimal tradeoff between performance and feasibility. [ABSTRACT FROM PUBLISHER]

In this brief, we propose local automatic rate adjustment in network-on-chips (NoC) (LAURA-NoC), a NoC with a distributed approach to dynamic voltage and frequency scaling (DVFS). The utilization of the switch buffers is used in a local feedback loop to automatically determine the appropriate clock frequency and voltage that allow the switch to sustain the rate at its input ports, without a global controller. The DVFS controller is simple and uses 2 voltage and 16 frequency values. We report a significant power saving compared to a global DVFS approach in a 45-nm CMOS technology, 33\% on average over four realistic video applications. [ABSTRACT FROM AUTHOR]

The interest in emerging nanotechnologies has been recently focused on nanomagnetic logic (NML), which has unique appealing features. NML circuits have very low power consumption and, because of their magnetic nature, maintain the information safely stored even without power supply. The nature of these circuits is much different from that of CMOS circuits. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics; and 3) modeling performance aspects such as speed and power, together with logic behavior. In this paper, we present a very-high-speed integrated circuits HDL (VHDL) behavioral model for NML circuits, which allows the evaluation of not only the logic behavior but also its power dissipation. It is based on a technological solution called “snake-clock.” We demonstrate this model using a case study which offers the right variety of internal substructures to test the method: a 4-bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area, and power dissipation, which we evaluate using a benchmark division algorithm. The results highlight the flexibility and the efficiency of this model, as well as the remarkable improvements that it brings to the analysis of NML circuits. [ABSTRACT FROM PUBLISHER]

The recently proposed Nanomagnet-based logic (NML) represents an innovative way to assemble electronic logic circuits. The low power consumption, combined with the possibility of maintaining the information stored without power supply, allows us to design low power digital circuits far beyond the limitations of CMOS technology. This paper is focused on the key logic block of NML, the majority voter (MV). It is thoroughly analyzed through detailed micromagnetic simulations, changing the geometrical parameters, and detecting logic behavior, timing performance, and energy dissipation. Our analysis enables us to derive important results, substantially enhancing the practical knowledge of NML. First, we demonstrate that NML circuits can be effectively fabricated not only using electron beam lithography, but also using high-end optical lithography without loosing performance. This is a promising opportunity for the future of this technology. Second, we demonstrate the robustness of the MV considering process variations and extracting useful guidelines for its technological implementation. Third, we show how, and how much, the alteration of magnets sizes and distances affect timing and energy consumption. Finally, fourth, we outline the problematic fabrication of the gate with real clock wires, and propose a modification that enables the fabrication of working gates, remarkably enhancing the possibilities of this technology. [ABSTRACT FROM PUBLISHER]

The International Technology Roadmap of semiconductors suggests that quantum-dot cellular automata (QCA) technology might be a possible CMOS substitute. In particular, magnetic quantum-dot cellular automata (MQCA) have recently drawn the attention of the researchers. Previous experimental works have demonstrated that MQCA are feasible, and can be fabricated with existing technological processes. They are also attractive due to their compactness and an extremely small power dissipation. Unlike in previous contributions, where architectural blocks are often presented without or only slightly considering their relations with technology, here we conceived, implemented, and described a complex MQCA computational block maintaining a clear link with technology. This link is achieved at different levels. At an architectural level, we propose the use of delay insensitive null convention logic (NCL) refid="ref1"/. It is implemented for MQCA in order to solve the “layout=timing” problem in the specific case of MQCA. We, thus, describe an architectural block at system level using a hardware description language (HDL). This NCL-HDL idea is adapted to a new structure, which we have called “snake clock,” proposed as a feasible solution for the problem of clock delivery, essential for MQCA operations. Furthermore, we demonstrated by means of accurate micromagnetic and finite element method simulations that the three-phase “snake-clock” NCL structure works correctly. [ABSTRACT FROM PUBLISHER]

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processor. [ABSTRACT FROM AUTHOR]

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper. [ABSTRACT FROM AUTHOR]

Proposes the use of turbo codes for several applications in including the development of wireless systems. Requirement of transmissions at very low signal-to-noise ratios; Problem of extracting the best coding gains; Iterative nature of the decoding process.

Editor's note:Emerging computing technologies inherently exhibit high process and timing variation. Many researchers believe that an asynchronous approach is likely to play an enabling role in making these technologies feasible. This article compares the cost and performance of fully synchronous and mixed synchronous-asynchronous implementations of quantum cellular automata, and makes the case that asynchrony is inevitable at the top levels of QCA designs.—Montek Singh, UNC Chapel Hill [ABSTRACT FROM PUBLISHER]