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A fast-settling phase-locked loop (PLL) adopting the cycle-slipping-elimination phase frequency detector and charge pump (CSE-PFDCP) is presented. The CSE-PFDCP solves the cycle-slipping problem in a conventional non-linear PFDCP (NL-PFDCP), which accelerates the settling speed of the PLL. In addition, the metastability problem of the proposed cycle-slipping-elimination technology is analyzed in this brief. The proposed fast-settling PLL is fabricated in a 180 nm CMOS process with core area of 0.38 mm2. The frequency range of the PLL prototype is 2.1-2.6 GHz. Using the proposed CSE-PFDCP, the settling time is less than 6 $\mu \text{s}$ when the PLL frequency jump is 480 MHz, and the PLL settling speed is increased by 171%. [ABSTRACT FROM AUTHOR]

Temperature-dependent dc and dynamic characteristics of p-GaN gate HEMT were thoroughly investigated from 300 to 140 K. At low temperature, in addition to barely shifted threshold voltage, substantial improvement in drain current was observed. At 300 K both positive and negative gate bias stressing were applied to the device in order to form a complete mapping of threshold voltage instability of p-GaN gate HEMT. Three mechanisms, namely hole trap emission, carrier out-spilling, and hole accumulation have been employed to elucidate the trends of threshold voltage shift at room temperature. Temperature-dependent dynamic performances, including threshold voltage instability and drain current degradation, were investigated. Via drain current transient spectroscopy, activation energy for hole emission and trapping process were extracted as 132 and 70 meV, respectively. Detailed pulsed output characteristics at various quiescent biases were explored. At 300 K, gate quiescent bias played a dominant role in determining current collapse compared with drain quiescent bias. Moreover, current collapse caused by gate pulse stressing was much mitigated with decrease of temperature. The detailed temperature-reliant dynamic performance provides valuable information for justifying feasibility of p-GaN gate HEMT for low-temperature applications and further device optimizations. [ABSTRACT FROM AUTHOR]

Mechanisms of trap effects are crucial to improving diamond-based transistor electrical performance. Here, the trap effects in hydrogen-terminated diamond metal–oxide–semiconductor field-effect transistors (HD MOSFETs) are investigated by separating the effects of gate dielectric bulk alumina (BA) and diamond substrate (DS) for the first time. First, the location of traps and their impact on the dynamic drain current are characterized by pulsed ${I}$ – ${V}$ characterization. The dynamic drain current is degraded by traps in both BA and DS. Furthermore, the quiescent-bias-point-dependent trapping effects are studied by different quiescent bias points to reveal the response intensity of these two kinds of traps. Second, to further respectively characterize the effects of traps in the BA and the DS on HD MOSFETs, the threshold voltage (${V}_{\text {th}}$) instability was characterized under negative gate bias stress (NGBS) conditions. Strong gate biases ranging from −4 to −8 V are selected to activate traps in DS. An extraordinary nonmonotonic change in ${V}_{\text {th}}$ is found under the −8 V NGBS condition. Moreover, the corresponding variation in ${V}_{\text {th}}$ is, unexpectedly, smaller than −4 and −6 V NGBS conditions. These phenomena indicate that the detrapping effect in the DS become dominant with increasing stress duration in the variation in ${V}_{\text {th}}$ under an NGBS of −8 V. Finally, based on these results, an improved kinetic model is proposed to separately describe the effects of traps in the BA and the DS. These results are useful for improving the performance of HD MOSFETs. [ABSTRACT FROM AUTHOR]

A 12-GHz transformer feedback Class-F2,3 voltage-controlled oscillator (VCO) using noise circulating is proposed in this letter. Transformer feedback is utilized in the proposed VCO to achieve Class-F2,3 resonant impedance control at the VCO output and tail current transistor input. Also, the noise contribution of the tail current transistor is further reduced by partially circulating its noise into itself. The proposed VCO is fabricated in 40-nm CMOS process with 0.04-mm2 core area. Experimental results show that the frequency tuning range of the VCO is 11.74–12.63 GHz. The VCO achieves phase noise of −120.2 dBc/Hz at 1-MHz offset frequency at 12 GHz with figure of merit (FoM) of 190.5 dBc/Hz and FoM $_{T}$ of 187.8 dBc/Hz, and consumes 13.23 mW from a 1.1-V supply. [ABSTRACT FROM AUTHOR]

In this article, the hydrogen-terminated diamond metal-oxide-semiconductor field effect transistors (MOSFETs) which can operate at high frequency of 10 GHz are demonstrated. The devices were fabricated with a 50 nm Al2O3 gate insulator and a 350 nm Si3N4 passivation layer, which is compatible with the process of monolithic microwave-integrated circuits (MMICs). The device with gate length of 0.35 $\mu \text{m}$ shows a high drain current density of −561 mA/mm. The RF small signal characteristics and power output performances at 10 GHz for the devices with different gate widths have been investigated. With the gate width increased from 100 to 200 $\mu \text{m}$ , the extrinsic maximum frequency of oscillation ${f} _{\text {max}}$ is slightly decreased from 23 to 21 GHz, whereas the output power density at 10 GHz is improved from 1.05 to 1.26 W/mm, with associated power added efficiency increased from less than 5% to 20.77%. Comparing with the devices fabricated by the self-aligned gate process, the power output performance is significantly improved, indicating it is a promising method to fabricate high power and high frequency diamond MOSFETs by using the thick Si3N4 passivation technique. [ABSTRACT FROM AUTHOR]

We propose a self-biased inverter-based amplifier for realizing a high-speed low-power second-order single-loop continuous-time bandpass delta-sigma modulator (CT-BP-ΔΣM). The design is amenable to nanoscale CMOS and exploits a single self-biased pseudo-differential inverter with a positive feedback to replace conventional op-amps used in an integrator configuration. The modulator also uses a 5-bit asynchronous successive approximation register (ASAR) quantizer. With a 30 MHz bandwidth at 400 MS/s sampling rate and 100 MHz intermediate frequency (IF), the modulator achieves 61 dB dynamic range (DR) and 58 dB SNDR while consuming 2.5 mW from a 1V supply. The core area in 28 nm LP CMOS is 0.04 mm2. A 38.6 fJ/conv.-step figure of merit is achieved. [ABSTRACT FROM AUTHOR]

In this article, we report a study on the dc and RF linearity performances of a hydrogen-terminated (C-H) diamond field-effect transistor. An atomic-layer-deposited Al2O3 (ALD-Al2O3) based C-H diamond (100) MOSFET was fabricated and then characterized by dc- $I-V$ , $C-V$ , small-signal, large-signal, pulsed $I-V$ , and two-tone inter-modulation characteristics. The typical transfer results suggest that the presented device achieves a maximum transconductance $(g_{m-\max}) \times$ gate-voltage swing (GVS) product of 673.2 $\text{V}\cdot $ mS/mm, which is a record value among single-crystal diamond FETs to the best of our knowledge. The improved ${g}_{m}$ -linearity in this work can be attributed to the enhanced mobility performance, and the extracted effective mobility ($\mu _{{\mathrm {eff}}}$) varies from 105 to 200 cm2/ $\text{V}\cdot \text{s}$. Furthermore, theoretical calculations reveal that the obtained high-performance $\mu _{{\mathrm {eff}}}$ is mainly due to the low-density surface charged impurities (${ \approx } 3.7\times 10^{12}$ cm−2) and the alleviated surface roughness scattering. Small-signal RF measurement shows that the drain current swing (DCS) of ${f}_{T}$ is as high as −434 mA/mm. Unexpectedly, the RF output power performance at 2.6 GHz suffers from the severe drain current compression under the RF input drive. The subsequent pulsed ${I}$ – ${V}$ results reveal that the cause could be ascribed to the drain-lag trapping effect. Even so, the device still shows attractive IM3-to-Carrier ratio (-C/IM3) values in the linear region, which indicates that the diamond MOSFET is a prospective candidate for the RF linearity application. [ABSTRACT FROM AUTHOR]

A novel structure of inverted electric-field decoupling (IED) to suppress the lateral crosstalk in monolithic gallium nitride (GaN) devices is proposed in this article. The IED structure features a Schottky metal in the trench between high-voltage power and low-voltage logic GaN devices, which is lined with nitride passivation and electrically connected with an on-chip integrated negative voltage supply (V−). The IED structure forms the inverted electric fields (e-fields) against the power device exerted ones, which can reduce the local e-fields at logic devices, decouple the monolithic devices, and suppress the lateral crosstalk. The calibrated TCAD simulation has been carried out for 100- and 650-V rating monolithic GaN devices with IED structure. During the blocking state of power device, the crosstalk current can be suppressed to negligible percentages over the current of power device by V− < −5 V, while in switching operations, both the crosstalk current and gate voltage in the logic device can be effectively suppressed. Possible false turn-on can be eliminated when V− < 0 V for 100-V rating and V− < −20 V for 650-V rating. The IED structure demonstrates high feasibility with a large process window. The proposed IED structure is promising for solving the crosstalk problems in high-frequency and highly integrated monolithic GaN devices and integrated circuits (ICs) for power conversion applications. [ABSTRACT FROM AUTHOR]

To reduce the Nd–Fe–B material cost and balance the utilization of rare earth sources, the misch metal (MM) substitution for Nd in the sintered magnet attracts interest. Under the processing of fabricating Nd–Fe–B magnet, hydrogen decrepitation (HD) is widely used to obtain magnetic powder; however, the HD behaviors of RE–Fe–B strips based on MM may be complex. The HD behaviors of the [(Pr, Nd)1–xMMx]30.8FebalCo1.4 B0.97 ($x $ = 0–1) strips were studied under 0.2 MPa pressure. We find that it is similar to the Nd–Fe–B, 2:14:1 tetragonal structure of RE–Fe–B strips based on MM which is not broken during hydrogen decrepitating. But the REFe2 phase in MM30.8FebalCo1.4B0.97 disappears dramatically as a result of hydrogenation. For the samples with MM, the HD process is quicker and the particle size gets smaller than that for free MM, especially for samples with 35 wt.% MM, which may be attributed to La and Ce elements. [ABSTRACT FROM AUTHOR]

This presents a novel fractional local oscillator (LO) divider with an area-efficient calibration scheme to mitigate oscillator pulling effects in transmitter (TX) by offsetting the LO and TX operating frequency. The multi-modulus division ratio is achieved by combining multiphase divide-by- ${N}$ signals from ${N}$ -stage ring counters. However, the delay mismatches due to layout or device mismatches among multiphase signal paths result in fractional spurs. By introducing the successive approximation detection (SAD) calibration scheme, the divider achieves real-time division ratio variance inexpensively without deteriorating the LO performance. A prototype is verified in the 65 nm CMOS process. Simulation results show that the entire system can provide LO signals for 4G/5G wireless communication systems. After calibration, fractional spurs are reduced from −37.67dBc to −57.93dBc at a typical output frequency of 2GHz. [ABSTRACT FROM AUTHOR]

This brief presents a high-linear current-reuse up-conversion mixer with built-in-self-calibration for LO feed through (LOFT) and I/Q imbalance for the 2.4GHz ISM band transmitter. Exploiting the negative feedback loop and the saturated switches biased by the current bleeding, third-order intermodulation (IM3) products are eliminated. Based on the fully differential push-pull OP-AMP and current mirror, the current-reuse input transconductance with a boosted gain is achieved. LOFT and I/Q imbalance calibrations are carried out utilizing two fully-integrated auto-calibration loops with the auto-zero comparator and the low noise envelope detector, respectively. Fabricated in 40 nm LP CMOS technology, the mixer shows 15.02 dBm OIP3 and −1.80 dBm ${OP}_{1dB}$ while consuming 12.75 mW from 1.1 V power supply for 4.17 dB gain. Along with the third-order filter, the up-conversion mixer achieves >40 dBc LO suppression ration (LSR) and 50.6 dBc image rejection ration (IMRR) within ±2 dB deviation among 10 MHz bandwidth, thanks to the two calibration loops. [ABSTRACT FROM AUTHOR]

This brief presents a low noise, high dynamic range (DR), high linearity, and high selectivity analog baseband (BB) for multi-standard TV applications. A customized sixth-order low pass filter with two additional zeroes Chebyshev-I filter is adopted to enhance the average adjacent channel rejection (ACR) and the attenuation at 5.25 MHz, and a novel programmable gain amplifier (PGA) realizes accurate gains with a fine-tuning gain step of 0.25 dB. The digitally assisted real-time dc offset cancellation (DCOC) loop can prevent the BB chain from saturation robustly with a low residual output dc offset voltage (DCOV) and an extremely low cut-off frequency. The digitally assisted complementary cumulative distribution function (CCDF)-based on-chip automatic gain control (AGC) loop implements reliable amplitude control for digital TV signals with a large peak to average power ratio (PAPR). The BB chain fabricated in a 0.18 ${\mu }\text{m}$ CMOS process occupies an area of 1.2 mm2 and consumes a current of 21.3 mA from 1.8-V supply including the output buffer. It achieves a maximum gain of 62 dB and a DR of 68 dB with 0.25 dB minimum step. The attenuation at 5.25 MHz is 48.6 dB and the average ACR is 38.2 dB. The measured equivalent input-referred noise voltage is 22 ${\mathrm{ nV/}}\sqrt {\mathrm{ Hz}} $ , out-of-band IIP3 of 37.61 dBV, and out-of-band IIP2 of 77.19 dBV at 56 dB gain. The residual output DCOV is less than 5 mV and the minimum 3 dB cut-off frequency is 100 Hz when BB operates in the maximum gain of 62 dB. [ABSTRACT FROM AUTHOR]

This brief presents a fully integrated dc offset cancellation (DCOC) scheme with configurable cut-off frequency and settling time. The proposed digitally assisted real-time DCOC scheme prevents the high gain baseband circuitry from saturation in direct conversion receivers. The proposed DCOC is designed and implemented in a $0.18~\mu \text{m}$ CMOS process. It occupies an area of 0.042 mm2 and consumes a current of 0.58 mA for I and Q paths under 1.8 V supply. The residual output dc offset voltage (DCOV) is less than 5 mV under the maximum baseband gain of 62 dB. The 3-dB high-pass cut-off frequency can be configured from 100 Hz to 1 kHz and settling time varying from 5.7 ms to 0.7 ms when the receiver operates under the maximum baseband gain. [ABSTRACT FROM AUTHOR]

In this paper, carrier transport and gain mechanisms are exploited in the $\beta $ -Ga2O3-based metal–semiconductor–metal photodetectors with Au back-to-back Schottky contacts. The resultant devices exhibit a low dark current of <10 pA at 10 V, a sustaining bias over 500 V without electric breakdown, a self-powered sensitivity with a UVC-to-visible rejection ratio over $10^{{3}}$ , and a photo-to-dark current ratio of 50 at 473 K, indicative of its strong operation capability at high temperature and in harsh environments. Temperature-dependent current–voltage features reveal that the dark reverse leakage is dominated by the thermionic field emission at low electric field and Poole–Frenkel emission from a deep trap level of 0.42 eV under the conduction band at high field, respectively. These negatively charged traps positioned below the Fermi level in the vicinity of Schottky interface capture photogenerated holes and reduce the barrier height upon illumination. The temperature- and bias-dependent photoresponse features are identified in physics that the photoconductive gain as well as slow response speed is originated from the change of barrier height due to trap repopulation. [ABSTRACT FROM AUTHOR]