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As the semiconductor manufacturing process is moving towards the 3 nm node, there is a crucial need to reduce the edge placement error (EPE) to ensure proper functioning of the integrated circuit (IC) devices. EPE is the most important metric that quantify the fidelity of fabricated patterns in multi-patterning processes, and it is the combination of overlay errors and critical dimension (CD) errors. Recent advances in machine learning have enabled many new possibilities to improve the performance and efficiency of EPE optimization techniques. In this paper, we conducted a survey of recent research work that applied machine learning/ deep learning techniques for the purposes of enhancing virtual overlay metrology, reducing overlay error, and improving mask optimization methods for EPE reduction. Thorough discussions about the objectives, datasets, input features, models, key findings, and limitations are provided. In general, the results of the review work show a great potential of machine learning techniques in aiding the improvement of EPE in the field of semiconductor manufacturing. [ABSTRACT FROM AUTHOR]

Here, we review the most recent developments in the field of 2-D electronics. We focus first on the synthesis of 2-D materials, discussing the different growth techniques currently available and assessing their strengths and weaknesses. Moreover, we describe a possible roadmap to enable CMOS compatible integration of 2-D materials. We then shift our attention to 2-D devices and circuits and review the state of the art. Among the plethora of device concepts, we look closely at 2-D tunnel FETs (TFETs) and negative-capacitance FETs (NC-FETs) for low-power applications. We also put a particular emphasis on doping-free polarity-controllable systems that use electrostatic doping to eliminate the need for physical or chemical doping. We conclude with an analysis of simulations of scaled devices and discuss the possibilities enabled at circuit level by 2-D electronics. [ABSTRACT FROM AUTHOR]

2-D material FETs hold the promise of excellent gate control, but the impact of nonidealities on their performance remains poorly understood. This is because of the need, so far, to use computationally intensive nonequilibrium Green’s function (NEGF) simulations. Here, we therefore use a semiclassical model to investigate the role of nonidealities in the scaling of back-gated (BG) and top-gated (TG) monolayer MoS2 FETs. We verify the electrostatics and transport of the semiclassical model with density functional theory-based NEGF simulations and calibrate nonidealities, such as interface traps (${D}_{\textsf {it}}$) and Schottky contact barrier height ($\phi _{\textsf {SB}}$) to experimental monolayer and bilayer MoS2 FETs. We find that among the nonidealities, ${D}_{\textsf {it}}$ has the strongest subthreshold swing impact with 70 mV/dec obtainable in BG devices for a ${D}_{\textsf {it}}$ of $5\times {10}^{11}$ cm−2eV $^{-1}$ , an equivalent oxide thickness (EOT) of 1 nm, and a channel length (${L}_{\textsf {ch}}$) of 5 nm. For scaled EOT, $\phi _{\textsf {SB}}$ only strongly impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ for the TG case, as the overlapping gate thins the Schottky barriers in the BG case. We show in TG devices that a spacer of only 5 nm results in a 1000-fold drop in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ because of the nonidealities. We propose positive spacer oxide charge as a solution and show that a charge density of above 1013 cm−2 is required to fully recover the device performance. [ABSTRACT FROM AUTHOR]

The effects of oxidants both in the channel and contact regions of MoS2 transistors are discussed through a systematic experimental study. This letter highlights the issues of partial instability in metal-organic chemical vapor deposition MoS2 and proposes a procedure, which considerably improves the electrical characteristics of back-gated transistors. By avoiding ambient exposure and layer oxidation, contact resistance can be reduced and intrinsic mobility increased by 50%. [ABSTRACT FROM AUTHOR]

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection. [ABSTRACT FROM AUTHOR]

Positive charges (PCs) in gate dielectric shift the threshold voltage and cause a time-dependent device variability. To assess their impact on circuits, it is useful to know their distribution for a wide energy range both within and beyond silicon bandgap. Such a distribution is still missing, and a technique for its extraction has not been demonstrated yet. The central objective of this paper is, for the first time, to develop a new fast technique and to demonstrate its capability for probing the energy distribution of PCs over such a wide energy range. Results show that PCs can vary significantly with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps that are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence-band edge are from created defects. The PCs within the bandgap have a peak near Ev + 0.8 eV and saturate for either longer stress time or higher stress temperature. In contrast, the PCs above a conduction band edge, namely the antineutralization positive charges, do not saturate, and their generation is clearly thermally accelerated. [ABSTRACT FROM AUTHOR]

Defects in gate oxide cause breakdown and shorten device lifetime. Early works mainly focused on generation process that converts a precursor into a charged defect. Although it can be neutralized through “recovery,” the defect is still there and will recharge when resuming stress. Recently, we have shown that this is not always the case and some defects can be lost, but a detailed investigation is missing. The central objective of this work is to accurately define and extract the loss, separate it from slowdown, and evaluate their enhancement of device lifetime. Loss is defined as elimination of defects, while slowdown means that recharging a “hardened” precursor takes longer than charging a fresh one. Clear evidences show that losses originate from permanent components, i.e., generated interface states and antineutralization positive charges, while slowdown occurs to both permanent and recoverable components. Loss is thermally accelerated, but slowdown of recoverable component is not. This improved understanding adds slowdown and losses to the existing framework for defects. For the first time, we report that the losses and slowdown enhance device lifetime by a factor of 2.6–4.3, for an allowed threshold voltage shift of 20–45 mV. [ABSTRACT FROM AUTHOR]

Interface states play an important role in the performance of MOSFETs, and previous works only addressed the states within band gap. The implicit assumption is that the states beyond band gap (SBBs) are negligible, but there is no experimental evidence supporting it. Because of a lack of techniques for characterizing SBBs, there is hardly any information available. The central objective of this paper is to develop a technique for evaluating SBBs and to show the impact of SBBs on mobility evaluation. For the first time, the pulse capacitance–voltage has been used to extract SBBs quantitatively. It is found that SBBs can reach the order of \10^13 \ \cm^-2\cdot\eV^-1 beyond both conduction- and valence-band edges on a fresh MOSFET. The conventional split C– V technique ignores the SBBs, and this can lead to an underestimation of carrier mobility over 30%. Using the newly developed technique as a tool, the impact of nitridation of Hf-based dielectric stacks on carrier mobility is assessed. As nitrogen density increases, the apparent reduction of carrier mobility observed by early works originates from the higher SBBs. Once SBBs are taken into account, nitridation does not degrade carrier mobility. The SBBs are sensitive to process conditions, and this paper opens the way for their minimization. [ABSTRACT FROM AUTHOR]

Characterizing interface states is a key task, and it typically takes seconds when conventional techniques, such as charge pumping (CP), are used. The stress-induced degradation can recover substantially during this time, and there is a need to improve the measurement speed. The central task of this work is to reduce the measurement time for interface states from seconds to microseconds to minimize the recovery. A fast single pulse CP (SPCP) technique is developed. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained, and their saturation level is used to evaluate interface states. Unlike the conventional CP (CCP) method, the contribution of currents during the plateaus of gate pulse is excluded for SPCP, making it less vulnerable to the interferences of gate leakage and defects within dielectrics. For the first time, the SPCP allows the recovery of interface states being monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100 \mu\s, which would be missed if the CCP were used. [ABSTRACT FROM PUBLISHER]

As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the current of MOSFETs. However, no solution has been reported to boost the on-current of the all-silicon p-TFET, a necessity for making an inverter and competing with the MOSFET. We have investigated the heterostructure TFET with respect to complementarity based on our semianalytical model, and we propose the In~Ga1~As-source silicon-TFET as p-TFET. This design is partitularly applicable to nanowire-based transistor architectures. We discuss the complementarity of the I-V curves, and we analyze the threshold voltage behavior of the complementary TFETs. [ABSTRACT FROM AUTHOR]

Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The loca- tion of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive charging. The results clearly show that positive charges are dominated by the interfacial layer (IL) and that they do not pile up at the HfSiONIIL interface. The results support the assumption that positive charges are located close to the IL/substrate interface. Unlike electron trapping that reduces rapidly for thinner Hf dielectric layer, posi. tive charges cannot be reduced by using a thinner HfSiON film. Index Ternzs-Hf silicates, high-k gate dielectric, instability, negative bias temperature instability (NBTI), positive charges, reliability, spatial distribution. [ABSTRACT FROM AUTHOR]

This paper shows important improvements in charge pumping (CP) measurements on stacked high-k dielectrics, where the defects in high-k and SiO2 can be distinguished and estimated. The spatial profile of the interface traps and bulk traps is obtained by plotting the trap density as a function of the discharge time. Furthermore, the spectroscopic character of the base-level CP technique is demonstrated in HfSiON/SiO2 gate dielectrics by changing the applied pulse bias. It is found that when large pulse amplitude is applied to the gate, two bands appear superimposed on top of the usual base-level CP curve, suggesting the presence of two separate defect energy levels in the high-k dielectric. [ABSTRACT FROM AUTHOR]

Combinatorial methodology enables the generation of comprehensive and consistent data sets, compared with the "one-composition-at-a-time" approach. We demonstrate, for the first time, the combinatorial methodology applied to the work function (Φm) extraction for Ta1-xAlxNy alloys as metal gates on HfO2, for complementary metal-oxide-semiconductor applications, by automated measurement of over 2000 capacitor devices. Scanning X-ray microdiffraction indicates that a solid solution exists for the Ta1-xAlxNy libraries for 0.05 ≤ x ≤ 0.50. The equivalent oxide thickness maps offer a snapshot of gate stack thermal stability, which show that Ta1-xAlxNy alloys are stable up to 950 °C. The Φm of the Ta1-xAlxNy libraries can be tuned as a function of gate metal composition over a wide (0.05 ≤ x ≤ 0.50) composition range, as well as by annealing. We suggest that Ta0.9Al0.1N1.24 gate metal electrodes may be useful for p-channel metal-oxide-semiconductor applications. [ABSTRACT FROM AUTHOR]

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability ΔVth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates ΔVth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of ΔVth is clarified. [ABSTRACT FROM AUTHOR]

A pFET threshold-voltage (Vt) reduction of about 200 mV is demonstrated by inserting a thin Al2O3 layer between the high-K dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiOx capped with 9 Å of Al2O3 obtains a low long-channel Vt of —0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm2 ⁄V · s at 0.8 MV/cm (92% of universal value), a negligible equivalent. oxide-thickness (EOT) increase of 0.1 Å (compared to the uncapped reference), and a low Vt instability of 4.8 mV at 7 MV/cm. It also passes the ten-year negative-bias-temperature-instability (NBTI) lifetime specification with a gate overdrive of —0.7 V. This indicates that Al2O3 caps are beneficial to the pFET applications. In contrast, nitrogen incorporation in the Al2O3-capped HfSiOx is not favorable because it increases the Vt by 50—140 mV, degrades the mobility by 10%-22%, increases the EOT by 0.5—0.8 Å and the Vt instability by 5–13 mV, and reduces the NBTI lifetime by four to five orders of magnitude. Compared to postcap nitridation, posthigh-k nitridation results in more severe degradation of these properties by incorporating nitrogen closer to the Si/SiO2 interface. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) with HfCl4 as a precursor is widely used for HfO2 fabrication. Due to the nature of the precursor under study, i.e., HfCl4 and H2O, the presence of chlorine residues in the film due to insufficient hydrolysis is eminent. Obviously, the chlorine residue in the HfO2 film is suspected to affect the quality of the HfO2 film. In this paper, we reduced the concentration of chlorine residues by increasing the H2O oxidant pulse time in between the deposition cycles from 0.3 to 10 and 90s. Time-of-flight secondary ion mass spectrometry analysis shows that this decreases the chlorine concentration in the HfO2 film by more than one order of magnitude. However, time-dependent dielectric breakdown analysis shows that the lifetime remains quasi unaffected (within identical error bars) for the different injection cycles. Charge pumping analysis was done by varying both pulse frequency and amplitude to investigate the creation of defects, but negligible differences were observed. Therefore, we conclude that the presence of chlorine residues has no significant impact on the trap generation and reliability of ALD HfO2 layers, and this result corresponded with the mobility result. The experimental picture is confirmed with first-principle calculations that show that the presence of chlorine residues does not induce defect levels in the bandgap of HfO2. [ABSTRACT FROM AUTHOR]

The effects of source/drain activation thermal bud- get and premetallization degas conditions on interfacial re- growth, carrier mobility, and defect densities are examined for SiO2/HfO2/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-κ bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 °C spike for t = 1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 °C for t = 60 s). For 1000 °C spike-annealed films, where the highest SiO2/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO2 and the IL which increases for high-temperature processing. [ABSTRACT FROM AUTHOR]

In this paper, an effective technique and methodology for the estimation of fixed charge components in high-k stacks was demonstrated by varying both the SiO2 and high-k dielectric thicknesses. The SiO2 thickness was scaled on a single wafer by uniformly changing the etch time of a thermally grown SiO2 layer across the wafer. This minimized wafer-to-wafer variations and enables acquisition of statistically significant datasets. Layers with different thickness of both the nitrided and non-nitrided hafnium-silicate layers were then grown on these wafers to estimate all the interfacial and bulk charge components. The reproducibility and validity of this technique were demonstrated, and this method was used to compare the fixed charge levels in Hf-silicates (HfSiO) and nitrided-Hf-silicate (HfSiON) layers. [ABSTRACT FROM AUTHOR]

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Å, a leakage current of 1.5 A/cm² at VG = 1 V, a peak mobility of 190 cm²/V · s, and a drive-current of 815 μA/μm at an OFF-state current of 0.1 μA/μm for VDD = 1.2 V. Identical gate stacks processed with a 1000-°C spike anneal have a higher peak mobility at 275 cm²/V · s, but a 5-Å higher EOT and a reduced drive current at 610 μA/μm. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 °C) for a ten-year lifetime, whereas positive-bias temperature-instability :measurements indicate a sufficient lifetime for operating voltages below 0.75 V. [ABSTRACT FROM AUTHOR]

Bi-Iayer gate stacks consisting of a HfO2 and an interfacial layer are fabricated by remote plasma oxidation (RPO) of Hf metal deposited on an Si substrate. Hf metal is fully oxidized by the RPO even at a temperature as low as 400 °C due to radical oxygens, leading to an improvement in the quality of HfO2 with less impact to the interfacial layer growth. An insufficient oxidation leads to a deterioration of mobility with increasing interface traps and positive bias temperature instability, which is likely caused by the oxygen vacancies acting as traps induced by the remaining Hf metal. The SiO2 -like interface improves the mobility with reduced interface states. Full oxidation and the controlled SiO2-like interface demonstrate RPO as a promising way for gate-stack optimization. [ABSTRACT FROM AUTHOR]

Dielectric relaxation currents in SiO2 /Al2O3 and SiO2 /HfO2 high-κ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-κ dielectric stacks. It is found that high-κ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-κ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO2/high-κ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO2/high-κ interface is a key requirement for high-κ dielectric stack application and reliability in MOS devices. [ABSTRACT FROM AUTHOR]

We propose a bilayer graphene (BLG) tunneling field-effect-transistor (TFET) suitable for digital CMOS logic circuits. The ultimate performance limit of this structure is evaluated by solving the quantum transport equations in nonequilibrium Green’s function framework. A bandgap opening is induced in BLG using both vertical electric field and top–bottom asymmetric chemical doping. To overcome the limitations of nonabrupt p-i-n junctions using practical process methods, source/drain regions are created using work-function engineered metal-graphene contacts. We evaluate the performance of BLG-TFET by taking doping gradient due to contact induced doping into account. Our BLG-TFET exhibits a subthreshold slope as low as 35 mV/dec, and I\mathrm{{\scriptstyle ON}}/I\mathrm{{\scriptstyle OFF}} as high as 2910 for a supply voltage of 0.2 V. The proposed BLG-TFET shows promise for ultralow-power applications, particularly in low to medium speed applications. [ABSTRACT FROM AUTHOR]

Conduction band-edge effective work functions (ϕm,eff) are demonstrated with TaCx and TiN by means of La2O3 capping of HfSiOx in a gate-first process flow with CMOS- compatible thermal budget. With TaCx, a 10-Å-thick La2O3 cap results in a ϕm,eff of 3.9 eV with a low equivalent oxide thickness (EOT) increase (1-2 Å) and unaffected electron mobility. With TiN, non-nitrided La2O3 capping results in a smaller ϕm,eff reduction at a larger EOT increase, while with post-cap nitridation, the TiN ϕm,eff is lower at a smaller EOT increase. Results show that the choice of metal and nitridation conditions have significant effects on La2O3 capped stacks. [ABSTRACT FROM AUTHOR]