297 results on '"de Man, H."'
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2. Panel session - great challenges in nanoelectronics and impact on academic research: More than Moore or Beyond CMOS?
3. Soft-in soft-out Reed-Solomon decoding using critically subsampled filterbanks
4. Filterbank decompositions for BCH-codes with applications to soft decoding and code division multiple acces systems
5. Scalable Gate-Level Models for Power and Timing Analysis.
6. CTH03-3: Reed-Solomon Codes Implementing a Coded OFDM Scheme for Rayleigh Fading Channels.
7. Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
8. Nanoscale System Design Challenges: Business as Usual?
9. High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.
10. Spatial-mode selection based on channel mean feedback for a robust joint linear precoder and decoder MMSE design.
11. Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs].
12. Measurement of the nonlinear behavior of a MEMS variable capacitor.
13. Joint compensation of IQ imbalance and frequency offset in OFDM systems.
14. Guidelines for managing bias in project risk management.
15. Spatial-mode selection for the joint transmit and receive MMSE design over flat-fading MIMO channels.
16. A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technology.
17. Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
18. Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits.
19. DRESC: a retargetable compiler for coarse-grained reconfigurable architectures.
20. OFDM-WLAN receiver performance improvement using digital compensation techniques.
21. MEMS variable capacitor versus MOS variable capacitor for a 5GHz voltage controlled oscillator.
22. Modeling and experimental verification of substrate noise generation in a 220Kgates WLAN system–on–chip with multiple supplies.
23. Cache conscious data layout organization for embedded multimedia applications.
24. High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
25. A systematic approach for system bus load reduction applied to medical imaging.
26. A highly linear BiCMOS down-conversion mixer with MCM passives for GPS applications.
27. Virtual Java/FPGA interface for networked reconfiguration.
28. Operating system based software generation for systems-on-chip.
29. Flexible hardware acceleration for multimedia oriented microprocessors.
30. Task concurrency management experiment for power-efficient speed-up of embedded MPEG4 IM1 player.
31. A hardware virtual machine for networked reconfiguration.
32. Formalized three-layer system-level reuse model and methodology for embedded data-dominated applications.
33. Extended design reuse trade-offs in hardware-software architecture mapping.
34. Trading-off power versus area through a parameterizable model for virtual memory management
35. A novel class of uplink of OFDM/SDMA algorithms: a statistical performance analysis
36. Embedded architecture co-synthesis and system integration
37. A single-package solution for wireless transceivers.
38. On the use of C++ for system-on-chip design.
39. Parametrizable behavioral IP module for a data-localized low-power FFT.
40. Area and Timing Optimisation of high performant datapaths with CHOPIN-2
41. The systematic design of a motion estimation array architecture.
42. Design technology research for the nineties.
43. CGE.
44. SLOCOP-II.
45. SPI.
46. Open-ended system for high-level synthesis of flexible signal processors.
47. A combined waveform relaxation.
48. Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment.
49. CoWare—a design environment for heterogenous hardware/software systems.
50. A programmable CDMA IF transceiver ASIC for wireless communications.
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