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Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

Racetrack memory (RTM) is a promising nonvolatile memory that provides multibit storage cells achieving a higher area and leakage energy efficiency compared to contemporary volatile and nonvolatile memories. These features make RTM a potential candidate to be used as a last-level-cache (LLC). One drawback of the multibit RTM cell is the serialized access to the stored data, resulting in a shift penalty to access a particular bit within the cell. This overhead is particularly critical for LLC tags, for which prior RTM designs place tags either in SRAM or in single-bit RTM cells. While this avoids shifting, these designs require a large number of leaky cells incurring high energy consumption. To address this problem, this article proposes an energy-efficient RTM design called BlendCache that efficiently stores the tags in the leakage-optimized multibit RTM cells. To reduce the RTM shift penalty of these cells, BlendCache exploits the spatial locality of programs by maximizing accesses to nearby locations in RTM. Employing 32-bit RTM cells for a single core, BlendCache reduces the energy consumption by 20.8% and area by 15.2% compared to the state-of-the-art while its impact on performance is negligible. For a 4-core system, the energy improvement translates to 35.9% with 3% performance degradation. [ABSTRACT FROM AUTHOR]

Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of the hottest server components (i.e., cores and cache). Previous methods focused on either improving energy efficiency by adopting new hybrid-cache architectures including the resistive random-access memory (RRAM) and static random-access memory (SRAM) at the hardware level, or exploring tradeoffs between lifetime limitation and performance of multicore processors under stable workloads conditions. Therefore, no work has so far proposed a co-optimization method with hybrid-cache-based server architectures for real-life dynamic scenarios taking into account scalability, performance, lifetime reliability, and energy efficiency at the same time. In this article, we first formulate a reliability model for the hybrid-cache architecture to enable precise lifetime reliability management and energy efficiency optimization. We also include the performance and energy overheads of cache switching, and optimize the benefits of hybrid-cache usage for better energy efficiency and performance. Then, we propose a runtime $q$ -learning-based reliability management and performance optimization approach for multicore microprocessors with the hybrid-cache architecture, jointly incorporated with a dynamic preemptive priority queue management method to improve the overall tasks’ performance by targeting to respect their end time limits. Experimental results show that our proposed method achieves up to 44% average performance (i.e., tasks execution time) improvement, while maintaining the whole system design lifetime longer than five years, when compared to the latest state-of-the-art energy efficiency optimization and reliability management methods for computing servers. [ABSTRACT FROM AUTHOR]

The most commonly used memory cells, namely a 32-bit $\times10$ -bit read-only memory, a 1-bit 4-transistor static random-access memory, D latch, and D flip-flop (DFF), were demonstrated using high temperature (HT) GaN technology on a monolithically integrated GaN-on-Si platform and n-FET-only E/D-mode logic (E: enhancement, D: depletion). The memory cells exhibit stable operation at 300 °C. A maximum clock frequency of 36 MHz at 300 °C was estimated for the DFF using the measured setup time. To the best of the authors’ knowledge, the operational temperature of the reported prototypes represents the highest value for GaN memory, paving the way for the realization of robust mixed-signal systems operating at HT. [ABSTRACT FROM AUTHOR]

Hierarchical high-radix router microarchitecture consisting of small SRAM-based intermediate buffers has been used in large-scale supercomputers interconnection networks. While hierarchical organization enables efficient scaling to higher switch port count, it requires intermediate buffers which can cause performance bottleneck. Shallow intermediate buffers can cause head-of-line blocking to create backpressure towards input buffers and reduce overall performance. Increasing intermediate buffer size overcomes this problem but becomes infeasible due to the large overhead. In this work, we propose to organise decentralized intermediate buffers as a centralized buffer and leverage alternate memory technology to increase its capacity. In particular, we exploit the high-density nature of Spin-Torque Transfer Magnetic RAM (STT-MRAM) to increase intermediate buffer depth while also providing near-zero leakage power. STT-MRAM has disadvantages such as higher write latency and higher write energy. To overcome these disadvantages, we propose DeepHiR, a novel deep hybrid buffer organization (STT-MRAM and SRAM) combined with a centralized buffer organization to provide high performance with minimal cost. Although the deep intermediate buffer provided by DeepHiR can effectively improve router performance, a large amount of input buffer will still cause a lot of hardware overhead. At the same time, deeper intermediate buffers also makes it take longer for the backpressure to propagate to the source node, thereby reducing the performance of DeepHiR. Therefore, we further propose ElasHiR, which leverages elastic input buffer design in the centralized row buffer to allow a part of the centralized row buffer to act as input buffer. ElasHiR adopts reduced input buffers and automatically determines the length of input buffer in the centralized row buffer. This design minimizes the buffer resource while achieving excellent efficiency. Evaluation results show that DeepHiR can achieve 56.7 percent performance improvement in packet latency under synthetic traffic, and the cost of energy and area is moderate. ElasHiR can reduce the input buffer by 93.8 percent with performance comparable to DeepHiR. [ABSTRACT FROM AUTHOR]

Nowadays, field programmable gate arrays (FPGAs) have been widely adopted to serve as accelerators in artificial intelligence and big data related applications. Since the static random access memory (SRAM)-based FPGA is suffering from limited density and high leakage power, nonvolatile FPGAs have been proposed, where SRAM is replaced with emerging nonvolatile memories (NVMs). Multilevel cell (MLC), which can store multiple bits within one memory cell, further improves the density of nonvolatile FPGAs and shows great potential to enable large on-chip memory. However, it suffers from limited lifetime. In this article, we propose a wear leveling scheme to improve lifetime of MLC-based nonvolatile FPGAs. Instead of generating a series of configuration files for runtime reconfiguration, we propose to identify write-heavy MLC regions and dynamically transform them to durable single-level cell (SLC) mode. Specifically, we propose three modules: 1) pertaining to write behavior monitor; 2) approximate cost calculator; and 3) mode transformation manager to achieve adaptive mode transformations. We consider FPGA features to design these modules, which is different from implementations for MLC-SLC transformation in CPU architecture. Evaluation shows that the proposed scheme can improve lifetime for MLC nonvolatile FPGAs by $6.03\times $ , at cost of 12.5% storage overhead. [ABSTRACT FROM AUTHOR]

RRAM-based in-memory computing (IMC) effectively accelerates deep neural networks (DNNs) and other machine learning algorithms. On the other hand, in the presence of RRAM device variations and lower precision, the mapping of DNNs to RRAM-based IMC suffers from severe accuracy loss. In this work, we propose a novel hybrid IMC architecture that integrates an RRAM-based IMC macro with a digital SRAM macro using a programmable shifter to compensate for the RRAM variations and recover the accuracy. The digital SRAM macro consists of a small SRAM memory array and an array of multiply-and-accumulate (MAC) units. The nonideal output from the RRAM macro, due to device and circuit nonidealities, is compensated by adding the precise output from the SRAM macro. In addition, the programmable shifter allows for different scales of compensation by shifting the SRAM macro output relative to the RRAM macro output. On the algorithm side, we develop a framework for the training of DNNs to support the hybrid IMC architecture through ensemble learning. The proposed framework performs quantization (weights and activations), pruning, RRAM IMC-aware training, and employs ensemble learning through different compensation scales by utilizing the programmable shifter. Finally, we design a silicon prototype of the proposed hybrid IMC architecture in the 65-nm SUNY process to demonstrate its efficacy. Experimental evaluation of the hybrid IMC architecture shows that the SRAM compensation allows for a realistic IMC architecture with multilevel RRAM cells (MLCs) even though they suffer from high variations. The hybrid IMC architecture achieves up to 21.9%, 12.65%, and 6.52% improvement in post-mapping accuracy over state-of-the-art techniques, at minimal overhead, for ResNet-20 on CIFAR-10, VGG-16 on CIFAR-10, and ResNet-18 on ImageNet, respectively. [ABSTRACT FROM AUTHOR]

Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-/energy-constrained edge devices due to the strong voltage scaling capability, fast design iteration, and flexibility in integration. In this article, a 13-transistor (13T) static-random access memory (SRAM) circuit with ultra-wide range voltage scaling capability is proposed for ultra-low-power applications. By adopting the concept of SCM, the 13T SRAM cell is custom-designed, while providing fully digital inputs and outputs. Without any analog circuitry, the 13T memory array is fully synthesizable and compatible with the commercial semi-custom design flow. A specialized circuitry is employed in the 13T SRAM cell to enable cell-level bit-interleaving. An 8-kb 13T SRAM bank is fabricated in the UMC 55-nm low power CMOS technology, achieving an area density of $5 \mu \text{m}$ 2/bit. The minimum operational voltage for the 13T SRAM circuit is 324 mV, while the data retention voltage is down to 279 mV. The 13T SRAM circuit achieves the minimum energy point at 0.4 V for both the read (32.8 fJ/bit) and write (54.1 fJ/bit) operations, providing a good opportunity to perform voltage scaling together with logic blocks when embedded in the same power domain. [ABSTRACT FROM AUTHOR]

In this work, we present a novel 8T static random access memory (SRAM)-based compute-in-memory (CIM) macro for processing neural networks with high energy efficiency. The proposed 8T bitcell is free from disturb issues thanks to the decoupled read channels by adding two extra transistors to the standard 6T bitcell. A 128 $\times $ 128 8T SRAM array offers massively parallel binary multiply and accumulate (MAC) operations with 64 $\times $ binary inputs (0/1) and 64 $\times $ 128 binary weights (+1/–1). After parallel MAC operations, 128 column-based neurons generate 128 $\times $ 1–5 bit outputs in parallel. The proposed column-based neuron comprises 64 $\times $ bitcells for dot-product, 32 $\times $ bitcells for analog-to-digital converter (ADC), and 32 $\times $ bitcells for offset calibration. The column ADC with 32 $\times $ replica SRAM bitcells converts the analog MAC results (i.e., a differential read bitline (RBL/RBLb) voltage) to the 1–5 bit output code by sweeping their reference levels in 1–31 cycles (i.e., $2^{N}$ –1 cycles for $N$ -bit ADC). The measured linearity results [differential nonlinearity (DNL) and integral nonlinearity (INL)] are +0.314/–0.256 least significant bit (LSB) and + 0.27/–0.116 LSB, respectively, after offset calibration. The simulated image classification results are 96.37% for Mixed National Institute of Standards and Technology database (MNIST) using a multi-layer perceptron (MLP) with two hidden layers, 87.1%/82.66% for CIFAR-10 using VGG-like/ResNet-18 convolutional neural networks (CNNs), demonstrating slight accuracy degradations (0.67%–1.34%) compared with the software baseline. A test chip with a 16K 8T SRAM bitcell array is fabricated using a 65-nm process. The measured energy efficiency is 490–15.8 TOPS/W for 1–5 bit ADC resolution using 0.45-/0.8-V core supply. [ABSTRACT FROM AUTHOR]

The use of deep learning (DL) to real-world applications, such as computer vision, speech recognition, and robotics, has become ubiquitous. This can be largely attributed to a virtuous cycle between algorithms, data and computing, and storage capacity, which has driven rapid advances in all these dimensions. The ever-increasing demand for computation and memory from DL workloads presents challenges across the entire spectrum of computing platforms, from edge devices to the cloud. Hence, there is a need to explore new hardware paradigms that go well beyond the current mainstays such as graphical processing units (GPUs), tensor processing units (TPUs), and neural processing units (NPUs). A key bottleneck of current platforms is the so-called memory wall, which arises from the need to move large amounts of data between memory and compute units, expending considerable time and energy. One promising solution to this challenge is to move some computations either closer to memory, within the memory subsystem, or even within individual memory arrays. This approach, which is broadly referred to as compute-in-memory (CiM), has the potential to break the memory wall, and thereby greatly improve speed and power consumption. In this article, we provide an overview of CiM techniques used at different levels of the memory hierarchy and based on different memory technologies, including static random access memories (SRAMs), nonvolatile memories (NVMs), and DRAMs. We also discuss architectural approaches to designing CiM-based DL accelerators. Finally, we discuss the challenges associated with adopting CiM in future DL accelerators. [ABSTRACT FROM AUTHOR]

As one type of associative memory, content-addressable memory (CAM) has become a critical component in several applications, including caches, routers, and pattern matching. Compared with the conventional CAM that could only deliver a “matched or not-matched” result, emerging multilevel CAM (ML-CAM) is capable of delivering “the degree of match” with multilevel distance calculation. This feature has been desired in applications that need beyond-Boolean matching results. However, existing ML-CAM designs are limited by the bit-cell device discharging current mismatch and vulnerability to the timing of sensing operations for distance calculation. This inherent constraint makes it difficult to further improve the accuracy and scalability toward higher accuracy and higher dimension matching. In this work, we propose CapCAM, a multilevel Capacitive Content Addressable Memory. It could be implemented based on either static random-access memory (SRAM) or emerging technologies, e.g., the ferroelectric field-effect transistor (FeFET). CapCAM could provide linear and stable voltage drop scaled by the match degree and need no strict timing for result sensing, which embraces the high-accuracy and high-scalability search. The inherent enabler of CapCAM is the charge-domain computing mechanism. This article will present the basic concept, operating mechanisms, detailed circuit designs, and circuit-level simulations of CapCAM. Besides, we apply CapCAM to few-shot learning applications and compare CapCAM with the current-domain TCAM designs. Results show 99.2% accuracy for a five-way five-shot classification task with our proposed CapCAM design while considering 1-fF capacitors, 20-domain FeFETs, and 256 columns. In contrast, the prior work based on discharging dynamics requires strict timing controls and suffers from accuracy degradation under the same configuration, which demonstrates CapCAM’s capability of low-power, accurate, and scalable multilevel CAM (ML-CAM) computing. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM) technologies, such as spin-transfer torque magnetic random access memory (STT-MRAM) and spin-orbit torque magnetic random access memory (SOT-MRAM), have significant advantages compared to conventional SRAM due to their nonvolatility, higher cell density, and scalability features. While previous work has investigated several architectural implications of NVM for generic applications, in this work, we present DeepNVM ++, a framework to characterize, model, and analyze NVM-based caches in GPU architectures for deep learning (DL) applications by combining technology-specific circuit-level models and the actual memory behavior of various DL workloads. We present both iso-capacity and iso-area performance and energy analysis for systems whose last-level caches rely on conventional SRAM and emerging STT-MRAM and SOT-MRAM technologies. In the iso-capacity case, STT-MRAM and SOT-MRAM provide up to $3.8 \times $ and $4.7 \times $ energy-delay product (EDP) reduction and $2.4 \times $ and $2.8 \times $ area reduction compared to conventional SRAM, respectively. Under iso-area assumptions, STT-MRAM and SOT-MRAM provide up to $2 \times $ and $2.3 \times $ EDP reduction and accommodate $2.3 \times $ and $3.3 \times $ cache capacity when compared to SRAM, respectively. We also perform a scalability analysis and show that STT-MRAM and SOT-MRAM achieve orders of magnitude EDP reduction when compared to SRAM for large cache capacities. Our comprehensive cross-layer framework is demonstrated on STT-/SOT-MRAM technologies and can be used for the characterization, modeling, and analysis of any NVM technology for last-level caches in GPUs for DL applications. [ABSTRACT FROM AUTHOR]

This article obtains fundamental limits on the computational precision of in-memory computing architectures (IMCs). An IMC noise model and associated signal-to-noise ratio (SNR) metrics are defined and their interrelationships analyzed to show that the accuracy of IMCs is fundamentally limited by the compute SNR (${\mathrm {SNR}}_{a}$) of its analog core, and that activation, weight, and output (ADC) precision needs to be assigned appropriately for the final output SNR (${\mathrm {SNR}}_{T}$) to approach ${\mathrm {SNR}}_{a}$. The minimum precision criterion (MPC) is proposed to minimize the analog-to-digital converter (ADC) precision and hence its overhead. Three in-memory compute models—charge summing (QS), current summing (IS), and charge redistribution (QR)—are shown to underlie most known IMCs. Noise, energy, and delay expressions for the compute models are developed and employed to derive expressions for the SNR, ADC precision, energy, and latency of IMCs. The compute SNR expressions are validated via Monte Carlo simulations in a 65 nm CMOS process. For a 512 row SRAM array, it is shown that: 1) IMCs have an upper bound on their maximum achievable ${\mathrm {SNR}}_{a}$ due to constraints on energy, area and voltage swing, and this upper bound reduces with technology scaling for QS-based architectures; 2) MPC enables ${\mathrm {SNR}}_{T}$ to approach ${\mathrm {SNR}}_{a}$ to be realized with minimal ADC precision; and 3) QS-based (QR-based) architectures are preferred for low (high) compute SNR scenarios. [ABSTRACT FROM AUTHOR]

The article presents an efficient static random access memory (SRAM)-based in-memory computation (IMC) architecture which is capable of performing image classification with improved linearity. In this work, we proposed a thermometric code-based IMC (TC-IMC) to perform multibit multiply-and-accumulate (MAC) operations with improved linearity. An input sparsity-aware compact thermometric code approach is proposed to reduce the number of SRAM bitcells compared to the thermometric code-based encoding without loss of accuracy in the MAC operation. We proposed an optimal sampling time to improve the linearity of the TC-IMC MAC operation with maximum signal margin (SM) based on the detailed nonlinearity analysis of 8T SRAM-based TC-IMC architecture. The test chip measurement results in 180 nm process show that the proposed TC-IMC has 72% better linearity than the traditional IMC. The measured results on 100 Modified National Institute of Standards and Technology (MNIST) and CIFAR-10 test images show an accuracy of 97% and 87%, respectively. In addition, the proposed TC-IMC architecture achieves MAC compute latency of 25 ns, GOPS/kb (normalized to 1 b $\times $ 1 b) of 29.8, and energy efficiency of 2.3 TOPS/W. The simulation result of the entire 10000 MNIST and CIFAR-10 images considering process variation effects shows an accuracy of 98.7% and 90.4%, respectively. [ABSTRACT FROM AUTHOR]

FPGAs are increasingly becoming sensitive to aging effects mainly through BTI phenomena in the latest technology nodes. This phenomenon can be modeled as a shift in the threshold voltage of transistors which leads to performance degradation and reduction in SNM of SRAM cells. To reduce the aging effects on FPGA building blocks, we propose FIFA, a fully invertible FPGA architecture. In this architecture, two small modules are introduced to make the bitstream of logic and routing resources of the FPGA tiles fully invertible. Accordingly, to insert recovery cycles in the lifetime of the transistors, the bitstream stored in the configuration SRAM cells can be inverted occasionally without any changes in the functionality of the design. Using the proposed architecture, it is neither required to repeat the placement and routing procedures to generate multiple configuration bitstreams, nor extra memory is needed to save alternative bitstreams for changing the SRAM cells’ contents. Our experimental results over a set of industrial benchmarks show that by choosing an appropriate switch block arrangement and an optimized flipping frequency, the proposed architecture can improve the aging induced performance degradation by up to 62.5% with acceptable power and area overheads on logic and routing resources. [ABSTRACT FROM AUTHOR]

As performance and energy-efficiency improvements from technology scaling are slowing down, new technologies are being researched in hopes of disrupting results. Domain wall memory (DWM) is an emerging non-volatile technology that promises extreme data density, fast access times and low power consumption. However, DWM access time depends on the memory location distance from access ports, requiring expensive shifting. This causes overheads on performance and energy consumption. In this article, we implement our previously proposed shift-reducing instruction memory placement (SHRIMP) on a RISC-V core in RTL, provide the first thorough evaluation of the control logic required for DWM and SHRIMP and evaluate the effects on system energy and energy-efficiency. SHRIMP reduces the number of shifts by 36% on average compared to a linear placement in CHStone and Coremark benchmark suites when evaluated on the RISC-V processor system. The reduced shift amount leads to an average reduction of 14% in cycle counts compared to the linear placement. When compared to an SRAM-based system, although increasing memory usage by 26%, DWM with SHRIMP allows a 73% reduction in memory energy and 42% relative energy delay product. We estimate overall energy reductions of 14%, 15% and 19% in three example embedded systems. [ABSTRACT FROM AUTHOR]

Electromigration (EM) is crucial for interconnect reliability. This article introduces the implementation and application of CacheEM which targets SRAM cache memory aging due to EM. CacheEM is based on a comprehensive framework including five parts: 1) microprocessor emulation; 2) memory cell array activity extraction; 3) computation of currents in segments of long complex interconnect structures; 4) evaluation of the time-dependent hydrostatic stress and the resistance shift of interconnects; and 5) characterization of the EM lifetime distribution of interconnects in the cache memory. The first two steps (top-down) are implemented with gem5 and cache simulation, respectively. These simulators export the number of read and write operations for each cell of a cache memory in a microprocessor after running benchmarks. Then, based on the number of operations and the currents corresponding to each operation, CacheEM calculates the equivalent current distribution in each interconnect segment as the third step (bottom-up). The currents due to read and write operations are stored in models which have been pretrained with a regression algorithm. These models provide accurate predictions of the corresponding currents under various parameter settings, such as temperature, supply voltage, and gate length. Afterward, the samples of time-dependent hydrostatic stress and the resistance shift in each interconnect segment are computed while incorporating the variations of the effective activation energy and critical stress. The EM lifetime distribution of the cache memory is extracted using predefined threshold values. The impact of configuration parameters on EM reliability and performance of the SRAM cache is analyzed by comparing EM lifetime distributions. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) has long been deemed to be an alternative or supplementary to complementary metal oxide semiconductor (CMOS) technology in theory in the future. In general, QCA works indispensably through a four-phase clocking mechanism. However, previous works on QCA circuits mainly use the clocking to enable the synchronization of signals. In this brief, a static random access memory (SRAM) is proposed for the first time by making use of the phase difference between adjacent clock zones of the unique clocking mechanism. The SRAM saves the address decoders and thus reduces the hardware cost. A look-up table (LUT) is then built through the SRAM to achieve a significant reduction in hardware cost. To verify the practicability of these circuits proposed above, a configurable logic block (CLB) in Xilinx’s XC4000 field-programmable gate array as an example is designed. Simulation results using QCADesigner-E show that the proposed circuits have correct functions and advantages in area, cell count, delay, cost, and energy dissipation compared with previous designs. Note that these circuits are easy to be extended to 16-bit, 32-bit, or higher bit. [ABSTRACT FROM AUTHOR]

Keyword spotting (KWS) has gained popularity as a natural way to interact with consumer devices in recent years. However, because of its always on nature and the variety of speech, it necessitates a low-power design as well as user customization. This article describes a low-power, energy-efficient KWS accelerator with static random access memory (SRAM)-based in-memory computing (IMC) and on-chip learning for user customization. However, IMC is constrained by macro size, limited precision, and nonideal effects. To address the issues mentioned above, this article proposes bias compensation and fine-tuning using an IMC-aware model design. Furthermore, because learning with low-precision edge devices results in zero error and gradient values due to quantization, this article proposes error scaling and small gradient accumulation to achieve the same accuracy as ideal model training. The simulation results show that with user customization, we can recover the accuracy loss from 51.08% to 89.76% with compensation and fine-tuning and further improve to 96.71% with customization. The chip implementation can successfully run the model with only 14 $\mu \text{J}$ per decision. When compared to the state-of-the-art works, the presented design has higher energy efficiency with additional on-chip model customization capabilities for higher accuracy. [ABSTRACT FROM AUTHOR]

This article investigates the single-event effects on 16-nm bulk field-effect transistors (FinFETS) in terms of single-bit upsets and multiple-cell upsets under heavy ion irradiation. These upsets are analyzed and classified according to voltage, linear energy transfer of ions, data patterns, and fail bit patterns. The analysis suggested a characteristic charge collection mechanism attributable to the FinFET structure. Estimation of a unique sensitive area shape based on cross sections is also discussed. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) with an interleaved bitmap design is of special concern for space applications because the interleaving architecture improves the efficiency of error correction code for single-event upsets (SEUs) in a harsh radiation environment. However, most of the interleaving layout is kept unreleased from the manufacturer, and determining the interleaving parameters of an intact SRAM is a challenge for the radiation hardening system. This work proposed a theoretical decryption model of conventional interleaved bitmaps based on the principle of multiple-bit upset (MBU) correlation analysis. The decryption method was practically implemented with a commercial SRAM, and its unknown interleaving architecture was resolved by the spatial correlation and MBU distance upon SEU fault injection attack with 252Cf source. The disclosed interleaving architecture, the subbyte characteristics, and the bit subblock distribution of the device under test (DUT) are in good agreement with the bitmap obtained with SEU mapping of the microbeam. This work demonstrates the valid and robust SRAM layout decryption model and provides a viable approach for evaluating correction efficiency and component reliability in the radiation hardening system. [ABSTRACT FROM AUTHOR]

This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based built-in self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs. [ABSTRACT FROM AUTHOR]

Driven by the trends of emerging technologies in on-chip memories, with increasing the size of last-level caches (LLCs), spin-transfer torque magnetic random access memories (STT-MRAMs) are the most promising alternative technology among the non-volatile memories (NVMs) to replace SRAMs. Despite their high density, scalability, and near-zero leakage power, the reliability of STT-MRAM LLCs is threatened by a high error rate due to their stochastic switching behavior. The error rate is highly influenced by the cache management, which necessitates redesigning the cache replacement policy based on the error behavior. In this article, we propose an error-aware cache replacement policy, namely, conditional replacement policy (CRP), to improve the reliability of STT-MRAM caches by decreasing the rate of both read disturbance and write failure. This is ascertained by nominating an appropriate data block in the cache to be replaced with an incoming data block, considering the minimum error rate. Moreover, the performance and latency of both write and read operations are considered. The simulation results show that compared with the state-of-the-art replacement policy in STT-MRAM caches, CRP reduces the total error rate by 68%. In addition, the proposed policy enhances the performance by 2% and saves energy consumption by 19%, on average. Meanwhile, the total number of writes is decreased by 41% compared with the previous scheme. [ABSTRACT FROM AUTHOR]

We study the radiation environment near the terahertz (THz) dump of the CERN Linear Electron Accelerator for Research (CLEAR) electron accelerator at CERN, using FLUktuierende KAskade in German (FLUKA) simulations and single-event upset (SEU) measurements taken with 32-Mbit Integrated Silicon Solution Inc. (ISSI) static random access memories (SRAMs). The main focus is on the characterization of the neutron field to evaluate its suitability for radiation tests of electronics in comparison with other irradiation facilities. Neutrons at CLEAR are produced via photonuclear reactions, mostly initiated by photons from the electromagnetic cascades that occur when the beam is absorbed by the dump structure. Good agreement is generally found between the measured single-event upset (SEU) rates and the expected values obtained from FLUKA simulations and the known SEU response of the ISSI SRAMs to neutrons, while one position is found to be potentially affected by photon-driven SEUs. [ABSTRACT FROM AUTHOR]

Existing person re-identification (Re-ID) methods usually rely heavily on large-scale thoroughly annotated training data. However, label noise is unavoidable due to inaccurate person detection results or annotation errors in real scenes. It is extremely challenging to learn a robust Re-ID model with label noise since each identity has very limited annotated training samples. To avoid fitting to the noisy labels, we propose to learn a prefatory model using a large learning rate at the early stage with a self-label refining strategy, in which the labels and network are jointly optimized. To further enhance the robustness, we introduce an online co-refining (CORE) framework with dynamic mutual learning, where networks and label predictions are online optimized collaboratively by distilling the knowledge from other peer networks. Moreover, it also reduces the negative impact of noisy labels using a favorable selective consistency strategy. CORE has two primary advantages: it is robust to different noise types and unknown noise ratios; it can be easily trained without much additional effort on the architecture design. Extensive experiments on Re-ID and image classification demonstrate that CORE outperforms its counterparts by a large margin under both practical and simulated noise settings. Notably, it also improves the state-of-the-art unsupervised Re-ID performance under standard settings. Code is available at https://github.com/mangye16/ReID-Label-Noise. [ABSTRACT FROM AUTHOR]

Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6 $\times $ logic density, 1.5 $\times $ energy efficiency, and 1.4 $\times $ operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration. [ABSTRACT FROM AUTHOR]

It is anticipated that ubiquitous computer vision (CV) and artificial intelligence (AI) applications used on mobile devices will grow significantly. Such applications require battery-powered, always-on mobile devices to support indoor/outdoor, day/night usages. A global shutter (GS), stacked digital pixel sensor (DPS) is a promising candidate to meet such requirements because of its potential for ultralow-power, ultrahigh dynamic range (HDR), and a small form factor. This article presents a prototype 4.0- ${\mu } \text{m}$ stacked DPS operating in its dual quantization (2Q) to realize HDR. The 4.0- ${\mu }\text{m}$ DPS pixel is formed with two layers, a backside illuminated pinned photodiode (PD) pixel on the top layer and an in-pixel analog-to-digital conversion (ADC) circuit with 9-bit static random access memory (SRAM) on the bottom layer. A Cu-to-Cu hybrid bonding (HB) technology is used to connect the two layers via pixel-level interconnect. In the 2Q scheme, a time-stamp (TS) quantization and a linear ADC are performed sequentially in the same frame, which extends the dynamic range (DR) with a small number of ADC bits of 9. The DPS with a 1024 $\times$ 832 pixel array has achieved a single-exposure ultra HDR of 107 dB in a single frame. The nonlinear conversion characteristic of the TS mode provides an equivalent full well capacity (FWC) of 2000ke−, while the noise floor in the linear ADC mode is 8.3e−. [ABSTRACT FROM AUTHOR]

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate (PG) transistors on write margin considering the negative BL (NBL) assist technique. [ABSTRACT FROM AUTHOR]

On-chip memory (usually based on Static RAMs—SRAMs) are crucial components for various computing devices including heterogeneous devices, e.g., GPUs, FPGAs, and ASICs, to achieve high performance. Modern workloads such as deep neural networks (DNNs) running on these heterogeneous fabrics are highly dependent on the on-chip memory architecture for efficient acceleration. Hence, improving the energy efficiency of such memories directly leads to an efficient system. One of the common methods to save energy is undervolting, i.e., supply voltage underscaling below the nominal level. Such systems can be safely undervolted without incurring faults down to a certain voltage limit. This safe range is also called voltage guardband. However, reducing voltage below the guardband level without decreasing frequency causes timing-based faults. In this article, we propose MoRS, a framework that generates the first approximate undervolting fault model using real faults extracted from experimental undervolting studies on SRAMs to build the model. We inject the faults generated by MoRS into the on-chip memory of the DNN accelerator to evaluate the resilience of the system under the test. MoRS has the advantage of simplicity without any need for high-time overhead experiments while being accurate enough in comparison to a fully randomly generated fault injection approach. We evaluate our experiment in popular DNN workloads by mapping weights to SRAMs and measure the accuracy difference between the output of the MoRS and the real data. Our results show that the maximum difference between real fault data and the output fault model of MoRS is 6.21%, whereas the maximum difference between real data and random fault injection model is 23.2%. In terms of average proximity to the real data, the output of MoRS outperforms the random fault injection approach by $3.21\times $. [ABSTRACT FROM AUTHOR]

In this article, we present a CMOS image sensor (CIS) for coded-exposure-based compressive focal-stack imaging. The proposed CIS has a pixel design, which includes two capacitive trans-impedance amplifiers (CTIAs) and a static random access memory (SRAM), and is capable of per-frame exposure encoding with adjustable spatiotemporal resolutions. A proof-of-concept CIS prototype with a 192 $\times $ 192 pixel array is designed and fabricated in a 0.13- $\mu \text{m}$ CMOS process with a pixel size of 12.6 $\times $ 12.6 $\mu \text{m}^{2}$. Operating at 30 frames per second (fps), the CIS demonstrates spatial–temporal coded exposure at a maximum rate of 768 masks/frame. The column-wise 10-bit single-slope (SS) analog-to-digital converter (ADC) includes a ramp-slope adaptation feature used for power optimization. During a frame of coded exposure, a linear focal sweep is implemented by a voice-coil motor (VCM) lens mounted in front of the proposed CIS. Through the sparse reconstruction of the coded image, a focal stack consisting of a volume of defocused images is used to synthesize the scene depth map. By introducing coded exposure, the proposed on-chip compressive focal-stack imaging approach facilitates a frame-saving method for passive depth sensing in machine vision and other imaging applications. [ABSTRACT FROM AUTHOR]

To efficiently implement searching and logic functions with the SRAM-based in-memory computing (IMC), we need to perform computations on bitlines (BLs) (called compute access) via multiple wordline (WL) activations. However, this may cause prominent read disturbance when the IMC is implemented with the standard 6 T SRAM. To address this reliability issue, existing solutions adopt either auxiliary assistance circuits or alternative bitcell topologies, but they lead to substantial overheads of the access speed or array density. In this article, we propose a novel 8T compute SRAM (CSRAM) for reliable and high-speed in-memory searching and compound logic-in-memory computations. Our 8T CSRAM features a pair of pMOS access transistors and split-WLs dedicated to the compute access. A thorough circuit-level analysis reveals that the pMOS-based compute access port is essential for significantly mitigating the read disturbance. Moreover, we propose an elevated precharge voltage scheme and a low-skewed inverter-based sensing amplifier to improve the sensing speed. We have validated the proposed 8T CSRAM design in a 16 Kb array with a 28-nm CMOS technology. Compared to the state-of-the-art 8 T CSRAM, results show that our design is not only reliable but also 3.1 times faster, with a maximum operating frequency upping to 2.44 GHz. [ABSTRACT FROM AUTHOR]

Computing-in-memory (CIM) is a promising approach to reduce latency and improve the energy efficiency of the multiply-and-accumulate (MAC) operation under a memory wall constraint for artificial intelligence (AI) edge processors. This paper proposes an approach focusing on scalable CIM designs using a new ten-transistor (10T) static random access memory (SRAM) bit-cell. Using the proposed 10T SRAM bit-cell, we present two SRAM-based CIM (SRAM-CIM) macros supporting multibit and binary MAC operations. The first design achieves fully parallel computing and high throughput using 32 parallel binary MAC operations. Advanced circuit techniques such as an input-dependent dynamic reference generator and an input-boosted sense amplifier are presented. Fabricated in 28 nm CMOS process, this design achieves 409.6 GOPS throughput, 1001.7 TOPS/W energy efficiency, and a 169.9 TOPS/mm2 throughput area efficiency. The proposed approach effectively solves previous problems such as writing disturb, throughput, and the power consumption of an analog to digital converter (ADC). The second design supports multibit MAC operation (4-b weight, 4-b input, and 8-b output) to increase the inference accuracy. We propose an architecture that divides 4-b weight and 4-b input multiplication to four 2-b multiplication in parallel, which increases the signal margin by $16\times $ compared to conventional 4-b multiplication. Besides, the capacitive digital-to-analog converter (CDAC) area issue is effectively addressed using the intrinsic bit-line capacitance existing in the SRAM-CIM architecture. The proposed approach of realizing four 2-b parallel multiplication using the CDAC is successfully demonstrated with a modified LeNet-5 neural network. These results demonstrate that the proposed 10T bit-cell is promising for realizing robust and scalable SRAM-CIM designs, which is essential for realizing fully parallel edge computing.

Voltage-controlled spintronic devices are considered promising candidates for low-power applications due to the nonvolatility and the elimination of the Joule heating energy. Recently, experiments have demonstrated the voltage-controlled magnetization switching in the bismuth ferrite (BFO)/CoFe heterojunction that can achieve 180° switching at room temperature. In addition, it has been demonstrated that the ferroelectric coercive voltage of the La-doped BFO can be as low as 0.2 V by tuning the doping concentration of La and choosing a thinner BFO layer. To evaluate the potential performance of the magnetoelectric magnetic random access memory (ME-MRAM) using the BFO/CoFe heterojunction, we first build a physics-based compact model of the antiferromagnet/ferromagnet (AFM/FM) bilayer. The results from our circuit-compatible model match well with the micromagnetic simulations on the dynamics of the order parameters in both the AFM and FM layers. Next, we simulate the read and write performances of ME-MRAM using the compact model we have developed. Our results show that the write energy of the ME-MRAM can be as low as a few fJ per bit and the layout area is ~20 F2, which is more energy and area efficient compared to SRAM and other spintronic memory candidates. [ABSTRACT FROM AUTHOR]

Impact of high total ionizing dose (TID) irradiation on stability of 65 nm static random-access memory (SRAM) cells is investigated in this article. The stability of 65 nm SRAM cells is measured not only by the SRAM array but also by the independent cell test structure. The test chip has been subjected to a TID irradiation of 200 Mrad(Si). Experimental results show a reverse data pattern imprinting effect, i.e., irradiated 65 nm SRAM cells are more inclined to the complementary TID data pattern, and the above asymmetry of irradiated 65 nm SRAM cells is due to the bias-dependent shift in threshold of the pull-down nMOSFETs constituting the SRAM cell. [ABSTRACT FROM AUTHOR]

The contribution of mymargin elastic scattering to upsets caused by 1–10-MeV terrestrial neutrons in a 40-nm bulk SRAM and the influence of cascade recoils are investigated using Geant4 simulations. It is shown that elastic scattering, rather than ($n$ , $p$) or ($n$ , $\alpha$), is a dominant mechanism, contributing ~66% of the total upsets induced by 1–10-MeV neutrons. The dominance is attributed to the major role it plays in upset cross sections below ~6 MeV, and the abundance of lower energy neutrons due to $E^{- 1}$ dependence characteristic of the terrestrial neutron differential flux below 10 MeV. After considering ionization energy deposition of cascade recoils in Geant4 simulations, remarkable rises in upset cross sections of 27%, 18%, and 9% are observed for reactor, 2.5- and 1–10-MeV neutrons, which are the consequence of cascade recoils induced by primary Si ions. In-depth TRIM calculations on the ionization energy deposition of incident Si ions and cascade recoils have been performed, revealing that the underlying mechanism is the reduction in the threshold energy of Si ions from ~50 to ~30 keV if cascade recoils are taken into account. [ABSTRACT FROM AUTHOR]

For advanced technology nodes, the static random access memories (SRAMs) are highly vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by a high-energy ion strike, which is due to the small transistor size and close proximity of the sensitive regions. However, the narrow connection between the fin and the bulk region for fin field-effect transistor (FinFET) inhibits the charge collection compared to the planar transistor structure. In this work, heavy-ion tests were conducted for 16-nm bulk FinFET dual-port SRAMs at two high linear energy transfers (LETs) of 60 and 85 MeV $\cdot $ cm2/mg. The non-saturating behavior of the SEU cross sections and event cross sections for a bit cell is observed even over the LET of 60 MeV $\cdot $ cm2/mg due to the expanding of the sensitive area surrounding the array and the cutting-off area in the FinFET SRAM cells. The distribution curves of the MCU event probabilities for different MCU cluster sizes show that the single-bit upset (SBU) occupies the largest probability of all the single-event cluster sizes, which exhibits the inhibition capability of the Fin structure against the upsets induced by high-energy particles. The parasitic bipolar effect (PBE) is also serious for 16-nm FinFET SRAMs as former planar SRAM, but the charge-sharing effect is effectively inhibited due to the narrow connection between the fin and the bulk region for FinFET. Results presented in this article will help designers estimate the error correcting code (ECC) and interleaving design parameters for radiation-hardened SRAM designs at the 16-nm FinFET process. [ABSTRACT FROM AUTHOR]

We consider noisy communications and storage systems that are hampered by varying offset of unknown magnitude such as low-frequency signals of unknown amplitude added to the sent signal. We study and analyze a new detection method whose error performance is independent of both unknown base offset and offset’s slew rate. The new method requires, for a codeword length $n\geq 12$ , less than 1.5 dB more noise margin than Euclidean distance detection. The relationship with constrained codes based on mass-centered codewords and the new detection method is discussed. [ABSTRACT FROM AUTHOR]

The demand for high-performance computing and rapidly increasing power consumption has increased the necessity for application-specific accelerators. In the datacenter and mobile system, more applications are increasingly relying on accelerators. Field-programmable gate arrays (FPGAs) emerge as a good candidate because they have high programmability and power efficiency. As the number of applications requiring acceleration increases, there is huge demand for FPGAs that support multiple contexts. Previous FPGA designs that support multicontext have various shortcomings such as volatility, poor power efficiency, large performance, area, and reconfiguration overhead. In this article, we propose a spin-transfer torque magnetic RAM (STT-MRAM)-based nonvolatile multicontext FPGA (NVMC-FPGA) that overcomes these shortcomings. We introduce the NVMC-FPGA architecture and operation modes that take advantage of nonvolatility and support multicontext. We also develop the multicontext-aware FPGA computer aided design flow to make the most of the NVMC-FPGA. Compared to the conventional SRAM-based FPGA, when eight identical circuits are mapped, the NVMC-FPGA improves the performance by 15.3% on average and reduces the power consumption by 11.2%–80.7%, depending on the number of simultaneously activated circuits. Moreover, when eight different circuits are mapped, the NVMC-FPGA improves the performance by 58.5% on average and reduces the power consumption by 6.2%–63.3%, depending on the number of simultaneously activated circuits. [ABSTRACT FROM AUTHOR]

Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the large storage overheads and the substantial computational cost of CNNs are problematic in hardware accelerators. Computing-in-memory (CIM) architecture has demonstrated great potential to effectively compute large-scale matrix–vector multiplication. However, the intensive multiply and accumulation (MAC) operations executed on CIM macros remain bottlenecks for further improvement of energy efficiency and throughput. To reduce computational costs, model compression is a widely studied method to shrink the model size. For implementation in a static random access memory (SRAM) CIM–based accelerator, the model compression algorithm must consider the hardware limitations of CIM macros. In this study, a software and hardware co-design approach is proposed to design MARS, a SRAM-based CIM (SRAM CIM)-based CNN accelerator that can utilize multiple SRAM CIM macros as processing units and support a sparse CNN, and an SRAM CIM-aware model compression algorithm that considers a CIM architecture to reduce the number of network parameters. With the proposed hardware software co-designed method, MARS can reach over 700 and 400 FPS for CIFAR-10 and CIFAR-100, respectively. In addition, MARS achieves 52.3 and 88.2 TOPs/W in VGG16 and ResNet18, respectively. [ABSTRACT FROM AUTHOR]

Lattice-based cryptography (LBC), exploiting learning with error (LWE) problems, is a promising candidate for postquantum cryptography. The number theoretic transform (NTT) is the latency- and energy-dominant process in the computation of LWE problems. This article presents a compact and efficient in-MEmory NTT accelerator, named MeNTT, which explores an optimized computation in and near a 6T SRAM array. Specifically designed peripherals enable fast and efficient modular operations. Moreover, a novel mapping strategy reduces the data flow between the NTT stages into a unique pattern, which greatly simplifies the routing among processing units (i.e., the SRAM column in this work), reducing the energy and area overheads. The accelerator achieves significant latency and energy reductions over prior arts. [ABSTRACT FROM AUTHOR]

Frequent to-and-from data transfers in the von Neumann architecture limit the overall throughput. One of the promising approaches used to overcome von Neumann bottleneck is in-memory computing (IMC) that aims to embed computing in memory to reduce the transfer of memory-processor data. This study proposes a configurable 6-transistor (6T) static random access memory (SRAM) array with a multilevel shared structure for IMC. A multilevel shared structure can effectively improve the utilization rate of the module. In addition to the conventional SRAM operation, the configurable structure can also perform the sum of absolute differences (SAD) and Hamming distance (HD) calculations. To quickly identify the minimum value among multiple calculation results, a four-input sense amplifier (SA) is proposed. The performance of the proposed memory is simulated in a 65-nm CMOS process. The post-layout simulation results show good linearity of the multirow read in the SAD and HD modes. The mean time required by the four-input SA to obtain the result is 190 ps. The SAD and HD calculations yield consumptions of 67.44 fJ/byte and 0.64 fJ/bit, respectively, at 0.8 V. Furthermore, a single column-sharing comparator consumes 2.78 and 3.41 pJ at 0.8 V in the SAD and HD modes, respectively. [ABSTRACT FROM AUTHOR]

SRAM-based field-programmable gate array (FPGA) vendors typically integrate error correction codes (ECCs) into the configuration memory to assist designers in implementing scrubbing mechanisms. In most cases, these ECC schemes guarantee the correction of single- and double-bit errors per configuration frame but fail to correct upsets with higher multiplicity in a single frame caused by a single event. This phenomenon has been observed in modern commercial-off-the-shelf FPGAs. Bit interleaving schemes are used in some FPGA families to scatter the multiple upsets into more than one frame, but this does not fully resolve the problem of uncorrectable errors. In this article, we propose a configuration memory scrubbing approach for SRAM-based FPGA devices, which combines the embedded ECC logic with an interframe, interleaved parity code to build a mixed 2-D coding technique. The proposed technique improves the multiple-bit error correction capabilities of the on-chip ECC scheme while keeping the error correction latency and hardware cost low. The scrubbing concept has been validated under heavy-ion irradiation, where it succeeded in correcting all the single and multiple upsets observed during the radiation experiment. [ABSTRACT FROM AUTHOR]

Phase unwrapping is a challenging task in signal processing, spanning its applications in optical metrology, SAR interferometry, and many other signal reconstruction tasks. Fringe Projection Profilometry is a popular active-sensing approach for generating high-resolution three-dimensional (3D) surface information in which phase unwrapping is a crucial step. This letter proposes a multi-task learning-based phase unwrapping method for simultaneous denoising and wrap-count prediction in fringe projection. The proposed network, referred to as TriNet, has nested pyramidal architecture with a single encoder and two decoders, all connected through skip connections. The proposed approach does not require any pre-processing for noise removal like the conventional methods or any post-processing such as smoothing, like in existing deep learning methods but results in a quite accurate phase unwrapping. The proposed method outperforms the existing and state-of-the-art methods for the 3D reconstruction task in Fringe Projection by a significant margin even in the presence of very high noise. [ABSTRACT FROM AUTHOR]

The metal resistance increase due to interconnect pitch scaling was traditionally offset by interconnect length scaling. This is no longer the case for deeply scaled nodes with narrow critical dimensions (CDs) of metals. Static random access memories (SRAMs) route long critical signals such as bitlines and wordlines in lower metal layers of the back-end-of-line (BEOL) and are particularly affected by this metal resistance increase. Buried power rail (BPR) has been proposed in sub-5-nm nodes for routing power and ground lines to improve the performance and density of standard cells and mitigate voltage IR drop issues. We extend the work by exploring the use of buried interconnect for both signal and power routing in SRAMs with minimal process flow changes to the already proposed BPR technology. A high-accuracy 3-D field solver is used for accurate parasitic extraction of SRAM bitcells with buried interconnects. Industry-standard methods are used to evaluate the SRAM macro-level power–performance metrics. We show that the buried interconnects can improve SRAM access time by up to 11%, write time by up to 28%, and dynamic power by 4%, effectively equivalent to one full technology-node gain improvement. [ABSTRACT FROM AUTHOR]

This article proposes novel nonvolatile (NV) static random access memory (SRAM) circuits based on spin transfer torque (STT) and spin orbit torque (SOT) operated magnetic tunnel junction (MTJ) device for energy-efficient power gating circuits. In which, two different designs of 9T-2MTJs and 10T-2MTJ-based NV SRAM circuits are proposed for low power, high noise margin, and faster switching speed with less area overhead. The proposed architecture uses a smaller number of transistor combinations to accommodate low-power operation with compact cell size when compared with available pieces of literature. Also, the combination of nMOS and pMOS transistors in the proposed architecture enhances the driving capability of the circuit for both low and high input operations. Here, the electrical characteristics of the proposed designs have been compared and contrasted with the available 11T-2MTJ and 7T-2D-2MTJ non volatile static random access memory (NVSRAM) and 6T SRAM circuits using a UMC-40 nm design kit and physics-based STT–SOT MTJ Verilog-A Model. The proposed 9T-2MTJ-based NVSRAM was found to be a better alternative and offers improved performance in terms of higher restore noise margin and lower power consumption than other circuits reported at this node. Moreover, the studied 10T-2MTJ exhibits an improved write and hold noise margin than the proposed/available 9T/7T-2D/11T-2MTJ circuits. [ABSTRACT FROM AUTHOR]

The impact of transient ionizing radiation effects on a 4-Mb static random access memory (SRAM) circuit which has an input–output (IO) supply voltage and a core supply voltage was studied. The experimental results indicate that a longer time is required to restore minimal operating voltage for core supply voltage. Based on the 180-nm bulk CMOS technology, 3-D mode numerical simulations with technology computer-aided design (TCAD) show that the parasitic bipolar effect plays a significant role in discrepancy in the recovery process between supply voltages. This effect will be discussed in depth in this article, and the simulation results illustrate that the n-well contact has a great impact on the operation mode of parasitic bipolar. Meanwhile, the supply voltage disturbance mitigation methods are presented through improving power supply voltage and placing more n-well contacts. [ABSTRACT FROM AUTHOR]

This work analyzes the performance of the reduced precision redundancy (RPR) error mitigation technique using the fast Fourier transform (FFT) as a case study. To this purpose, several configurations of an FFT IP design were implemented in field-programmable gate array (FPGA) using reduced precision triple modular redundancy (RP-TMR) and tested under proton irradiation and fault injection. The cross section, the sensitivity to common-mode failures (CMFs), and the signal-to-noise ratio of these configurations were evaluated. The results of the radiation experiments and fault injection campaigns are in agreement and show that the RP-TMR technique may be used as an alternative to triple modular redundancy (TMR) if small errors can be tolerated, as it has a good performance in terms of error correction capabilities, area usage, and sensitivity to critical errors. [ABSTRACT FROM AUTHOR]

We conducted a real-time soft-error rate characterization of CMOS bulk 65-nm static random access memories (SRAMs) subjected to fusion neutrons during deuterium–deuterium (D-D) plasma operation at W–tungsten–Environment in Steady-state Tokamak (WEST). The test equipment, installed in the experimental hall at several locations of the tokamak, was irradiated during machine shots by a flux of particles dominated by primary 2.45-MeV neutrons. Real-time neutron metrology, neutron spectrometry, complementary characterization with monoenergetic neutrons, and Monte Carlo numerical simulations at both material and circuit levels have also been performed to analyze the experimental data. Our results suggest that higher energy neutrons, simultaneously produced by deuterium–tritium (D-T) reactions due to triton burn-up in the D-D plasma, play a significant role in the radiation response of SRAMs for which multiple cell upsets are detected and cannot be attributed to D-D neutrons. [ABSTRACT FROM AUTHOR]

The effects of total ionizing dose (TID) on static random access memory (SRAM) physical unclonable functions (PUFs) are studied through X-ray and proton irradiation of commercially available SRAM. Negative shifts in the fractional Hamming weight (FHW) were measured with increasing TID, indicating a migration of bistable cells toward logic low. Additionally, positive shifts in the intra-die fractional Hamming distance (FHD) were measured and indicate changes to the virtual fingerprint of an SRAM PUF with TID, especially in devices that were dosed while holding data. Shifts in inter-die FHD were negligible, allowing individual SRAMs still to be easily identified based on the FHD between a known and unknown sample even after moderate amounts of TID. In some cases, SRAMs could still be identified by their PUFs after the devices had failed. In all cases, the irradiated SRAM devices retained their virtual fingerprint after recovery through annealing. [ABSTRACT FROM AUTHOR]

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat. [ABSTRACT FROM AUTHOR]