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Block permutation and Co-XOR (BPCX) image encryption is a commonly used encryption method for reversible data hiding in the encryption domain, which can effectively improve the embedded capacity and the ability resisting the existing attacks including ciphertext-only attack and known plaintext attack (KPA). This paper proposes a KPA based on bit-block inversion and mean equivalent division (MED) to estimate the block permutation key of BPCX image encryption. Firstly, we divide an image block into the bit-block and point out that the maximum of the numbers of 0 bit and 1 bit of a bit-block before and after the Co-XOR encryption remains unchanged. And then two inversion rules of bit-block are defined to construct pseudo plain-ciphertext images to eliminate the influence of pixel value changes caused by Co-XOR encryption. Finally, the MED based KPA is designed to estimate the block permutation key sequence according to the pseudo plain-ciphertext images. The relationship between the key estimation accuracy and the number of known plain-ciphertext pairs, block size, and pseudo ciphertext are discussed. Experimental results show that even in the minimum block size (2×2), the average estimated correct rate of the block permutation sequence exceeds 40%. The block permutation key estimation accuracy is more than 50% when the block size is greater than 3×3. Some improved encryption methods against the proposed KPA are also given.

Reversible data hiding in encrypted images (RDH-EI) technology is commonly used in cloud storage images for privacy protection. Most existing RDH-EI techniques reported in the literature applied block permutation and co-modulation (BPCM) encryption to generate encrypted images. This work analyses the security of the RDH-EI algorithm based on BPCM encryption under known plaintext attack (KPA). Different from the existing KPAs, this paper considers that attackers can perform KPA based on marked encrypted images and shows that BPCM encryption has the risk of information leakage. To find the constant features of a block before and after co-modulation, the first-pixel difference block (FDB) of a block is first defined. Then, a pseudo cypher difference image of the cyphertext image is constructed to eliminate the changed FDBs so that the differences in the cyphertext FDBs are the same as the FDBs in the corresponding plaintext difference image. Finally, we design an FDB-based block permutation key estimation method according to the plaintext difference image and pseudo cyphertext difference image. The influence of block size on key estimation accuracy and the time complexity of the proposed KPA algorithm are analysed and discussed. Experimental results show that the correct rate of key estimation is positively correlated with the block size and the number of plain-cyphertext pairs. The average correct rate of key estimation reaches 63% when the block size is greater than 33.

LU factorization is extensively used in engineering and scientific computations for solution of large set of linear equations. Particularly, circuit simulators rely heavily on sparse version of LU factorization for solution involving circuit matrices. One of the recent advances in this field is exploiting the emerging computing platform of graphics processing units (GPUs) for parallel and sparse LU factorization. In this article, following contributions are made to advance the state of the art in hybrid right-looking algorithm (RLA): 1) a novel GPU kernel based on parallel column and block size optimization (PCBSO) is developed for adaptively allocating the block size while optimizing the number of columns for parallel execution based on the size of their associated submatrices at every level. The proposed approach helps to minimize the resource contention and to improve the computational performance and 2) an algorithm is developed to enable the execution of the new adaptive mode with dynamic parallelism. Also, a comprehensive performance comparison using a set of benchmark circuit examples is presented. The results indicate that, the proposed advancements can improve the results of state-of-the-art right looking sparse LU factorization in GPU by $1.54\times $ (Arithmetic Mean).

As the basis of stereo observation, epipolar resampling is a critical technology for 3D reconstruction. With the development of the 3D reconstruction using multi-view satellite images, the epipolar resampling of the multi-view satellite images has become a new challenging problem. In this paper, we propose an epipolar resampling method for multi-view high resolution satellite images based on block. Firstly, we establish the relationship between the vertical parallax and image block size for the epipolar resampling based on block. Using this relationship, we can choose the block size to limit the maximum vertical parallax in epipolar resampling. Secondly, we use the rational function model (RFM) to generate virtual corresponding points for fundamental matrix estimation, so image pairs with large stereo angles and poor consistency in multi-view satellite images which are difficult to extract feature matching point can be rectified. Experiments with multi-view satellite images demonstrated the universality and effectiveness of the proposed method. All the image pairs in the multi-view satellite image dataset were rectified successfully. The average epipolar resampling error is only 0.25 pixels when we rectify the multi-view satellite images acquired by WorldView-3 with the block size of 3000*3000 pixels, significantly less than the similar method.

In a video-on-demand (VoD) service, blockbuster videos have stable and predictable popularity, but the traffic can vary significantly within short timescale. To efficiently serve the user pool in a geographic region, we consider a regional auto-scaling cloud-based data center consisting of multiple servers. For efficient storage, we partition the videos into fixed-size blocks. To respond to dynamic user traffic in a timely and cost-effective manner, we may activate or deactivate each server according to the traffic while keeping at least one replica for each block in the active servers. We maximize the user capacity of the active servers (and hence minimizing the number of active servers at any time) by jointly optimizing block allocation in the servers, server selection at each traffic level, and request dispatching to a server. We believe that this is the first work to study such problem for an auto-scaling cloud-based VoD data center. We first formulate the problem and show its NP-hardness. We then propose AVARDO ( A uto-scaling V ideo A llocation and R equest D istribution O ptimization), a simple but efficient approximation algorithm with proven optimality. AVARDO operates the servers like a stack, with a server being pushed into or popped from the existing active server set according to some optimized traffic thresholds. We prove that AVARDO approaches the theoretical optimum as the block size reduces. Trace-driven experimental results based on large-scale real-world video data further validate that AVARDO is closely optimal. It achieves significantly higher user capacity as compared with other state-of-the-art and traditional schemes, and reduces the optimality gap by multiple times.

Recovery of an unknown sparse signal from a few of its projections is the key objective of compressed sensing. Often one comes across signals that are not ordinarily sparse but are sparse blockwise. Existing block sparse recovery algorithms like BOMP make the assumption of uniform block size and known block boundaries, which are, however, not very practical in many applications. This paper addresses this problem and proposes a two step procedure, where the first stage is a coarse block location identification stage while the second stage carries out finer localization of a non-zero cluster within the window selected in the first stage. A detailed convergence analysis of the proposed algorithm is carried out by first defining the so-called pseudoblock-interleaved block RIP of the given generalized block sparse signal and then imposing upper bounds on the corresponding RIC. We also extend the analysis for complex vector as well as matrix entries where it turns out that the extension is non-trivial and requires special care. Furthermore, assuming real Gaussian sensing matrix entries, we find a lower bound on the probability that the derived recovery bounds are satisfied. The lower bound suggests that there are sets of parameters such that the derived bound is satisfied with high probability. Simulation results confirm significantly improved performance of the proposed algorithm as compared to BOMP., 18 pages, 5 figures

Convolutional Neural Networks (CNN) are widely used in different artificial intelligence (AI) applications. Major part of the computation of a CNN involves 2D convolution. In this paper, we propose novel fast convolution algorithms for both 1D and 2D to remove the redundant multiplication operations in convolution computations at the cost of controlled increase of addition operations. For example, when the 2D processing block size is 3×3, our algorithm has multiplication saving factor as high as 3.24, compared to direct 2D convolution computation scheme. The proposed algorithm can also process input feature maps and generate output feature maps with the same flexible block sizes that are independent of convolution weight kernel size. The memory access efficiency is also largely improved by the proposed method. These structures can be applied to different CNN layers, such as convolution with stride > 1, pooling and deconvolution by exploring flexible feature map processing tile sizes. The proposed algorithm is suitable for both software and hardware implementation.

In this article, with the rapid development of industrial Internet of Things, a large number of embedded devices, such as sensors and tag readers, have been widely deployed for gathering and sending data. These devices are commonly unreliable and vulnerable to many threats, because they are located in unattended areas which are vulnerable to device capture attacks. Such environments can be regarded as white-box attack contexts, in which the adversary has total visibility and full control of the implementations. White-box cryptography (WBC) aims to protect implementations of symmetric encryption algorithms in white-box attack contexts. Unfortunately, existing WBC schemes are vulnerable to various attacks, and most of them are insufficiently secure in strict white-box attack contexts. Based on the investigation of existing designs and the corresponding cryptanalysis, we propose a novel design approach for securing WBC schemes, which is named state-dependent selectable random substitutions (SDSRS). It uses SDSRSs to defeat various related white-box cryptanalytic approaches. With special considerations for IIoT systems, such as high performance for supporting real-time applications and small block size for fitting industrial protocols, a concrete WBC scheme designed with the proposed approach has been provided. Our theoretical analysis shows that the proposed scheme is secure. Additionally, experimental results indicate that the scheme performs well in practice, and it is significantly efficient in time and energy consumptions compared with existing secure white-box cryptographic schemes.

Recently, reversible data hiding in encrypted compressed images (RDHECI) has attracted more attention due to privacy information protection concerns. Meanwhile, AMBTC as one technique of lossy image compression that has lower storage costs and the simplicity in computation and is extensively used in many applications. Hence, this paper proposes an RDHECI scheme based on AMBTC, named O-AMBTC, to address privacy concerns. First, the original image is scrambled in a block-wise manner to generate the scrambled image which then is compressed by an AMBTC compression technique. Subsequently, the derived AMBTC compression codes are encrypted by using the methods of value modulation and stream cipher while the correlations between two quantization levels of AMBTC compression codes are retained and exploited to vacate redundant room to embed secret messages. Data hiding is then performed with the use of PBTL labeling strategy. In addition, another modified AMBTC compression code based RDHECI scheme, called M-AMBTC, is suggested to increase the ability to carry secret messages. In our dual approach, both the AMBTC-compressed image and the secret messages can be correctly recovered. Experimental results show that two proposed schemes are able to achieve average embedding rates as large as 0.6 bpp and 0.8 bpp when the block size is set to $2\times 2$ , respectively.

QARMA is a new tweakable block cipher used for memory encryption, the generation of short tags and the construction of the keyed hash functions in future. It adopts a three-round Even-Mansour scheme and supports 64 and 128 bits of block size, denoted by QARMA-64 and QARMA-128, respectively. Their tweak lengths equal the block sizes and their keys are twice as long as the blocks. In this paper, we improve the security analysis of reduced-version QARMA against impossible differential and meet-in-the-middle attacks. Specifically, first exploit some properties of its linear operations and the redundancy of key schedule. Based on them, we propose impossible differential attacks on 11-round QARMA-64/128, and meet-in-the-middle attacks on 10-round symmetric QARMA-128 and the last 12 rounds of asymmetric QARMA-128. Compared with the previously best known results on QARMA-64, our attack can recover 16 more bits of master key with the almost complexities. Compared with the previously best known results on symmetric QARMA-128, the memory complexity of our attack in Section IV is reduced by a factor of 248. Moreover, the meet-in-the-middle attack on 12-round QARMA-128 is the best known attack on QARMA-128 in terms of the number of rounds.

Offset codebook or ${\mathsf {OCB}}$ mode is a popular block cipher mode of operation for authenticated encryption. The latest version of this cipher, called ${\mathsf {OCB3}}$ , is one of the finalists in CAESAR. In this paper, we explore the scope of random read access and out-of-sequence decryption in ${\mathsf {OCB}}$ . We observe that the current versions of ${\mathsf {OCB}}$ are inefficient in this respect owing to the ineptness of the underlying mask generating function (MGF). We propose new candidates for MGF based on ${\mathsf {AES}}$ round function, which are efficient in direct computation and provide comparable performance in the usual setting. Our schemes are not the obvious choices for MGF in conventional sense as they do not have optimal almost XOR universal (AXU) bound. In existing ${\mathsf {OCB}}$ designs, the MGFs are required to have $ 2^{-n} $ , i.e. optimal, AXU bound in order to upper bound the distinguishing advantage to $ O(\sigma ^{2}/2^{n}) $ , where $ n $ is the block size of the underlying block cipher and $ \sigma $ is the total number of blocks among all queries. We find this specific requirement too restrictive. We abstract the ${\mathsf {OCB}}$ design, termed as ${\mathsf {GOCB}}$ , to look into the universal notion required from the underlying MGF. We propose a relaxed notion of AXU, called locally imperfect XOR universal (LIXU) hash, which can be of independent interest. Using LIXU as the underlying MGF, we recover reasonable security bounds for our schemes.

We consider the problem of recovering a signal $ \mathbf {x^{*}}\in \mathbb {R}^{n}$ , from magnitude-only measurements, $y_{i} = \left |{ \left \langle{ { \mathbf {a}_{i}}, \mathbf {x^{*}} }\right \rangle }\right | $ for $i=\{1,2,\ldots ,m\}$ . This is a stylized version of the classical phase retrieval problem , and is a fundamental challenge in nano- and bio-imaging systems, astronomical imaging, and speech processing. It is well-known that the above problem is ill-posed, and therefore some additional assumptions on the signal and/or the measurements are necessary. In this paper, we consider the case where the underlying signal $ \mathbf {x^{*}}$ is $s$ -sparse. For this case, we develop a novel recovery algorithm that we call Compressive Phase Retrieval with Alternating Minimization , or CoPRAM . Our algorithm is simple and is obtained via a natural combination of the classical alternating minimization approach for phase retrieval with the CoSaMP algorithm for sparse recovery. Despite its simplicity, we prove that our algorithm achieves a sample complexity of $ \mathcal {O}\left ({{s^{2} \log n}}\right )$ with Gaussian measurements $ { \mathbf {a}_{i}}$ , which matches the best known existing results; moreover, it also demonstrates linear convergence in theory and practice. An appealing feature of our algorithm is that it requires no extra tuning parameters other than the signal sparsity level $s$ . Moreover, we show that our algorithm is robust to noise. The quadratic dependence of sample complexity on the sparsity level is sub-optimal, and we demonstrate how to alleviate this via additional assumptions beyond sparsity. First, we study the (practically) relevant case where the sorted coefficients of the underlying sparse signal exhibit a power law decay. In this scenario, we show that the CoPRAM algorithm achieves a sample complexity of $ \mathcal {O}\left ({{s \log n}}\right )$ , which is close to the information-theoretic limit. We then consider the case where the underlying signal $ \mathbf {x^{*}}$ arises from structured sparsity models. We specifically examine the case of block-sparse signals with uniform block size of $b$ and block sparsity $k=s/b$ . For this problem, we design a recovery algorithm that we call Block CoPRAM that further reduces the sample complexity to $ \mathcal {O}\left ({{ks \log n}}\right )$ . For sufficiently large block lengths of $b=\Theta (s)$ , this bound equates to $ \mathcal {O}\left ({{s \log n}}\right )$ . To our knowledge, our approach constitutes the first family of linearly convergent algorithms for signal recovery from magnitude-only Gaussian measurements that exhibit a sub-quadratic dependence on the signal sparsity level.

For the detection of median filtering (MF) forensics, this paper proposes the feature vector extracted from the bit-planes slicing of the forged image. The assembled feature vector is trained in a support vector machine (SVM) classifier for the MF detection (MFD) of the forged images. The performance of the proposed MFD scheme is measured with several types of forged images: unaltered, Gaussian filtering (3 × 3), averaging filtering (3 × 3), downscaling (0.9), upscaling (1.1), and post-frame-up, respectively, in a block size 32 × 32 and 64 × 64 pixels. Subsequently, in experimental items, a classification ratio, Area Under the Curve (AUC), PTP at PFP = 0.01, and Pe (a minimum average decision error) are estimated. The result in terms of AUC shows that the estimation of the proposed MFD scheme is graded as `Excellent (A)'.

Our approach to contrast enhancement (CE) of images is based on natural scene statistics (NSS). We show, in this paper, that the average intensity distribution of natural images can be linearly approximated to the ramp distribution in an ordered histogram domain as the contrast increases. Based on this finding, we propose ramp distribution-based global and local CE algorithms. The ramp distribution-based slant thresholding (RDST) algorithm is proposed as a global CE method which uses slant thresholding in an ordered histogram domain to yield a contrast-enhanced image. Also, the ramp distribution-based adaptive slant thresholding (RDAST) algorithm is proposed as a local CE method. It adaptively adjusts a slant angle of the ramp distribution in each block to suppress noise amplification in uniform regions and maximizes contrast in non-uniform regions. The RDAST also employs a scaled global modified histogram to minimize sensitivity to block size changes. Moreover, we propose a metric to measure the amount of over-contrast in an image to evaluate all CE algorithms more correctly. The experimental results show that the proposed algorithms have better or competitive performance as well as computational efficiency.

The rate of a network code is the ratio of the block size of the network's messages to that of its edge codewords. We compare the linear capacities and achievable rate regions of networks using finite field alphabets to the more general cases of arbitrary ring and module alphabets. For non-commutative rings, two-sided linearity is allowed. Specifically, we prove the following for directed acyclic networks: (i) The linear rate region and the linear capacity of any network over a finite field depend only on the characteristic of the field. Furthermore, any two fields with different characteristics yield different linear capacities for at least one network. (ii) Whenever the characteristic of a given finite field divides the size of a given finite ring, each network's linear rate region over the ring is contained in its linear rate region over the field. Thus, any network's linear capacity over a field is at least its linear capacity over any other ring of the same size. An analogous result also holds for linear network codes over module alphabets. (iii) Whenever the characteristic of a given finite field does not divide the size of a given finite ring, there is some network whose linear capacity over the ring is strictly greater than its linear capacity over the field. Thus, for any finite field, there always exist rings over which some networks have higher linear capacities than over the field., Comment: Submitted to IEEE Transactions on Information Theory June 4th, 2017 Revised January 29th, 2018

This paper first introduces a parametric binary tree labeling scheme (PBTL) to label image pixels in two different categories. Using PBTL, a data embedding method (PBTL–DE) is proposed to embed secret data to an image by exploiting spatial redundancy within small image blocks. We then apply PBTL–DE into the encrypted domain and propose a PBTL-based reversible data hiding method in encrypted images (PBTL–RDHEI). PBTL–RDHEI is a separable and reversible method that both the original image and secret data can be recovered and extracted losslessly and independently. Experiment results and analysis show that PBTL–RDHEI is able to achieve an average embedding rate as large as 1.752 bpp and 2.003 bpp when block size is set to $2\times 2$ and $3\times 3$ , respectively.

In this paper, a joint compression-encryption and symbol scrambling scheme is proposed for orthogonal frequency-division multiplexing (OFDM) systems for image date. First, in the compression-encryption phase, the original image data is fist divided into sub-blocks and then an secure image block compressive sensing (BCS) is applied to resulting image data, in which a chaotic sparse basis matrix and a chaotic measurement matrix based on the discrete cosine transform (DCT) are used. Secondly, the resulting secure CS data is transform into binary phase shift keying (BPSK) symbols and then a chaotic scrambling operation is applied to the obtained BPSK symbols. The simulation results show that the proposed secure BCS scheme can achieve better peak signal-to-nose ratio (PSNR) performance than that of the conventional chaotic measurement method. The simulation results also show that a good trade-off performance of signals between PSNR and computational complexity can be achieved when the proper sub block size of image is adopted. In addition, the performances of the BPSK OFDM signal, which is generated from the secure BCS of the image, are evaluated over AWGN and multipath fading channels. The simulation results show that the proposed scheme not only achieve effective secure block compressive sensing and achieve secure transmission in physical layer. The security of the transmitted image data is enhanced by the joint compression-encryption and symbol scrambling.

This paper investigates and presents a block-based opto-color cipher using double random phase encoding (DRPE) with different block sizes. The color plainimage is divided into equal-sized blocks and then converted to an optical signal by an optical emitter. The obtained optical signal is encrypted by employing the DRPE technique, which applies two types of phase modulation, time, and Fourier domains. Finally, the optical color cipherimage is, upon detection, converted to digital format by a charge-coupled device digital camera. Experiments and security analysis show that the proposed block-based optical color image cipher using DRPE with increased block size is secure, effective, and including a good immunity to channel noise.

DBlock is a new family of block ciphers proposed by Wu et al. in Science China in 2015, which consists of three variants specified as DBlock-128/192/256. DBlock-n employs a 20-round Feistel-type structure with n-bit block size and n-bit key size. We propose the first fault analysis on DBlock and show that no more than 2 pairs of correct/faulty ciphertexts are needed to retrieve the master key. In the attack, a byte-oriented fault is injected in round 16, and three properties including diffierential distribution of the Sbox, bijection nature of the linear function and Feistel-type key scheduling are fully utilized to distinguish between the correct and wrong keys. A fault position guessing strategy based on known intermediates is adopted, which efficiently makes the known-fault attack apply to the random fault model. The experimental results show that, with a pair of ciphertexts, 11.820-bit exhaustive search is needed to derive the whole 128-bit key on average. With 2 pairs of ciphertexts, the unique key can be determined within 6.5 minutes.

The effectiveness of Machine Learning (ML) methods depend on access to large suitable datasets. In this article, we present how we build the LS-CAT (Large-Scale CUDA AutoTuning) dataset sourced from GitHub for the purpose of training NLP-based ML models. Our dataset includes 19 683 CUDA kernels focused on linear algebra. In addition to the CUDA codes, our LS-CAT dataset contains 5 028 536 associated runtimes, with different combinations of kernels, block sizes and matrix sizes. The runtime are GPU benchmarks on both Nvidia GTX 980 and Nvidia T4 systems. This information creates a foundation upon which NLP-based models can find correlations between source-code features and optimal choice of thread block sizes. There are several results that can be drawn out of our LS-CAT database. E.g., our experimental results show that an optimal choice in thread block size can gain an average of 6% for the average case. We thus also analyze how much performance increase can be achieved in general, finding that in 10% of the cases more than 20% performance increase can be achieved by using the optimal block. A description of current and future work is also included.

The characteristic basis function method (CBFM) was developed as an algorithm to accelerate the analysis based on direct matrix solver. In CBFM, the optimum block size greatly influences the overall analysis time. In this paper, we propose a guideline for setting the optimal block size that can be applied to every algorithm based on CBFM. Rough estimation of the optimal block size is $L_{B}^{rough} \approx 0.05 N^{6/{29}}$ , and the exact optimal block size can be determined through preprocessing based on rough estimation. Numerical results of electromagnetic scattering problems are shown to demonstrate the performance of the proposed method.

High memory/storage complexity poses severe challenges to achieving high throughput and high energy efficiency in discrete 2-D FIR filtering. This performance bottleneck is especially acute for embedded image or video applications, that use 2-D FIR processing extensively, because real-time processing and low power consumption are their paramount design objectives. Fortunately, most of such perception-based embedded applications possess so-called “inherent fault tolerance”, meaning slight computing accuracy degradation has a little negative effect on their quality of results, but has significant implication to their throughput, hardware implementation cost, and energy efficiency. This paper develops a novel stochastic-based 2-D FIR filtering architecture that exploits the well-known probabilistic convolution theorem to achieve both low hardware cost and high energy efficiency while achieving very high throughput and computing robustness. Our ASIC synthesis results show that stochastic-based architecture achieves $L$ outputs per cycle with 97 and 81 percent less area-delay-product (ADP), and 77 and 67 percent less power consumption compared with the conventional structure and recently published state-of-the-art architecture, respectively, when the 2-D FIR filter size is $4 \times 4$ , the input block size is $L=4$ , and the image size is $512 \times 512$ .

This paper presents an efficient implementation of elliptic curve cryptography (ECC) over the National Institute of Standards and Technology (NIST) K-233 curve for 8-bit AVR microcontrollers commonly used for sensor nodes in wireless sensor networks. Until now, several ECC implementations over NIST-compliant curves have been presented on 8-bit sensor nodes. However, most of them do not provide 112-bit security level currently recommended by NIST. Although some works provide more than 112-bit security level, their performance needs to be improved in order to be executed properly on resource-constrained sensor nodes. For optimizing the performance of ECC, we focus on the efficiency of field arithmetics and propose several optimization techniques. First, we present a novel polynomial multiplication technique based on multiplier encoding. The proposed method significantly reduces the required number of registers for a multiplier, which allows the larger block size for the Karatsuba Block-Comb method. The proposed method provides around 17.05% of improvement compared with the best result previously presented. Second, we optimize modular squaring and reduction algorithms considering the features of 8-bit AVR, and each of them provides around 21.86% and 3.7% improvements compared with the related works. With proposed methods, we present two versions of ECC implementation: (highly fast) $HF$ and (highly secure) $HS$ over NIST K-233 curve on an 8-bit ATmega128. Especially, $HF$ version outperforms the best result previously implemented on the same curve by 18.6% and 34.5% for a variable and a fixed-based scalar multiplication, respectively. Furthermore, on the 8-bit AVR platform, our ECC implementation shows the best performance compared with other existing implementations over both NIST-standardized prime or binary curves.

The design of modern architectures with reduced capacity is an important challenge that electronics and computer engineers face. A modern architecture has been proposed for MMF2 encryption algorithm in this paper to reduce the occupied gate level. The algorithm uses an input block size of 64 b, an initiation key of 128 b with nine repetitions. The obtained results indicate to GE16023 decreasing in the hardware cost. The Verilog hardware language description language and QUARTUSII software have been used for simulation. The effectiveness of the method has been proven to be effective in the production of chips from CYCLONEII generation in 0.13- $\mu \text{m}$ CMOS technology.

Differential fault analysis of stream ciphers, such as Grain (Grain v1 and Grain-128) has been an active area of research. Several countermeasures to thwart such analysis have been also proposed in the related cryptographic literature. In this paper, we demonstrate a novel combination of power and fault analysis strategies to devise attacks against such protected implementations of Grain stream cipher. We considered clock glitch induced faults occurring in practice to construct our fault model. In addition, we developed a generic power analysis attack technique against the Grain family of stream ciphers assuming that the cipher implementation can be resynchronized multiple times with a fixed secret key and any randomly generated initialization vector. Subsequently, we combine our proposed power analysis strategy with the notion of the practically occurring faults to mount attacks on various fault attack countermeasures. In order to validate our proposed power analysis attack, we report the results of power trace classifications of a Grain v1 implementation on SASEBO-GII board. The captured power traces were analyzed using least squares support vector machine learning algorithm-based multiclass classifiers to segregate the power traces into the respective Hamming distance (HD) classes. To extract power samples with high information about HD classes, signal-to-noise ratio (SNR) metric was chosen for feature selection. The experimental results of power trace classifications of test set showed success rate as high as 92.5% when the seven largest SNR sample instants over a clock cycle were chosen as features along with a suitable kernel hyperparameter combination.

In compressive sensing (CS) of images or videos, a block-based sensing or recovery scheme can facilitate low-cost sampling or recovery in memory and computation. However, its recovery with small block size and small subrate suffers greatly from its lack of information of the measurement data essential to recover a unique solution among many candidates. This study, based on prior knowledge of the signal to be sensed, namely, the relative magnitude difference of signal entries, designs a weighting process to limit the solution space of the recovered signal and combines it with much simplified Landweber iterations to deliver a complete recovery algorithm, called iterative weighted recovery (IWR). We theoretically verify the performance of the proposed IWR, including error bound, convergence rate, and stopping criterion. Application of the proposed IWR to block-based CS of images or videos confirms the quality improvement of the recovered images or videos and reduction of recovery time.

The block-based analysis for tamper localization is a prevailing mechanism in hash-based forgery detection algorithm. One of the main problems with a block-based analysis is its rough localization stemming from the demand to use relatively large blocks to reduce hash length. While decreasing the block size can improve the localization resolution, the hash length tends to become too long to be practical. In this paper, we propose a binary ranking hashing approach that satisfies both the requirements of compact hash length and small block size, to obtain a binary map combined with spatial information. Meanwhile, we investigate a multiscale difference map fusion approach that fuses multiple candidate difference maps, resulting from the analysis of the subtraction between two binary maps with different sliding windows, to obtain a single, more reliable tampering map with better localization resolution. We use manifold ranking to model this multiscale difference map fusion problem and propose a two-stage scheme, namely, ranking with tampering queries and nontampering queries. Our results indicate that the proposed tamper detection method can improve the tamper localization resolution compared with state-of-the-art methods.

In deep sub-micron region, spin transfer torque RAM (STT-RAM) shows read-disturbance error (RDE) which presents a crucial reliability challenge. We present SHIELD, a technique to mitigate RDE in STT-RAM last level caches (LLCs). SHIELD uses data compression to reduce cache-write traffic and restore requirement. Also, SHIELD keeps two copies of data blocks compressed to less than half the block size and since several LLC blocks are only accessed once, this approach avoids several restore operations. SHIELD consumes smaller energy than two previous RDE-mitigation techniques, namely high-current restore required read (HCRR, also called restore-after-read) and low-current long latency read (LCLL) and even an ideal RDE-free STT-RAM cache .

Video compression has become more and more important nowadays along with the increasing application of video sequences and rapidly growing resolution of them. H.264 is a widely applied video coding standard for academic and commercial purposes. And fractal theory is one of the most active branches in modern mathematics, which has shown a great potential in compression. In this paper, this study proposes an improved inter prediction algorithm for video coding based on fractal theory and H.264. This study take the same approach to make intra predictions as H.264 and this study adopt the fractal theory to make inter predictions. Some improvements are introduced in this algorithm. First, luminance and chrominance components are coded separately and the partitions are no longer associated as in H.264. Second, the partition mode for chrominance components has been changed and the block size now rages from $16\times 16$ to $4\times 4$ , which is the same as luminance components. Third, this study introduced adaptive quantization parameter offset, changing the offset for every frame in the quantization process to acquire better reconstructed image. Comparison between the improved algorithm, the original fractal compress algorithm and JM19.0 (The latest H.264/AVC reference software) confirms a slightly increase in Peak Signal-to-Noise Ratio, a significant decrease in bitrate while the time consumed for compression remains less than 60% of that using JM19.0.

Silicon physical unclonable functions (PUFs) produce a sequence of response bits from chip-unique manufacturing variations. Since the response bits are physically derived, there is noise present. To generate bit-exact cryptographic keys, error correction algorithms are used. The error correction is typically split into small processing blocks to reduce implementation complexity. The reliability of PUF responses varies from bit to bit, but there has been very little work so far that mathematically analyzes the effect of the block size on the reliability of PUF response sequences. We use the information theoretical concept of typicality to show that the probability of drawing an unreliable sequence decreases exponentially with the block size. We present differential sequence coding that scales efficiently across larger block sizes without having the super-linear increase in decoding complexity of prior approaches. It scans the entire PUF response sequentially and then only operates on one single, maximally reliable, block to generate the cryptographic key. Our sample FPGA implementation with a convolutional code is designed for a popular SRAM PUF scenario. It generates a 128-bit key for an average input bit error probability of 15% with an output bit error probability of $6.14 \cdot 10^{-9}$ and only uses 974 PUF bits and 1, 108 helper data bits. There are 36% less PUF bits and 71% less helper data bits than the best previous individual results in both criteria without increasing the implementation size of the key generation module noticeably.

Signal subspace identification provides a performance improvement in hyperspectral applications, such as target detection, spectral unmixing, and classification. The HySime method is a well-known unsupervised approach for hyperspectral signal subspace identification. It computes the estimated noise and signal correlation matrices from which a subset of eigenvectors is selected to best represent the signal subspace in the least square sense. Depending on the complexity and dimensionality of the hyperspectral scene, the HySime algorithm may be computationally expensive. In this paper, we propose a massively parallel design of the HySime method for acceleration on NVIDIA's graphics processing units (GPUs). Our pure GPU-based implementation includes the optimal use of the page-locked host memory, block size, and the number of registers per thread. The proposed implementation was validated in terms of accuracy and performance using the NASA AVIRIS hyperspectral data. The benchmark with the NVIDIA GeForce GTX 580 and Tesla K20 GPUs shows significant speedups with regards to the optimized CPU-based serial counterpart. This new fast implementation of the HySime method demonstrates good potential for real-time hyperspectral applications.

Fingerprint features can be divided into three major categories based on the granularity at which they are extracted: level 1, level 2, and level 3 features. Orientation field, ridge frequency field, and minutiae set are three fundamental components of fingerprint, where the orientation field and ridge frequency field are regarded as level 1 features and minutiae set as level 2 features. It is generally believed that level 1 features, especially orientation field, can be reconstructed from level 2 features, i.e., minutiae. However, it is still a question that if minutiae can be extracted from level 1 features. In this paper, we analyze the relations between level 1 and level 2 features using the frequency modulation (FM) model and propose an approach to extract minutiae from level 1 features (i.e., orientation field and frequency field). The proposed algorithm is evaluated on NIST SD27 and FVC2002 DB1 databases. The true detection rate (TDR) and false detection rate (FDR) of minutiae detection on NIST SD27 and FVC2002 DB1 are about 45% and 30% compared with manually marked minutiae, respectively, with level 1 features extracted at a block size of 16 pixels. When pixelwise orientation and frequency fields are available, TDR and FDR can reach 70% and 25%, respectively. With a smaller block size, the minutiae recovering accuracy can be even higher. Our quantitative and experimental results show the deep relationship between level 1 and level 2 features of a fingerprint.

Extensive work has been done in the performance evaluation of delay-/disruption-tolerant networking (DTN) technologies in cislunar and deep-space communications using simulation or emulation file transfer experiments. However, little work has been seen for studying in an analytical manner the performance of DTN protocols for space communications characterized by asymmetric channel rates. Accurate estimate of file delivery latency [i.e., round trip time (RTT)] is essential for efficient transmission control, reliable delivery, and bandwidth usage optimization of a protocol. In this paper, we present a performance analysis of the main DTN convergence layer adapter (CLA), i.e., Licklider transmission protocol (LTP) CLA (LTPCL adapter), over cislunar space channels, focusing on RTT estimates, in the presence of asymmetric channel rates. Analytical models are built for the RTT estimate of LTPCL transmissions with the effect of delay caused by space channel-rate asymmetry, channel impairment, and link disruption taken into consideration. The models are validated by file transfer experiments using a PC-based test bed. It is found that a smaller LTP data block size results in a longer delay in acknowledgement (ACK) transmission and thus a longer RTT. With a block size equal to or larger than a calculated threshold size, the ACK delay is avoided; thus, their RTT is consistently very low, leading to significantly shorter file delivery time and goodput advantage.

In this paper, we analyze the contents of lookup tables (LUTs) of distributed arithmetic (DA)-based block least mean square (BLMS) adaptive filter (ADF) and based on that we propose intra-iteration LUT sharing to reduce its hardware resources, energy consumption, and iteration period. The proposed LUT optimization scheme offers a saving of 60% LUT content for block size 8 and still higher saving for larger block sizes over the conventional design approach. We also present here the design of a register-based LUT matrix for maximal sharing of LUT contents and full-parallel LUT-update operation. Based on the proposed design approach, we have derived a DA-based architecture for the BLMS ADF, which is scalable for larger block sizes as well as higher filter lengths. We find that the hardware complexity of the proposed structure increases less than proportionately with input block size and filter length. It offers a saving of 60% LUT-update per output and 59% LUT access per output over the recently proposed DA-based BLMS ADF structure for block size 8 and filter length 64. Besides, the proposed structure involves nearly 30% saving in the iteration period over the other for 16-bit coefficient word length. Application specific integrated circuit (ASIC) synthesis result shows that the proposed structure for block size 8 offers a saving of 48% area-delay product (ADP) and 53% energy per sample (EPS) over the existing DA-based BLMS ADF structure on average for different filter lengths, and offers 30% higher sampling rate due to its shorter iteration period. Compared with the existing DA-based LMS ADF structure, the proposed structure involves 68% less ADP and $1.6 \times $ less EPS.

Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration does not directly support the block processing unlike direct-form configuration. In this paper, we explore the possibility of realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters for both fixed and reconfigurable applications. Based on a detailed computational analysis of transpose form configuration of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose form FIR filter. We have derived a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A low-complexity design using the MCM scheme is also presented for the block implementation of fixed FIR filters. The proposed structure involves significantly less area-delay product (ADP) and less energy per sample (EPS) than the existing block implementation of direct-form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure. Application-specific integrated circuit synthesis result shows that the proposed structure for block size 4 and filter length 64 involves 42% less ADP and 40% less EPS than the best available FIR filter structure proposed for reconfigurable applications. For the same filter length and the same block size, the proposed structure involves 13% less ADP and 12.8% less EPS than that of the existing direct-form block FIR structure.

Vector orthogonal frequency-division multiplexing (V-OFDM) for single-transmit-antenna systems is a generalization of OFDM where single-carrier frequency-domain equalization and OFDM are just two special cases. Phase noise in a V-OFDM system leads to a common vector block phase error (CVBPE) and an intervector block carrier interference effect. Severe performance degradation may occur if these two effects are not estimated and compensated well. In this paper, blind and semiblind phase noise estimation and compensation in a V-OFDM system is investigated by using the expectation-maximization (EM) algorithm. This is motivated by the fact that the conventional frequency-domain phase noise suppression schemes based on pilot-aided common phase error (CPE) or CVBPE estimation and compensation are not spectrally efficient as the vector block size is increased. Two novel schemes are proposed: One estimates the CVBPE only, and the other estimates the entire phase noise sequence in the time domain. General closed-form formulas for the maximization step of the EM algorithm for the two schemes are derived, and their computational complexity values are analyzed. The performances of the two schemes are investigated by using linear-minimum-mean-square-error (LMMSE) receivers. Simulations show that the two proposed schemes are very effective in estimating and compensating for phase noise in V-OFDM systems. It turns out that the second proposed scheme not only outperforms the traditional CPE or CVBPE schemes but is computationally efficient as well when applied to V-OFDM systems.

Conventional inverse synthetic aperture radar observes the target from one viewing direction and only obtains partial information. By using a distributed multiple-input multiple-output (MIMO) array, the target can be observed from multiple views and a better image can be obtained. The distributed MIMO radar imaging signal model is derived in this paper. Because the strong scatterers (scattering centers) of a target are usually sparsely distributed, a sparse signal recovery algorithm using homotopy between the l 1 norm and l 0 norm applicable to complex signals is proposed to recover the strong scatterers. This l 1 norm and l 0 norm homotopy method is then extended to the block sparse signal case. The equivalence between complex l 1 l 0 norms homotopy method and block size of two real l 1 l 0 norms homotopy method is demonstrated. This proves that a complex signal-based algorithm is better than a real signal-based algorithm, which only separates the complex signal into its real part and imagery part and does not use their block property. This method is compared with other methods, i.e., block orthogonal matching pursuit (BOMP), block CoSaMp, block smoothed l 0 norm based method (BSL0), spectral projected gradient (SPG L1), and block sparse Bayesian learning (BSBL). The signal recovery performance of l 1 l 0 norms homotopy method is better than the other methods except for BSBL. However, BSBL costs more computationally. Imaging using distributed MIMO antennas is simulated. The simulation results show that the image quality using distributed MIMO radar is better than that using monostatic (or bistatic) MIMO radar.

In this paper we present a linear optimization model for choosing parameters in the Time Memory Trade Off method (TMTO). The restrictions of the given model are oriented to achieve a feasible TMTO for maximum time and memory given. Experiments confirmed that the proposed scheme determines the parameters in order to get high probability to invert a one-way function. The method can also be applied for combinations of time and memory not included in the reviewed literature.

In this paper, we present a framework for biclique cryptanalysis of block ciphers which extremely requires a low amount of data. To that end, we enjoy a new representation of biclique attack based on a new concept of cutset that describes our attack more clearly. Then, an algorithm for choosing two differential characteristics is presented to simultaneously minimize the data complexity and control the computational complexity. Then, we characterize those block ciphers that are vulnerable to this technique and among them, we apply this attack on lightweight block ciphers Piccolo-80, Piccolo-128, and HIGHT. The data complexity of these attacks is only 16-plaintext-ciphertext pairs, which is considerably less than the existing cryptanalytic results. In all the attacks, the computational complexity remains the same as the previous ones or even it is slightly improved.

A new cryptographic suite (CS) for mutual authentication is proposed on the basis of the next Electronic Product Code Class-1 Generation-2 (C1G2) standard. The Advanced Encryption Standard cryptographic algorithm with a block size of 128-b is used, and a modified output-feedback mode is applied for generating a key, encrypting data, and decrypting data. As a result, the proposed mutual authentication has fast processing speed. To install this CS into the CMOS passive tag, several low-power design techniques are utilized for the digital processor. The fully integrated CMOS security-enhanced passive (SEP) tag is designed and implemented with the Tower 0.18- μm CMOS process. Regardless of secure level on radio-frequency-identification communications, the CMOS SEP tag intercommunicates with the SEP interrogator emulator under a long identification range. In the measured results, the CMOS SEP tag has sensitivities of -12.0 and - 11.6-dBm in insecure and secure communications, respectively. Moreover, it takes a short time of around 40 ms to mutually authenticate a couple of tag and interrogator. Therefore, it is expected to take roughly 1 s for mutual authentications between 25 tags and 1 interrogator.

Through-silicon via (TSV) is a vertical channel that passes through a chip to connect stacked dies in 3-D packaging. Void may be produced during the high aspect ratio TSV filling process with copper electroplating method. Therefore, void detection becomes an important aspect for high-quality TSV devices. In this paper, a rapid void detection method using a single 2-D X-ray imaging was developed. An image processing method was used to divide the X-ray image into some small blocks for multithreshold image cutting and feature extraction. An artificial neural network was then used to find and locate the blocks that contain voids. The effects of segmentation threshold, various block widths, and heights were studied; a block size of 30 × 40 pixels (width × height) is recommended. The void detection is more sensitive to block width than height. Experiments show that the method proposed in this paper can automatically and rapidly detect voids in TSVs using one 2-D X-ray image.

In this paper, the block processing of a discrete-time (DT) improper-complex second-order cyclostationary (SOCS) random process is considered. In particular, it is of interest to find a preprocessing operation that enables the adoption of conventional signal processing techniques and algorithms developed for the filtering of proper-complex signals and that leads to computationally efficient near-optimal postprocessing. An invertible linear-conjugate linear (LCL) operator named the DT frequency shift (FRESH) properizer is first proposed. It is shown that the DT FRESH properizer converts a DT improper-complex SOCS random process input to an equivalent DT proper-complex SOCS random process output by utilizing the information only about the cycle period of the input. An invertible LCL block processing operator named the asymptotic FRESH properizer is then proposed that mimics the operation of the DT FRESH properizer but processes a finite number of consecutive samples of a DT improper-complex SOCS random process. It is shown that the output of the asymptotic FRESH properizer is not proper but asymptotically proper and that its frequency-domain covariance matrix converges to a highly structured block matrix with diagonal blocks as the block size tends to infinity. Two representative estimation and detection problems are presented to demonstrate that asymptotically optimal low-complexity postprocessors can be easily designed by exploiting these asymptotic second-order properties of the output of the asymptotic FRESH properizer.

Through-silicon via (TSV) is a vertical channel that passes through a chip to connect stacked dies in 3-D packaging. Voids may be produced during via filling; therefore, void detection is important for improving the quality of TSV devices. In this paper, a rapid void detection method using a single 2-D X-ray imaging was developed. An image processing method was used to divide the x-ray image into blocks for multithreshold image cutting and feature extraction. An artificial neural network (ANN) was then used to find the blocks that contain voids, and the voids were located by Hough transform. The effects of various block widths and heights were studied; a block size of 30 $\,\times\,$ 40 pixels is recommended. The void detection is more sensitive to block width than height. Experiments show that the method proposed in this paper can automatically and rapidly detect voids in TSVs using one 2-D X-ray image.

The small slop approximation (SSA) is an accurate method to calculate the electromagnetic (EM) scattering properties of rough surfaces. However, its computational complexity restricts its application to smaller domains and there is always the need for speedup in very large cases using pure central processing units (CPUs) hardware. With the development of graphics processing units (GPUs), more processors are dedicated to perform independent calculations. In addition, NVIDIA introduced a parallel computing platform, compute unified device architecture (CUDA), which provides researchers an easy way to use processors on GPU. To calculate EM scattering properties on GPU, we reformulate the SSA method with CUDA to take advantage of GPU threads. Because each thread executes synchronously and deals with a corresponding point data of rough surface, the CUDA-based SSA method calculates faster than the pure-CPU equivalent. To overcome memory limitations, the data of large rough surface are stored on hard disk. Moreover, a subsidiary thread is used to deal with the process of data transmission between the memory and the hard disk and reduce transmitting time further. The factors, block size, data transfers, and register, are also discussed in the optimization of the CUDA application. Test cases running on a NVIDIA GTX 460 GPU indicate that two orders of magnitude speedup, including file input and output, is obtained with our new formulation.

This paper presents bi-directional trajectory tracking with variable block-size motion estimation for frame rate up-conversion (FRUC) based on the algorithm/architecture co-exploration (AAC) design methodology. Due to concurrent exploration in both algorithm and architecture domains, the designed system requires fewer computations and lowers hardware cost, but is capable of enhancing the accuracy of motion vectors (MVs) by allowing MV refinement from coarse-grained to fine-grained. In addition, a method that uses multiple block candidates tracked by bi-directional MVs for interpolation is also presented to improve visual quality. Benefiting from AAC, we can extract architectural information at algorithmic design phase to determine the most feasible architecture; then, the proposed algorithm can be mapped onto target platform smoothly. The proposed FRUC system, which is capable of converting the frame rate from 60 fps up to 120 fps at full HD (1920 × 1080) resolution, was successfully implemented and verified on a field-programmable gate array. This FRUC system's performance has not only been shown to surpass state-of-art alternatives in algorithmic performance, but its hardware cost is less than the comparable works described in the literature.

In PET detector designs, the scintillator material can be partitioned such that a block of crystals share timing/energy readout electronics. A fraction of the incident 511 keY photons produce simultaneous events in two adjacent block readouts due to Compton scattering followed by escape from the primary block. These inter-block Compton scatter events are typically not processed in current PET scanners. We have used radiation transport simulations to determine the fraction of inter-block Compton events for different block sizes using LYSO scintillator. The simulations showed the statistical distribution of the energy signals and time stamps in the two blocks and guided the selection of energy and time criteria for an event recovery algorithm. With a particular block size, we experimentally demonstrated that inter-block Compton events may be recovered as valid events with a corrected time stamp and estimated position of initial interaction. The results showed a significant improvement in detector sensitivity at the expense of a small degradation in the timing resolution of the detector block.

Graphic Processing Units offer the possibility of executing several threads in parallel, providing the user with higher throughput with respect to traditional multi-core processors. However, the additional resources required to schedule and handle the parallel processes may have the countermeasure of making GPUs more prone to be corrupted by neutrons. The reported experimental results prove that un-optimized thread distribution may exacerbate the device output error rate. As demonstrated, increasing the parallel algorithm block size minimizes the GPU neutron-induced output error rate. The GPU parallelism management is then analyzed as a method to increase reliability.

The success of a side-channel attack depends mainly on three factors, namely, the cipher algorithm, the attack platform, and the measurement noise. In this paper, we consider a class of side-channel attacks known as differential cache attacks on Feistel ciphers, and develop a theoretical framework to understand the relationship between the attack's success, the target platform, and the cipher algorithm. The framework allows a comparison of various differential cache attack forms, and is supported by case studies on the block ciphers CLEFIA and CAMELLIA. To understand the effect of noise in the attack's success, the paper uses empirical methods on standard Intel platforms in a time driven side-channel analysis scenario.

It has long been held that errors in received noisy ciphertexts should be eliminated using as many as possible powerful error correcting codes in order to reduce the avalanche effect on legitimate users' performance in block ciphered systems. However, the negative effect of erroneous ciphertexts on cryptanalysis by an eavesdropper has not been well understood, nor the possible measurable trade-off between security enhancement and performance degradation under noisy ciphertexts. To address these questions, we have launched a case study in this paper using Data Encryption Standard (DES)-based block ciphers operating in cipher feedback (CFB) mode to show quantitatively the pros and cons of exploiting voluntarily or nonvoluntarily introduced binary errors in ciphertexts of block ciphered systems using our proposed comparison metrics. A serially concatenated scheme with both outer and inner encoder-encipher pairs is proposed which allows us to quantitatively reveal the sacrifice made by legitimate users in its postdecryption capacity, as well as the security improvement factor (SIF) which reflects the additionally required plaintext-ciphertext pairs for eavesdropper's known plaintext attack, in the presence of noise in ciphertexts. Simulation results demonstrate the accuracy of derived approximations of the postdecryption performance for the legitimate receiver.

In this brief, we present how parallel-interleaved addresses generated by a quadratic permutation polynomial (QPP) interleaver are related to each other and propose a low-complexity parallel QPP interleaver based on the relationship. While a conventional parallel turbo decoder employs a number of interleavers as many as the parallel factor, the proposed method, which benefits from the arithmetic relationship denoted as the permutation pattern (PP), supports the parallel interleaving using only a single interleaver, resulting in a notable reduction of complexity. The strength of the proposed method stems from the fact that the PP is fully determined by only the decoding parameters, such as block size, parallel factor, and QPP coefficients. Experiment results on the Long Term Evolution turbo codes show that the proposed interleaver can significantly reduce the hardware complexity compared with conventional implementations.