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This paper introduces a heterogeneous die integration process using electroplated copper to mount a bare die into a silicon handling wafer while simultaneously forming vertical, through-wafer vias. Deep reactive-ion etching is used to form openings in the handling wafer allowing the die to be flush-mounted for minimal device thickness. The backsides of the support wafer and die are coated by copper sputtering and electroplating, which physically secures the die in place. Electrical isolation is achieved through passivation of the silicon handle wafer sidewalls before copper electroplating. Wet thermal oxide growth was chosen over plasma-enhanced chemical vapor deposition as the sidewall passivation technique, as wet thermal oxide was found to yield superior coverage and uniformity. Topside interconnects were realized using a previously established thick-film copper metallization process. A $3\times 3$ die array was successfully produced and tested for die-to-die connectivity. Thermal modeling of the fabricated devices showed that power densities up to 1 W/cm $^{2}$ could be accommodated while keeping the maximum temperature below 85 °C.

In this letter, an innovative fabrication method for InGaN-based light-emitting diode (LED) was proposed, and the produced optical device was called the wafer-level InGaN-based thin-film flip-chip LEDs (wTFFC-LEDs). Packaging technologies, such as wafer-to-wafer bonding, laser lift-off, textured surface, and interconnection techniques, were applied to complete the device. Through this architecture, the absorption caused by electrodes in traditional vertical injection LEDs (V-LEDs) can be minimized, as well as the light extraction efficiency can be improved. Light-output power of wTFFC-LEDs (350 mA) was increased by 36.5% and 17.2% compared with the V-LEDs and flip-chip LEDs. Furthermore, the external quantum efficiency was also relatively enhanced by 36.3% and 15.5% higher than those of reference devices.

By co-integrating optics and electronics on the same chip, high-functionality, high-performance and highly integrated devices can be fabricated with a well-mastered microelectronics fabrication process. Different integration schemes with bonding are presented either with die-to-wafer or wafer to wafer bonding. Depending of the applications and the maturity level of the technologies, the strategies for integration will differ.

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

A wafer-level vacuum package with silicon bumps and electrical feedthroughs on the cap wafer is developed for a microelectromechanical systems (MEMS) resonator device. A MEMS resonator wafer and a cap wafer are bonded together in a vacuum chamber using glass frit bonding. The cap wafer not only provides a vacuum chamber to protect the movable resonator structure and improve the resonant performance but also realizes the redistribution of the electrical feedthroughs by using the silicon bumps. The silicon bumps provide vertical interconnections between the cap wafer and the resonator wafer, which realizes the bonding pads “transferring” from the resonator wafer to the cap wafer. A gold-aluminum eutectic is used to ensure electrical contacts between the cap wafer and the device wafer. The device fabrication and glass frit hermetic bonding process as well as the packaged MEMS resonator characterization are presented in this paper. Experimental results show that the wafer-level vacuum-packaged MEMS resonator results in over 100× higher quality factor (Q) than the resonator vibrating in atmosphere pressure, which confirms the transmission performance improvement due to vacuum packaging. Vacuum inside the package is measured indirectly by measuring the Q of the MEMS resonator inside the package. The experimental results indicate that vacuum about 1 mbar can be sealed in this approach.

The effects of temporary bonding processes on thin wafer handling were investigated. Backside dielectric curing process was found to be a critical process for the void formation in the thin wafer handling which was confirmed by scanning acoustic microscope and by thermo-gravimetric analyzer out-gassing analysis. The effects of voids on back-side wafer processes were discussed. Finally, 3-D through silicon via integration with thin wafer handling (50 μm in thickness) was demonstrated with selected dielectric passivation material and temporary bonding adhesives.

We present the successful fabrication of capacitive micromachined ultrasonic transducers (CMUTs) with an improved insulation layer structure. The goal is to improve device reliability (electrical breakdown) and device performance (reduced parasitic capacitance). The fabrication is based on consecutive thermal oxidation steps, on local oxidation of silicon (LOCOS), and on direct wafer bonding. No chemical-mechanical polishing step is required during the device fabrication. Aside from the advantages associated with direct wafer bonding for CMUT fabrication (simple fabrication, cell shape flexibility, wide gap height range, good uniformity, well-known material properties of single-crystal materials, and low intrinsic stress), the main vertical dimension (electrode separation) is determined by thermal oxidation only, which provides excellent vertical tolerance control (

A new ultrathin chip fabrication and assembly process, consisting of a preprocess module Chipfilm and a postprocess module Pick, Crack, and Place, is presented. In contrast to the established wafer thinning technique, the preprocessed wafer substrates are prepared with extremely narrow buried cavities beneath the chip areas at a well-defined distance from the wafer surface, thus precisely defining the chip thickness a priori. After CMOS integration on those dedicated wafer substrates, chips are detached from the wafer surface by etching trenches at the chip edges into the buried cavities and breaking of residual anchors by mechanical force in the postprocess. The feasibility of the new process is demonstrated through a mixed-signal circuit having 38 000 digital and 2700 analog transistors, showing full functionality within specifications for 20-mum-thin chips even under a bending stress of up to 110 MPa.

With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored.

This paper presents a novel approach to combine wafer level packaging (WLP) with micromachined hotplate gas-sensing elements. This concept allows liquid-tight sealing of gas sensor devices, which protects them during production (e.g., wafer dicing) and later in the application while still allowing the target gases to reach the sensing layer. The basis of the WLP is the combination of a structured Pyrex wafer with a micromachined substrate wafer. Thereafter, thick-film SnO 2 layers are deposited and stabilized before a diffusion membrane is attached, which seals the wafer stack

Making chips a single wafer at a time can reduce chip oversupply and help ensure sustainable growth in the semiconductor industry.

In this letter, an approach to the redistribution of electrical interconnections is investigated for potential application in 3-D wafer-level packaging. A cap wafer with silicon bumps and electrical feedthroughs is bonded together with a device wafer using wafer-level glass-frit bonding technology. During the bonding process, the mechanical bond is performed by glass-frit bonding to form hermetic packaging. Simultaneously, the silicon bumps provide close contact for the electrical feedthroughs on the cap wafer and the metal pads on the device wafer, on which a gold-aluminum eutectic is formed to achieve electrical interconnections between the cap wafer and the device wafer. Moreover, the silicon bumps provide a way to control well the height of the bonding materials. This process not only realizes a wafer-level hermetic sealing but also achieves the redistribution of electrical interconnections. Application of this approach for a high performance MEMS resonator is demonstrated, which illustrates the feasibility of this process.

Present designs for millimeter and submillimeter superconducting mixer circuits often require finished quartz wafer thicknesses from a few mils to less than a mil. Typically this is accomplished by first dicing the wafer into individual chips and then thinning each chip separately. In our new process the entire wafer is first diced; however, the cuts are only made two mils deeper than the desired finished chip thickness. An ultra-flat Si wafer is prepared with a 5 /spl mu/m thick Apiezon-W black wax coating on both sides. The quartz wafer is mounted to the Si carrier, cuts side down, which is itself mounted to a stainless steel lapping block. The "stack" of block/Si/quartz is then placed in a tool designed to permit compression of the sandwich to 30 psi at 145C. In this process the quartz wafer is positioned flat with respect to the Si wafer to better than +/-2.5 /spl mu/m. The stack is then lapped and polished through the backside of the wafer, into the cuts to the desired wafer thickness to better than +/-5 /spl mu/m. The Si/quartz bilayer is subsequently removed from the block resulting in a fully diced and thinned quartz wafer.

In this paper, we present a new wafer-level transfer bonding technology. The technology can be used to transfer devices or films from one substrate wafer (sacrificial device wafer) to another substrate wafer (target wafer). The transfer bonding technology includes only low-temperature processes; thus, it is compatible with integrated circuits. The process flow consists of low-temperature adhesive bonding followed by sacrificially thinning of the device wafer. The transferred devices/films can be electrically interconnected to the target wafer (e.g., a CMOS wafer) if required. We present three example devices for which we have used the transfer bonding technology. The examples include two polycrystalline silicon structures and a test device for temperature coefficient of resistance measurements of thin-film materials. One of the main advantages of the new transfer bonding technology is that transducers and integrated circuits can be independently processed and optimized on different wafers before integrating the transducers on the integrated circuit wafer. Thus, the transducers can be made of, e.g., monocrystalline silicon or other high-temperature annealed, high-performance materials. Wafer-level transfer bonding can be a competitive alternative to flip-chip bonding, especially for thin-film devices with small feature sizes and when small electrical interconnections (

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP/sup TM/. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed.

Bonded wafer substrates that are optimized for integrating high-energy-particle silicon detector arrays with their readout electronics have been fabricated. The detectors are processed in the handle wafer, which is a 300- mu m-thick, high-resistivity, silicon wafer. This wafer is bonded to a primary wafer using a low-temperature process that does not affect the detector material. The support electronics are processed in the remnant of the primary wafer, which is a submicron-thick silicon film formed by a bond-and-etchback procedure. These two materials are isolated from each other by a radiation-hardened dielectric film. The integration process is based on a low-temperature, radiation-hardened VLSI CMOS process that is also shown not to seriously affect the detector material. >

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 /spl mu/m in thickness, a crucial factor for use in various size sensitive electronic products.

A new air-isolation process is described which overcomes many of the problems of existing isolation technologies. The process consists of standard integrated circuit processing except for the p-n junction isolation process which is omitted. After metal mask, the device wafer is glass bonded face down to a supporting silicon wafer. Subsequent backlapping, masking, and mesa etching steps yield an air-isolated integrated circuit. As one application of this technology, the fabrication of a radiation-hardened operational amplifier is described.