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In this article, we demonstrate the Ti/TiN/Al (15/50/50 nm) ohmic contact on InGaP/GaAs heterojunction bipolar transistors (HBTs) epitaxially grown on 200-mm Si substrate. We study the rapid thermal annealing (RTA) effect of the metal stack on both n-type InGaAs and p-type GaAs. The dc characteristics of the HBT devices fabricated using the Ti/TiN/Al metal contacts have been analyzed. Contact resistances (R-c)

We report on the growth of In0.30Ga0.70As channel high electron mobility transistor (HEMT) epi-layers on a 200-mm Si substrate by metal-organic-chemical-vapor-deposition. The HEMT layers were grown on the Si substrate by using a ~3- ${\mu }\text{m}$ thick epitaxial buffer composing of a Ge layer, a GaAs layer, and a compositionally graded and strain relaxed InAlAs layer. The optimized epitaxy has a threading dislocation density of less than $2 {\times } 10^{{7}}$ cm−2 and a root mean square surface roughness of ~6.7 nm. The device active layers include a ${ {\delta } }$ -doped InAlAs bottom barrier, a ~15-nm thick InGaAs channel, a ~8-nm InGaP top barrier layer and a heavily doped InGaAs contact layer. MOSHEMTs with channel length down to 130 nm were fabricated. The devices achieve a peak transconductance of ${\sim }450 ~{\mu }\text{S}/ {\mu }\text{m}$ at ${V} _{ D}$ of 0.5 V. The peak effective mobility ( ${\mu }_{\text {eff}}$ ) in a device with a channel length of 20 $ {\mu }\text{m}$ device channel was ~3700 cm2/ $\text{V} {\cdot }\text{s}$ .

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work.

In this letter, a novel compact on-chip output matching network to achieve harmonic impedance matching is proposed. With the proposed matching network, a highly efficient GaN monolithic microwave circuit power amplifier (PA) is designed for 5-GHz wireless local area network 802.11ac application. The implemented PA achieves a maximum power-added efficiency (PAE) of 49.5%-61.3% over the frequency band from 4.9 to 5.9 GHz, with a saturated output power (Psat) of 34.6-36.1 dBm. When tested with 802.11ac VHT80 MCS9 (80 MHz, 256-quadratic -amplitude modulation) signal with 11.3-dB peak-to-average power ratio, the PA achieves an average output power of 23.7-26.3 dBm, with a PAE of 24.9%-30.9%, while meeting the standard error vector magnitude specification of -32 dB. Accepted version

This paper describes the analysis following the breakdown of an ion cyclotron radio frequency (ICRF) tuner purchased from Advanced Ferrite Technology (AFT). The codes used in the analysis were CST and COMSOL. These codes use the standard gyromagnetic model for the ferrite, which gives results that are largely in error when compared with measurements at ICRF and at lower hybrid frequencies. We have measured a slab of the ferrite used in the ICRF tuner provided by AFT and from these measurements we have constructed a tabular model of the ferrite and inserted it into the COMSOL code. The results give performance that closely agrees with the performance specifications issued by AFT. We then used this modified code to correlate the simulation with the destructive evidence found in the tuner. The correlation was good between the destruction spot and the peak of the standing electric field. Pictures of the destruction and the heating in the tuner and the standing field results from the simulation are given.

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain.

Single-layer antireflective coating (SLARC) materials and design for GaAs1_xPx/Si tandem cells were analyzed by TCAD simulation. We have shown that optimum SLARC thickness is a function of bandgap, thickness, and material quality of top GaAs 1-x P x /Sisubcell. Cells are analyzed for P fractions x = 0, 0.17, 0.29, and 0.37, and ARC materials: Si 3 N 4 , SiO 2 , ITO, 11fO 2 , and Al 2 O 3 . Optimum ARC thickness ranges from 65-75 nm for Si 3 N 4 and ITO to ~100-110 nm for SiO2. Optimum ARC thickness increases with increasing GaAs1_xPx absorber layer thickness and with decreasing P fraction x. Simulations show that optimum GaAs 1-x P x /Siabsorber layer thickness is not a strong function of ARC material, but it increases from 250 nm for x = 0 to1 μm for x = 0.29 and 0.37. For all P fractions, Si 3 N 4 , 11fO 2 , and Al 2 O 3 performed almost equally, while SiO2 and ITO resulted in ~1% and ~2% lower efficiency, respectively. Optimum SLARC thickness increases as the material quality of the top cell increases. The effect of ARC material decreases with decreasing GaAs1_xPx material quality. The maximum efficiencies are achieved for cells with ~1-μm GaAs0.71P0.29 absorber (r = 10 ns): ~26.57% for 75-nm Si 3 N 4 SLARC and 27.62% for 75-nm SiO2/60-nm Si 3 N 4 double-layer ARC.

The quality of germanium (Ge) epitaxial film grown directly on silicon (Si) substrate is investigated based on the electrical properties of a metal-oxide-semiconductor capacitor (MOSCAP). Different thermal cycling temperatures are used in this study to investigate the effect of temperature on the Ge film quality. Prior to high-k dielectric deposition, various surface treatments are applied on the Ge film to determine the leakage current density using scanning tunneling microscopy. The interface trap density (Dit) and leakage current obtained from the C-V and I-V measurements on the MOSCAP, as well as the threading dislocation density (TDD), show a linear relationship with the thermal cycling temperature. It is found that the Ge epitaxial film that undergoes the highest thermal cycling temperature of 825°C and surface treatment in ultraviolet ozone, followed by germanium oxynitride (GeOxNy) formation, demonstrates the lowest leakage current of ~ 2.3×10-8 A/cm2 (at -2 V), Dit ~ 3.5 × 1011 cm-2/V, and TDD

In this letter, the tuning of a nickel fully germanided metal gate effective workfunction via a hyperthin yttrium (Y) interlayer at the bottom of the metal electrode was demonstrated on both SiO2 and HfO2. By varying the Y interlayer thickness from 0 to 9.6 nm, a full range of workfunction tuning from 5.11 to 3.65 eV has been achieved on NiGeY/SiO2 stacks. It was also found that the chemical potential of the material that is adjacent to the gate electrode/gate insulator plays an important role in the determination of the effective workfunction. This work-function tuning window was observed to decrease to a range of 5.08-4.25 eV on NiGeY/HfO2 stacks.

We have experimentally studied impact ionization (II) in the strained-Si layer of a strained-Si/SiGe heterostructure. Our key finding is that the impact ionization multiplication coefficient has a positive temperature coefficient which is opposite to that of bulk Si. Furthermore, the temperature dependence of the multiplication coefficient has been found to be exponential in nature. Our experimental work shows that the combination of a strong and positive temperature dependence of the II coefficient and the significant self-heating that this structure suffers from results in an overall impact ionization rate that is more than an order of magnitude higher than that of reference Si devices operating under identical bias conditions.

High-performance p/sup +//n GaAs solar cells were grown and processed on compositionally graded Ge-Si/sub 1-x/Ge/sub x/-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm/sup 2/ solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm/sup 2/ did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.

The impact of processing factors such as ion implantation and rapid thermal annealing on mobility enhancement in strained-Si n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) has been investigated. Long-channel strained-Si and bulk n-MOSFETs were fabricated with various channel-region implant doses and thermal budgets. Neutral Si and Ge species were used to study the impact of the implant damage on mobility separately from ionized impurity scattering effects. Electron mobility enhancement is shown to degrade considerably when the implant dose is above a critical dose for a given thermal budget. Transmission electron microscopy, secondary ion mass spectrometry and Raman spectroscopy were used to investigate the mobility degradation mechanisms. Residual implant damage and implant damage enhanced Ge up-diffusion into the Si are shown to be responsible for the mobility degradation. Two-dimensional damage simulations of 30-nm scale MOSFETs are used to examine potential technological implications of these findings.

Hole mobility is characterized in P-MOSFETs with a layered substrate consisting of tensile strained Si cap on a compressively strained Si/sub 0.4/Ge/sub 0.6/ buried layer grown pseudomorphically to a relaxed Si/sub 0.7/Ge/sub 0.3/ virtual substrate. Besides the expected mobility enhancement in the strained Si cap and in the buried Si/sub 0.4/Ge/sub 0.6/ layer, a second peak in mobility versus total inversion carrier areal density curve was observed under strong inversion conditions in thin Si-cap layer samples. Qualitatively, this reversed mobility trend can be correlated to the transition of inversion conduction from the buried layer to the surface layer, but quantitative analysis reveals that the surface layer mobility in thin Si-cap samples needs to be substantially larger than that in thick-cap samples, if it can be assumed that mobility is a function of transverse field. Further analysis found that, if it is assumed that mobility is a function of inversion carrier density, measured mobility curves can be matched consistently with a single set of mobility-carrier-density relationship.

Dual junction GaInP/GaAs solar cells have been grown and fabricated on Si substrates using relaxed, compositionally graded SiGe buffer layers that provide a nearly lattice-matched low threading dislocation Ge surface for subsequent cell growth. The dual junction cells on SiGe/Si displayed high open circuit voltages in excess of 2.2 V, compared to 2.34 V for control cells on GaAs, that are consistent with maintaining the 1.8/spl times/10/sup 6/ cm/sup -2/ threading dislocation density throughout the cell structure. Even with total current output limited by large grid coverage and high reflectance, total area AM1.5G efficiency is 16.8%, with active area efficiency at 18.6%. The high V/sub oc/ establishes that SiGe metamorphic buffers are viable for integrating III-V multijunction cells on Si in a monolithic process.

Fully depleted strained-Si n- and p-MOSFETs have been demonstrated on bonded-SiGe-on-insulator (SGOI) substrates. The fully depleted devices show significant electron and hole mobility enhancements of 60 and 35%, respectively, demonstrating that high material quality, thin SGOI substrates can be fabricated by a wafer bonding approach. The bottom SiGe/buried-oxide interface in the SGOI structure and its impact on fully depleted device performance are also investigated.

High-hole and electron mobility in complementary channels in strained silicon (Si) on top of strained Si/sub 0.4/Ge/sub 0.6/, both grown on a relaxed Si/sub 0.7/Ge/sub 0.3/ virtual substrate is shown for the first time. The buried Si/sub 0.4/Ge/sub 0.6/ serves as a high-mobility p-channel, and the strained-Si cap serves as a high-mobility n-channel. The effective mobility, measured in devices with a 20-/spl mu/m gate length and 3.8-nm gate oxide, shows about 2.2/spl sim/2.5 and 2.0 times enhancement in hole and electron mobility, respectively, across a wide vertical field range. In addition, it is found that as the Si cap thickness decreased, PMOS transistors exhibited increased mobility especially at medium- and high-hole density in this heterostructure.

In this letter, we investigate the dependence of electron inversion layer mobility on high-channel doping required for sub-50-nm MOSFETs in strained silicon (Si), and we compare it to co-processed unstrained Si. For high vertical effective electric field E/sub eff/, the electron mobility in strained Si displays universal behavior and shows enhancement of 1.5-1.7/spl times/ compared to unstrained Si. For low E/sub eff/, the mobility for strained Si devices decreases toward the unstrained Si data due to Coulomb scattering by channel dopants.

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si/sub 0.75/Ge/sub 0.26/ and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si/sub 1-x/Ge/sub x/ layer.