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Ruthroff-type transmission line transformers (TLTs) and baluns prevail over their broadband and low-loss performance. A typical Ruthroff-type balun with a 1:4 step-up impedance transformation ratio was successfully presented using integrated passive devices (IPDs) process. Moreover, two proposed baluns with step-down impedance transformation ratios of 1:1 and 9:4 were developed by modifying the combination of one Ruthroff-type TLT and one Ruthroff-type balun. The two proposed impedance step-down baluns whose balanced impedance is lower than unbalanced impedance make Ruthroff-type balun more flexible for applications; meanwhile, fabricating the baluns using IPD process can help to enhance the low-loss performance. The measured results show that the proposed 1:1 balun exhibits an insertion loss of 0.46 dB with 1-dB fractional bandwidth of 138.9%, and the proposed 9:4 balun exhibits an insertion loss of 0.75 dB with 1-dB fractional bandwidth of 72.4%. The chip areas of the proposed 1:1 and 9:4 baluns, including the pads, are 0.6 and 0.64 ${\rm mm}^{2}$ , respectively. The two proposed baluns are the first on-chip step-down Ruthroff-type baluns and having an option of center tap, which is highly contributive to wideband and high-efficiency power amplifier design.

Strontium zirconate nickelate [(SZN); Sr0.69Ni0.47Zr0.085O3.75] was synthesized through a sol-gel method by adding nickel (II) acetylacetone instead of titanium isopropoxide, which can effectively make thin films smoother and further act as gate insulators applied in pentacene-based thin-film transistors. Sol-gel SZN thin films were investigated by X-ray photoelectron spectroscopy and atomic force microscopy to confirm the chemical composition and smooth surface roughness, and the latter property was found to be compatible for pentacene thin film growth. Thus, the electrical characteristics of pentacene-based transistors exhibited a high mobility of 10.04 cm2 V-1s-1 low threshold voltage of -1.51 V,, and low subthreshold swing slope of 350 mV/decade. To realize high mobility mechanisms, intermolecular coupling and reorganization energy of pentacene thin films were introduced. Another purpose of this introduction was to evaluate the higher hopping rate of carriers between the adjacent pentacene molecules on SZN derived from the March-Hush equation than other high-κ traditional sol-gel insulators.

A high-gain gate-pumped down-conversion mixer at 60 GHz is realized in a standard 90-nm CMOS process. The proposed mixer adopted a Darlington cell and a microstrip-line Lange coupler to yield wide 3-dB bandwidth from 5 to 65 GHz. The measured performance demonstrates a conversion gain (CG) of 6 dB at 4.2-mW power consumption. The maximum CG is 6.5 dB at 36 GHz. This mixer is then integrated with a three-stage low-noise amplifier, to form a 60-GHz receiver front-end. The receiver achieves a CG of 28 dB with a noise figure of 7.1 dB at 20-mW power consumption from a 1-V supply voltage. The 3-dB RF bandwidth is 14 GHz.

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm2. The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm2. The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm2. A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm2.

In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current ION and reduce the off leakage current IOFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the ION/IOFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric

Pentacene-based organic thin-film transistors with solution-processed barium zirconate titanate dielectric layers are demonstrated. According to the programming/erasing operations, the devices exhibited memory characteristics, such as reversible threshold voltage shifts and nondestructive readout. In addition, the reliability of the memory devices was confirmed by data retention time and repeated switching cycles' endurance testing. In addition, the possible mechanism of the memory effect was also discussed. These results suggest that the devices could potentially be applied to nonvolatile memory applications in organic electronics.

A three-phase four-wire power factor corrector based on neutral-point-clamped (NPC) topology is adopted to reduce the current harmonics and increase the input power factor. Using the NPC topology, the voltage stress of power switches can be reduced to the half of the dc-link voltage. With the dc-link voltage controller and the phase locked loop circuit, the balanced and sinusoidal line currents can be drawn from the ac supply system under the balance and unbalance mains voltages. The hysteresis current comparators are adopted in the current control loop to track the line current commands. Three voltage levels are generated on the ac terminal to the neutral point. Simulations and experiments are provided to verify the validity and the effectiveness of the proposed control scheme.

A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-mum CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm2. To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-mum CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.

In this letter, fluorine ion implantation with low- temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin- film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of Imin is achieved because 25% grain- boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low VTH ~ 1.32 V, excellent subthreshold swing ~0.141 V/dec, and high ION/Imin current ratio ~1.98 times 107.

A compact V-band star monolithic microwave integrated circuit mixer has been designed using compensated overlay capacitors in dual baluns for the input of local oscillator and radio frequency ports. The reduced-size balun can be simply realized by shunting overlay capacitor in either input or end of balun. The proposed V-band star mixer achieved a conversion loss of 8.6 dB, the port-to-port isolations better than 18 dB, and an input 1-dB compression point higher than 7.7 dBm at 60 GHz. Moreover, better than 50% length reduction of dual balun was achieved, and chip size of star mixer including pads was less than 0.68 times 0.59 mm2.

A 16-46 GHz mixer using broadband balun fabricated in standard 0.18-mum CMOS process is demonstrated. The broadside-coupled balun with wide bandwidth and low insertion loss utilizes the inherent 3D multilayer structure in CMOS process. The mixer exhibits radio frequency bandwidth from 16 to 46 GHz with a conversion loss ranging from 13 plusmn 1.5 dB, and achieves bandwidth over 103% with a compact chip size of 0.24 mm2.

This work presents a miniature Q-band balanced single side-band sub-harmonically pumped image rejection diode mixer (SHIRM) using a compact Marchand dual balun design. The SHIRM is realized employing four anti-parallel diode pairs for frequency mixing, a Lange coupler for radio frequency (RF) signal input, and a reduced size three-conductor-line Marchand dual balun for local oscillator pumping. The length of three-conductor-line dual balun is reduced by 81% after shunting two lumped capacitors at the center conductor. The measured results exhibit a minimum conversion loss of 8.6 dB, a maximum image rejection ratio of 22 dB, all ports isolation better than 37 dB, and an input 1-dB compression point of 2.5 dBm at RF bandwidth of 40.5 to 43.5 GHz and fixed intermediate frequency of 2.4 GHz. The chip area is very compact, only 1 times 0.84mm2

In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>104) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application