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By using integrated lumped elements based on through-silicon via (TSV) technology, a 3-D low-pass filter (LPF) with ultracompact size and ultrawide stopband is proposed. The 3-D magnetic coupling is enhanced between microsize spiral inductors to increase the mutual inductance and improve the high-frequency performance. A coaxial TSV with enhanced capacitance in high resistivity silicon (HRS) is utilized both as capacitor and as a vertical interconnection without any overhead in area and routing. The 3-D nature of the proposed filter yields a miniaturized size of 0.2 x 0.10 mm². The LPF is analyzed with equivalent circuit model and validated with the well-matched S-parameters obtained by finite element method simulation and measurement. With -3-dB cutoff frequency at 2.6 GHz, the LPF exhibits an insertion loss below 1 dB, a reflection loss over 17 dB in the passband, and a suppression level over 20 dB from 5.28 up to 40 GHz in the stopband.

An extended model of through-silicon via (TSV)-based solenoid inductor is proposed to save on-chip areas for 3-D radio frequency (RF) ICs and package integration. To achieve a high inductance density, the nested topology consists of high-density TSVs in high-resistivity silicon substrate and multilayers of metals in compatible CMOS process. Then, an analytical inductance model, considering the mutual inductance of TSVs and complicated metal traces, is established and verified. The inductance variation in physical dimensions is studied based on the modeled and simulated results of a TSV solenoid inductor in single tier. The proposed TSV solenoid typology gets better performance at inductance density and quality factor around some frequencies through analytical model and full-wave simulations. Further studies are directed toward RF application overview according to broadband and low power consumption.

A balanced substrate-integrated waveguide (SIW) bandpass filter (BPF) is designed and fabricated based on through-quartz-via (TQV) technologies in this article. Sixth-order filtering response centered at 41.4 GHz with equal source and load termination is achieved by the transformation of the Chebyshev polynomial. By exploiting cross-coupled resonators, the 3-dB fractional bandwidth (FBW) achieves 12.1%, and the out-of-band rejection is better than 30 dB with frequencies up to $2f_{0}$ . High CM suppression can be achieved up to $2.2f_{0}$ with the help of two slots on the bottom metal layer. Based on the theory of the proposed SIW BPF, asymmetric diplexer with different resonance orders for two channels is studied with high isolation and wide stopband. The mixed dual-mode (TE101 and TE301) and single-mode (TE101) junction resonators provide a transition between the input port and two channels. Diplexer with lower and upper channels centered at 20.2 and 37.5 GHz, respectively, is fabricated and measured to verify the proposed structure, which exhibits high isolation better than 40 dB over the whole band and a wide stopband up to $3f_{0}$ of the lower channel. Measured results are in good agreement with the simulations.

This brief proposes a novel comparator to greatly increase its comparison speed while not degrading its noise performance. This comparator is well suited for high-speed high-resolution SAR ADCs. Its structure is based on the classic Miyahara’s two-stage comparator with the addition of only an extra charge pump. This simple modification greatly accelerates both the second-stage amplification phase and the regeneration phase, leading to significantly increased comparison speed. Meanwhile, the noise performance is not degraded, because the input pair transconductance of the second stage is increased while its integration time is decreased. For fair comparison, both the proposed comparator and the classic Miyahara’s comparator are implemented in the same 40nm CMOS process. Measurement results show that the proposed comparator speed is faster by 60% compared with the classic Miyahara’s comparator, while the input-referred noise is similar.

This article presents a novel pico-watt voltage reference (VR) circuit whose power consumption is well controlled at high temperature. Unlike a traditional pico-watt VR circuit whose power consumption increases exponentially with temperature, the power consumption in this article increases linearly with temperature, thus saving much energy at high temperature. It generates the reference voltage through a 2-transistor (2-T) structure and a current generator to well control the current versus temperature. In the current generator, a gate leakage transistor replaces a huge resistor, thus saving 4-mm2 area. Fabricated in a 0.13- $\mu \text{m}$ CMOS process, this VR circuit generates a reference voltage of about 560 mV and shows an average temperature coefficient (TC) of 18.4 ppm/°C after trimming across −25 °C to 85 °C and a line sensitivity (LS) of 0.15%/V, while consuming 20 pW at 1-V ${V} _{\text {DD}}$ and 27 °C. The power consumption at 3.3-V ${V} _{\text {DD}}$ and 85 °C is 114 pW, which is at least two times smaller than reported in state-of-the-art work at high temperature. The core area is 0.003 mm2.

A bandwidth optimization model for a novel equivalent 90° transmission-line section is proposed in this paper. Furthermore, the structure of 3-D compact 3-dB branch-line directional coupler and its equivalent-circuit model are presented. They can achieve both excellent isolations between each branch and high-density integration by using equivalent 90° transmission-line sections and coaxial through-silicon via technology in 3-D integrated circuits. Finally, a 3-D coupler is designed with the center frequency of 100 GHz, as well as the bandwidth and size reach 20 GHz and $174\times 236.9\times 208.7\,\,\mu \text{m}^{3}$ , respectively. The results of the 3-D full-wave field solver High-Frequency Structure Simulator and the proposed model are well matched, showing that the proposed model can be used to quickly evaluate the electrical performance of the 3-D coupler before manufacture, thus effectively promoting the design efficiency and quality.

This paper proposes a substrate integrated waveguide bandpass filter (SIW BPF), exploiting the through-dielectric via (TDV)-based 3-D integrated circuit (3-D IC) technology. The SIW BPF is designed on the dielectric cavity that is etched on the traditional low-resistivity silicon (LRSi) in a 3-D IC system, acting as the insulating material between through-silicon via plugs and LRSi. This construction can reduce prominent eddy current losses in LRSi and coupling losses among TDV plugs for the millimeter-wave application. Benzocyclobutene and glass are chosen as the dielectric cavity due to the low dielectric constant and loss tangent. The detailed design procedure beginning from the normalized Chebyshev low-pass filter to the final optimized SIW BPF is presented. The filter having a 12.5% fractional bandwidth is centered at 159.67 GHz. The return losses and insertion loss across the passband are about −10 and −1.5 dB, respectively. Numerical analysis of the advanced design system and full-wave simulation results of Ansoft’s HFSS show a good agreement.

In this paper, an ultra-compact low-pass filter (LPF) with wide stopband is proposed based on lumped L-C structure in through-silicon via-based 3-D stacked configuration. The spiral inductor (L), interdigital capacitor (C), and the proposed LPF are theoretically analyzed based on parasitic parameters and equivalent circuit models. To evaluate the characteristics, the proposed LPF is simulated by HFSS, fabricated with CMOS-process-compatible technology, and measured with de-embedding method. Simulation and measured results are in good agreement. Compared with the other literature, the proposed LPF has the most compact size of $0.028\lambda _{g }\times 0.017 \lambda _{g}$ . ( $\lambda _{g}$ is the guide wavelength at $f_{c}$ .) With the cutoff frequency at 10.05 GHz, the filter has an insertion loss of 0.14 dB and reflection loss over 13 dB from dc to 9 GHz in the passband. The suppression levels are better than 20 dB from 20.4 up to 40 GHz in the stopband.

A wideband equivalent-circuit model of coaxial-annular through-silicon vias (TSVs) for three-dimensional (3-D) integrated circuits is proposed in this paper. Rigorous closed-form formulas for the resistance and inductance of coaxial-annular TSVs are derived by computing the longitudinal electrical field in Cu and the longitudinal magnetic vector potentials in ${\rm{SiO}}_{2}$ and Si substrate with Bessel functions. The equivalent-circuit model can appropriately capture the skin effect in Cu as well as eddy-current effect in Si substrate. The proposed model is verified using 3-D full-wave field solver high frequency simulator structure, showing that it can yields highly accurate results up to 100 GHz.

The 3-D multistrata integration puts forward high requirements for signal integrity. The shielded-pair through-silicon vias (SPTSVs) proposed in this paper feature superior transmission properties and high jamming immunity suitable for differential-mode and common-mode transmission. Based on the quasi-static field theory, a wideband impedance model of SPTSVs considering the proximity effect, the line-to-line crosstalk, and the eddy current effect is derived. The parasitic parameters calculated by the impedance model are further given. The finite-element analysis shows that the proposed model highly agrees with the 3-D full-wave simulation and the analytical calculation. In addition, the characteristics of the impedance and the transmission coefficient are deeply analyzed with different design parameters. Finally, the impacts of the substrate effect and the metal–oxide–semiconductor effect on electrical characteristics of SPTSVs are revealed.

This paper presents an effective loop impedance extraction method and a model of a signal through-silicon via (TSV) surrounded by multiground TSVs. According to this method, the effective coupling substrate capacitances of multiground TSVs with different numbers and placements are calculated. Based on the calculated values of the resistance-inductance-capacitance-conductance (RLCG) parameters, the equivalent circuit and a two-port network model are established. The S -parameters of the model are validated by the simulated and measured results. Then, the effect of different patterns of ground TSVs on the central signal and coupling capacitance are discussed. Note that the hexagon pattern proposed in this paper can save the occupied area prominently without damaging the signal integrity.

This letter explores the inductance of interconnections including through-silicon vias (TSVs) and redistribution layers (RDLs) in 3-D stacked-chip packaging. It is described that the common summing method of partial inductances will result in some deviations from the full inductance. Then, the inductances of TSVs and RDLs are, respectively, calculated and are verified by a commercial electromagnetic simulator. The modified formulas are proposed for the more accurate full inductance model, which is derived from different design physical parameters of the interconnections. The side effect of a general summing method can be reduced a lot by our proposed analytical model.

The parasitic parameters and equivalent electrical model of differential dielectric-cavity through-silicon via (DDC-TSV) array on traditional low-resistivity silicon (LRSi) are proposed in this letter. TSV plugs are placed in the dielectric-cavity etched on LRSi. Each analytical formula in the model is established as the fuction of various physical geometries. The resistance–inductance–capacitance–conductance model and S-parameters of the DDC-TSV array are constructed by the Advanced Design System (ADS), which is verified by the 3-D full-wave electromagnetic solver High Frequency Simulator Structure (HFSS). Simulation results of the ADS and HFSS accord well with each other with frequencies up to 100 GHz, which shows good accuracy of the proposed model.

Keep-out-zone (KOZ) is a conservative way to prevent any devices/cells from being impacted by the through-silicon via (TSV)-induced stress. In this paper, an effective approach was proposed of reducing the KOZ induced by coaxial TSV, by using the structure of coaxial-annular TSV, without decreasing the electrical performance of coaxial TSV. The analytical model was developed appropriate for the thermal stress induced by both coaxial and coaxial-annular TSVs, and was verified by the finite element method. The KOZs induced by coaxial and coaxial-annular TSVs were compared in detail, and the effects of Cu plasticity, TSV material, TSV size, and inner metal plating ratio of coaxial-annular TSV were also studied. The electrical characteristics of different TSVs were compared by employing ANSYS' HFSS, and a feasible fabrication process for coaxial-annular TSV was suggested. It could be concluded that: 1) a 1.6-μm (22.2%) drop of KOZ for coaxial-annular TSV could be reached as compared with that of coaxial TSV; 2) coaxialannular TSV was proved to offer the same superior signal integrity with coaxial TSV, improving S21 by about 93% at 5 GHz and 60% at 20 GHz compared with ordinary cylindrical and annular TSVs; and 3) the coaxial-annular TSV is realizable.

Since the coupling loss of conventional low resistivity silicon (LRSi) is considerable in high speed three-dimensional integrated circuits (3-D ICs), air-cavity through-silicon vias (TSVs) on LRSi are proposed in this letter to reduce the conductive substrate losses for microwave applications. The $Q$ -factor and insertion loss are exploited to assess the effect of air-cavity TSVs. The accurate wideband equivalent circuit model and simplified $\pi$ -model are derived based on the physical design parameters, which are established by the ADS software. Well agreements between the proposed models and 3-D full-wave EM field simulation of Ansoft's HFSS are shown with the operating frequencies up to 20 GHz.

In this letter, Ground-Signal-Ground type through-silicon vias (TSVs) are designed to achieve millimeter wave applications in three-dimensional integrated circuits (3-D ICs). Air-gap is exploited as the insulation layer due to the low permittivity. The accurate wideband equivalent-circuit model are established with frequency up to 20 GHz by using a set of resistance inductance capacitance conductance (RLGC) parameters, which are derived from the different design physical parameters and materials of the TSVs. Good agreements between the proposed models and full-wave simulation of Ansoft's HFSS are shown over a wide frequency range of interest.

In this letter, the parasitic inductance of tapered ground-signal-ground (GSG) type through-silicon via (TSV) pair used in high speed three-dimensional integrated circuits (3-D ICs) are proposed. Rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs. The proposed models are in good agreement with the 3-D electromagnetic (EM) simulator and measurement results with maximum errors of 8%.