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Accurate and timely traffic flow forecasting is the key technology to address the issue of urban traffic congestion, which is significant for intelligent transportation system. However, it is a quite challenging task to develop an efficient, robust and automatically generated forecasting model. In this paper, we propose a novel model, ensemble forecasting architecture based on non-negative constrained sparse autoencoder and extreme learning machine(NCAE-ELM-EA). This model is designed using NCAE to extract traffic characteristics layer-by-layer through a greedy unsupervised algorithm, and the prediction network formed by connecting NCAE and ELM serves as base learner of each lag pool. Then, employing adaptive enhanced integration algorithm to build an ensemble optimized forecasting model with scalable size suitable for each road segment. The model was applied to the actual data collected from I5 NB highways in Portland, USA, and J6-J7(N) freeways in the United Kingdom, with higher accuracy and lower labor costs compared with existing predictors.

High-valent transition-metal (Ti or Mo)-doped ZnO thin-film transistors (TFTs) were fabricated using radiofrequency magnetron sputtering at 150 °C. When the Ti or Mo was doped in the ZnO channel, device characteristics, such as threshold voltage, were modulated and field effect mobility could be enhanced. The device stability of the TFTs with a low Mo content was dramatically improved, which can be attributed to the incorporation of Mo suppressed the generation of oxygen vacancies in the ZnO active channel layer. These results indicate that high-valent transition-metal-doped ZnO TFTs strongly sustain further investigation for their applicability as alternative channel materials.

Chip-scale packages (CSPs) are widely used in portable electronic products. Mechanical drop testing is a critical reliability requirement for these products. With the switch to lead-free solder, new reliability data must be generated. Most drop test reliability data reported for CSPs are for the as-built condition. However, the mechanical shock reliability over the life of the product is equally important. This paper provides a systematic study of surface finish (immersion Sn and immersion Ag) and reflow profile (cool down rate) on the drop test reliability of CSP assemblies. A limited experiment was also performed with organic solderability preservative (OSP)-coated boards. The Sn finish provides an initial Cu-Sn intermetallic layer, while the Ag finish and OSP coating allows the formation of the initial Cu-Sn intermetallic during the reflow cycle. Drop test results for assemblies as-built and as a function of aging at 125 degC are correlated with cross-sectional analysis of the solder joints. The mean number of drops to failure decreases by approximately 80% with aging at 125 degC through 480 h. Voids develop at the Cu-Sn intermetallic-to-Cu interface during high-temperature aging, but the crack path is through the intermetallic layer and does not propagate from void-to-void. Thus, it can be concluded that the voids do not contribute to the decrease in drop test survivability observed in this study

Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.

High-performance thin-film transistors with amorphous indium zinc oxide (IZO) films was deposited by embedding indium oxide nanocrystals (In2O3 NCs) into IZO films based on a sol-gel process. Excellent electrical properties have been demonstrated, including a field-effect mobility value of 32.6 cm2·V-1·s-1 and an on-off ratio of 107 , which were obtained at 1 mol% In2O3 NCs in amorphous IZO films. Our findings demonstrate the feasibility of low-temperature sol-gel-based oxide semiconductor transistors, which is more cost-effective compared with conventional fabrication techniques but with comparable performance.