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A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-μm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm 2 .

A 2.5GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83ps (rms) less than 0.7% of the output period. The total power dissipation is 21mW at 2.5GHz output frequency, and the core area is 0.08mm2.

The long-term bit error rate (BER) performance of partial response maximum likelihood (PRML) system using an adaptive equalizer in a perpendicular magnetic recording (PMR) channel with thermal decay is studied. A thermal decay model based on the experimental data giving the amplitude change of reproducing waveforms with the elapsed time for CoPtCr-SiO 2 PMR medium is obtained. The BER performance of PR1ML channel for the 16/17(0,6/6) run-length-limited (RLL) code is evaluated by computer simulation using the model. The relationship between the ratio Rj of the jitter-like media noise power to the total noise power at the reading point and the required SNR to achieve a BER of 10 -4 is also obtained and the performance is compared with that of the conventional equalization. The results show that the significant improvement in SNR by utilizing the adaptive equalization is recognized over all Rj compared with the conventional equalization.

This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 μm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.

High performance delay-locked loop (DLL) is key to the high data rate chip-to-chip communication, suggesting the output jitter, due to power noise, bang-bang noise, temperature-voltage drift, etc, should be properly controlled. In this paper, high speed DRAM operation can be achieved by a dual loop DLL with various novel techniques; a new counting code with hysteretic bit-transitions can remove the large DAC glitches by preventing the binary bit-transitions in the locking states. A delay buffer, which is insensitive to the power supply fluctuations, is proposed. The voltage-temperature (VT) dependencies of the feedback path and the open clock path are balanced, minimizing the VT shift of the clock. As a result, the high-speed DRAM interface with the maximized setup/hold window can be accomplished.

This paper presents a wide frequency range delay-locked loop implemented with a 0.35 μm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.

This paper describes a digital impedance controller (DIC) [I] for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23Ω to 140Ω with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is 2.26% with RQ ranging from 23 Q to 53 Ω, the same range covered by conventional scheme. The high resolution and wide range impedance control is implemented by using automatic gate voltage optimization. The amount of jitter caused by quantization error is 6.9 ps while 13.8 ps in conventional scheme. The data input valid window is 623 ps at 0.75±200 mV and maximum eye open is 641 mV meaning about 10% improvement at 1.5Gbps/pin DDR3 SRAM interface.