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Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2 × 1016 to 5 × 1019 cm−3 of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices.

Electronic transport properties of a finite (7,0) carbon nanotube (CNT) coupled to Au (111) surfaces are investigated with a fully nonequilibrium Green's functions method combined with the density functional theory. The results show that the coupling effect between the CNT and Au electrode plays an important role in the transport properties, which leads to the formation of a high plateau in the transmission spectrum around Fermi energy. In addition, the current-voltage characteristic of the (7,0) CNT coupled to Au electrodes is different from an isolated (7,0) CNT.

The high power microwave (HPM) damage effect on the AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) is studied by simulation and experiments. Simulated results suggest that the HPM damage to pHEMT is due to device burn-out caused by the emerging current path and strong electric field beneath the gate. Besides, the results demonstrate that the damage power threshold decreases but the energy threshold slightly increases with the increase of pulse-width, indicating that HPM with longer pulse-width requires lower power density but more energy to cause the damage to pHEMT. The empirical formulas are proposed to describe the pulse-width dependence. Then the experimental data validate the pulse-width dependence and verify that the proposed formula P = 55t 0.06 is capable of quickly and accurately estimating the HPM damage susceptibility of pHEMT. Finally the interior observation of damaged samples by scanning electron microscopy (SEM) illustrates that the failure mechanism of the HPM damage to pHEMT is indeed device burn-out and the location beneath the gate near the source side is most susceptible to burn-out, which is in accordance with the simulated results.

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave (HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.

The motion of current filaments in avalanching PIN diodes has been investigated in this paper by 2D transient numerical simulations. The simulation results show that the filament can move along the length of the PIN diode back and forth when the self-heating effect is considered. The voltage waveform varies periodically due to the motion of the filament. The filament motion is driven by the temperature gradient in the filament due to the negative temperature dependence of the impact ionization rates. Contrary to the traditional understanding that current filamentation is a potential cause of thermal destruction, it is shown in this paper that the thermally-driven motion of current filaments leads to the homogenization of temperature in the diode and is expected to have a positive influence on the failure threshold of the PIN diode.

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET).

A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer.

This paper presents a theoretical study of the pulse-width effects on the damage process of a typical bipolar transistor caused by high power microwaves (HPMs) through the injection approach. The dependences of the microwave damage power, P, and the absorbed energy, E, required to cause the device failure on the pulse width τ are obtained in the nanosecond region by utilizing the curve fitting method. A comparison of the microwave pulse damage data and the existing dc pulse damage data for the same transistor is carried out. By means of a two-dimensional simulator, ISE-TCAD, the internal damage processes of the device caused by microwave voltage signals and dc pulse voltage signals are analyzed comparatively. The simulation results suggest that the temperature-rising positions of the device induced by the microwaves in the negative and positive half periods are different, while only one hot spot exists under the injection of dc pulses. The results demonstrate that the microwave damage power threshold and the absorbed energy must exceed the dc pulse power threshold and the absorbed energy, respectively. The dc pulse damage data may be useful as a lower bound for microwave pulse damage data.

A novel semicircular electrode metal-semiconductor-metal (SEMSM) ultraviolet detector is modeled, investigated and characterized with a self-consistent numerical calculation method. For the purpose of model and performance verification, a comprehensive comparison of the SEMSM detector and a conventional electrode MSM detector is carried out with experimental data. The results indicate that the physical models are able to predict the enhanced device features. Moreover, the structural parameters have been adjusted appropriately to optimize the SEMSM detector. The findings show that a device with a 2 μm finger radius and 3 μm spacing exhibits outstanding characteristics in terms of a peak responsivity of 0.177 A/W at 290 nm, a maximum external quantum efficiency of over 75%, and a comparable normalized photocurrent to dark current ratio of 1.192 × 1011 W−1 at 0.3 V bias. These results demonstrate that the SEMSM detector has excellent performance for optoelectronic integrated circuit applications.

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.

An improved structure of silicon carbide metal—semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.

A two-dimensional model of a 4H-SiC metal?semiconductor?metal (MSM) ultraviolet photodetector has been established using a self-consistent numerical calculation method. The structure-dependent spectral response of a 4H-SiC MSM detector is calculated by solving Poisson's equation, the current continuity equation and the current density equation. The calculated results are verified with experimental data. With consideration of the reflection and absorption on the metal contacts, a detailed study involving various electrode heights (H), spacings (S) and widths (W) reveals conclusive results in device design. The mechanisms responsible for variations of responsivity with those parameters are analyzed. The findings show that responsivity is inversely proportional to electrode height and is enhanced with an increase of electrode spacing and width. In addition, the ultraviolet (UV)-to-visible rejection ratio is > 103. By optimizing the device structure at 10 V bias, a responsivity as high as 180.056 mA/W, a comparable quantum efficiency of 77.93% and a maximum UV-to-visible rejection ratio of 1875 are achieved with a detector size of H = 50 nm, S = 9 ?m and W = 3 ?m.

A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression. Characteristics of the device have been investigated based on physical models for material properties and improved trap models. By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate (BG-FP) structure, it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate-drain capacitance (Cgd) under a large drain voltage. A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less Cgd than a conventional FP. For microwave applications, 4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel. For high power applications, the proposed structure is able to endure higher operating voltage as well. The maximum saturation current density of 460 mA/mm is yielded. Also, the gate-lag ratio under a drain voltage of 20 V is close to 90%. In addition, 5% and 17.8% improvements in fT and fmax are obtained compared with a BG-FP MESFET in AC simulation, respectively. Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.

A study on the influence of the external resistor and the external voltage source during the injection of the electromagnetic pulse (EMP) into the bipolar transistor (BJT) is carried out. Research shows that the increase of the external resistor Rb at base makes the burnout time of the device decrease slightly, the increase of the external voltage source Vbe at base can aid the damage of the device when the magnitude of the injecting voltage is relatively low and has little influence when the magnitude is sufficiently high causing the device appearing the PIN structure damage, and the increase of the external resistor Re can remarkably reduce the voltage drops added to the device and improve the durability of the device. In the final analysis, the effect of the external circuit component on the BJT damage is the influence on the condition which makes the device appear current-mode second breakdown.

The response of a bipolar transistor (BJT) under a square-wave electromagnetic pulse (EMP) with different injecting voltages is investigated. Adopting the curve fitting method, the relationship between the burnout time, the damage energy and the injecting voltage is obtained. Research shows that the damage energy is not a constant value, but changes with the injecting voltage level. By use of the device simulator Medici, the internal behavior of the burned device is analyzed. Simulation results indicate that the variation of the damage energy with injecting voltage is caused by the distribution change of hot spot position under different injection levels. Therefore, the traditional way to evaluate the trade-off between the burnout time and the injecting voltage is not comprehensive due to the variation of the damage energy.