Search

In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage (V dd ), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2. A hybrid self-assembled monolayer/aluminum oxide (AlO x ) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping technique and gate stack technology, we experimentally realized a high gain of 9 at V dd of 0.5 V in the WSe2 CMOS inverter. This study paves the way for the research and development of transition metal dichalcogenides-based devices and circuits.

This study reposts the fabrication of top-gate molybdenum disulfide (MoS2) field-effect transistor (FET) by the transfer printing of a gate dielectric in conjunction with a poly(vinyl-alcohol) (PVA) coating for carrier doping. The spin-coated PVA film increases the carrier concentration in MoS2, while the back-gate MoS2 FET cannot be turned off. The transferred top-gate structure with the PVA coating makes it possible to turn off the fabricated device without permanent damage to MoS2. The results of this study suggest interesting directions for the research and development of two-dimensional material-based functional devices.

We demonstrate chip-level integrated n-type metal–insulator–semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.

This study describes the transfer printing of an Al2O3 gate dielectric for the fabrication of a top-gate MoS2 FET. The transfer printing of the Al2O3 gate dielectric involves the peeling-off process, etching of the sacrificial layer, and stacking on the MoS2. This method eliminates the direct deposition of Al2O3 gate dielectric on fragile MoS2 and provides an abrupt Al2O3/MoS2 interface. The fabricated FET has small hysteresis, low leakage current, a subthreshold slope of 120 mV dec−1, and a carrier mobility of 7.3 cm2 V−1 s−1. The transfer printing approach is applicable to various high-k gate dielectrics and layered materials for constructing functional devices.

The effect of remote Coulomb scattering on electron mobility in W/La2O3/Si gate stacked metal-oxide-semiconductor field-effect transistors (MOSFETs) was studied. Experimental results show that scattering caused by the Coulomb charges located near the W/La2O3 interface becomes a dominant factor for the mobility of MOSFETs with an equivalent oxide thickness (EOT) of 1 nm or less.

The electrical characteristics of molecular-beam-deposited HfO2/n-InAs/InGaAs metal–oxide–semiconductor capacitors with different postdeposition annealing (PDA) temperatures (400–550 °C) are investigated. Results show that the sample with the PDA temperature of 500 °C exhibits the best capacitance–voltage (C–V) behavior with small frequency dispersion and small hysteresis. The X-ray photoelectron spectroscopy (XPS) spectra show the reduction of the amount of As-related oxides to below the XPS detection level when the PDA temperature is up to 500 °C. As the PDA temperature was increased to above 500 °C, As and In atoms seem to diffuse significantly into HfO2, resulting in the degradation of C–V behavior.