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The SAR imaging processor is an essential part in SAR system to produce the final SAR image quality that used for various remote sensing applications. In this paper, we propose the design and describe the development of onboard SAR image processor based on LEON3 softcore multiprocessor implemented on FPGA board. The proposed SAR image processor is targetted to used for future onboard Unmanned Aerial Vehicle (UAV) and microsatellite of Josaphat Microwave Remote Sensing Laboratory (JMRSL). The system-on-chip (SoC) approach has been used for highly configurable, easy to integrate with other IP core through an AMBA on-chip bus and low-cost implementation. The open hardware LEON3 multiprocessor has been configured to meet the system requirement to aim at high-performance processing. The implementation of the proposed SAR image processing is targetted on an Altera Cyclone IV FPGA family and Xilinx Artix-7 FPGA AC701 Evaluation Kit. The RDA algorithm is implemented as software to run on the LEON3 Multiprocessor, and the functionality validated using the ALOS PALSAR raw data. The preliminary results show that the functionality of the system successfully works and can compress the SAR raw data into an SAR image, whereas the processing speed needs to be improved. The proposed design promises to answer the problem of SAR image processing in the future with a low price.

This paper proposes a novel phase error compensation algorithm for the direct digital synthesizer (DDS) chirp generator of high-resolution synthetic aperture radar (SAR). The proposed compensation algorithm adopts the curve fitting method to calculate the error of transmission SAR signal called chirp. In addition, this paper proposes the polynomial modeling method during chirp generation stage to improve spectrum characteristics. The mathematical equations proposed in this paper indicate that the phase shift of chirp in time domain can be eliminated clearly. Simulation results show that the proposed compensation algorithm enhances the peak-to-side lobe ratio (PSLR) and the integrated side ratio (ISLR) up to -0.2068 dB and -0.1091 dB respectively. In addition, spur components have been reduced when compared to the spectrum output of conventional DDS output.

This paper proposes a novel phase error compensation algorithm for the direct digital synthesizer (DDS) chirp generator of high-resolution synthetic aperture radar (SAR). The proposed compensation algorithm adopts the curve fitting method to calculate the error of transmission SAR signal called chirp. In addition, this paper proposes the polynomial modeling method during chirp generation stage to improve spectrum characteristics. The mathematical equations proposed in this paper indicate that the phase shift of chirp in time domain can be eliminated clearly. Simulation results show that the proposed compensation algorithm enhances the peak-to-side lobe ratio (PSLR) and the integrated side ratio (ISLR) up to -0.2068 dB and -0.1091 dB respectively. In addition, spur components have been reduced when compared to the spectrum output of conventional DDS output.

The SAR imaging processor is an essential part in SAR system to produce the final SAR image quality that used for various remote sensing applications. In this paper, we propose the design and describe the development of onboard SAR image processor based on LEON3 softcore multiprocessor implemented on FPGA board. The proposed SAR image processor is targetted to used for future onboard Unmanned Aerial Vehicle (UAV) and microsatellite of Josaphat Microwave Remote Sensing Laboratory (JMRSL). The system-on-chip (SoC) approach has been used for highly configurable, easy to integrate with other IP core through an AMBA on-chip bus and low-cost implementation. The open hardware LEON3 multiprocessor has been configured to meet the system requirement to aim at high-performance processing. The implementation of the proposed SAR image processing is targetted on an Altera Cyclone IV FPGA family and Xilinx Artix-7 FPGA AC701 Evaluation Kit. The RDA algorithm is implemented as software to run on the LEON3 Multiprocessor, and the functionality validated using the ALOS PALSAR raw data. The preliminary results show that the functionality of the system successfully works and can compress the SAR raw data into an SAR image, whereas the processing speed needs to be improved. The proposed design promises to answer the problem of SAR image processing in the future with a low price.

This paper proposes a novel phase error compensation algorithm for the direct digital synthesizer (DDS) chirp generator of high-resolution synthetic aperture radar (SAR). The proposed compensation algorithm adopts the curve fitting method to calculate the error of transmission SAR signal called chirp. In addition, this paper proposes the polynomial modeling method during chirp generation stage to improve spectrum characteristics. The mathematical equations proposed in this paper indicate that the phase shift of chirp in time domain can be eliminated clearly. Simulation results show that the proposed compensation algorithm enhances the peak-to-side lobe ratio (PSLR) and the integrated side ratio (ISLR) up to -0.2068 dB and -0.1091 dB respectively. In addition, spur components have been reduced when compared to the spectrum output of conventional DDS output.

The SAR imaging processor is an essential part in SAR system to produce the final SAR image quality that used for various remote sensing applications. In this paper, we propose the design and describe the development of onboard SAR image processor based on LEON3 softcore multiprocessor implemented on FPGA board. The proposed SAR image processor is targetted to used for future onboard Unmanned Aerial Vehicle (UAV) and microsatellite of Josaphat Microwave Remote Sensing Laboratory (JMRSL). The system-on-chip (SoC) approach has been used for highly configurable, easy to integrate with other IP core through an AMBA on-chip bus and low-cost implementation. The open hardware LEON3 multiprocessor has been configured to meet the system requirement to aim at high-performance processing. The implementation of the proposed SAR image processing is targetted on an Altera Cyclone IV FPGA family and Xilinx Artix-7 FPGA AC701 Evaluation Kit. The RDA algorithm is implemented as software to run on the LEON3 Multiprocessor, and the functionality validated using the ALOS PALSAR raw data. The preliminary results show that the functionality of the system successfully works and can compress the SAR raw data into an SAR image, whereas the processing speed needs to be improved. The proposed design promises to answer the problem of SAR image processing in the future with a low price.

This paper proposes a novel phase error compensation algorithm for the direct digital synthesizer (DDS) chirp generator of high-resolution synthetic aperture radar (SAR). The proposed compensation algorithm adopts the curve fitting method to calculate the error of transmission SAR signal called chirp. In addition, this paper proposes the polynomial modeling method during chirp generation stage to improve spectrum characteristics. The mathematical equations proposed in this paper indicate that the phase shift of chirp in time domain can be eliminated clearly. Simulation results show that the proposed compensation algorithm enhances the peak-to-side lobe ratio (PSLR) and the integrated side ratio (ISLR) up to -0.2068 dB and -0.1091 dB respectively. In addition, spur components have been reduced when compared to the spectrum output of conventional DDS output.

The SAR imaging processor is an essential part in SAR system to produce the final SAR image quality that used for various remote sensing applications. In this paper, we propose the design and describe the development of onboard SAR image processor based on LEON3 softcore multiprocessor implemented on FPGA board. The proposed SAR image processor is targetted to used for future onboard Unmanned Aerial Vehicle (UAV) and microsatellite of Josaphat Microwave Remote Sensing Laboratory (JMRSL). The system-on-chip (SoC) approach has been used for highly configurable, easy to integrate with other IP core through an AMBA on-chip bus and low-cost implementation. The open hardware LEON3 multiprocessor has been configured to meet the system requirement to aim at high-performance processing. The implementation of the proposed SAR image processing is targetted on an Altera Cyclone IV FPGA family and Xilinx Artix-7 FPGA AC701 Evaluation Kit. The RDA algorithm is implemented as software to run on the LEON3 Multiprocessor, and the functionality validated using the ALOS PALSAR raw data. The preliminary results show that the functionality of the system successfully works and can compress the SAR raw data into an SAR image, whereas the processing speed needs to be improved. The proposed design promises to answer the problem of SAR image processing in the future with a low price.

This paper proposes a novel phase error compensation algorithm for the direct digital synthesizer (DDS) chirp generator of high-resolution synthetic aperture radar (SAR). The proposed compensation algorithm adopts the curve fitting method to calculate the error of transmission SAR signal called chirp. In addition, this paper proposes the polynomial modeling method during chirp generation stage to improve spectrum characteristics. The mathematical equations proposed in this paper indicate that the phase shift of chirp in time domain can be eliminated clearly. Simulation results show that the proposed compensation algorithm enhances the peak-to-side lobe ratio (PSLR) and the integrated side ratio (ISLR) up to -0.2068 dB and -0.1091 dB respectively. In addition, spur components have been reduced when compared to the spectrum output of conventional DDS output.

The SAR imaging processor is an essential part in SAR system to produce the final SAR image quality that used for various remote sensing applications. In this paper, we propose the design and describe the development of onboard SAR image processor based on LEON3 softcore multiprocessor implemented on FPGA board. The proposed SAR image processor is targetted to used for future onboard Unmanned Aerial Vehicle (UAV) and microsatellite of Josaphat Microwave Remote Sensing Laboratory (JMRSL). The system-on-chip (SoC) approach has been used for highly configurable, easy to integrate with other IP core through an AMBA on-chip bus and low-cost implementation. The open hardware LEON3 multiprocessor has been configured to meet the system requirement to aim at high-performance processing. The implementation of the proposed SAR image processing is targetted on an Altera Cyclone IV FPGA family and Xilinx Artix-7 FPGA AC701 Evaluation Kit. The RDA algorithm is implemented as software to run on the LEON3 Multiprocessor, and the functionality validated using the ALOS PALSAR raw data. The preliminary results show that the functionality of the system successfully works and can compress the SAR raw data into an SAR image, whereas the processing speed needs to be improved. The proposed design promises to answer the problem of SAR image processing in the future with a low price.

This paper presents the development of unmanned aerial vehicle (UAV) -based Circularly Polarized Synthetic Aperture Radar (CP-SAR) raw data processing system for the experimental JX-2 UAV. First, we present the design and outline of CP-SAR system, followed by derivation of resolution and raw data rate value from axial ratio and geometry. Following the signal processing requirements, we propose to use mobile heterogeneous platform for on-board raw SAR data processing system. Then we describe the raw data processing steps based on Range-Doppler Algorithm for stripmap mode UAV SAR. Experiment results using a middle-end CPU-GPU mobile heterogeneous hardware development kit with CUDA programming interface and raw data input from actual UAV mission demonstrate the capability of the proposed mobile heterogeneous platform for SAR processing on-board JX-2 UAV.

This paper presents the development of unmanned aerial vehicle (UAV) -based Circularly Polarized Synthetic Aperture Radar (CP-SAR) raw data processing system for the experimental JX-2 UAV. First, we present the design and outline of CP-SAR system, followed by derivation of resolution and raw data rate value from axial ratio and geometry. Following the signal processing requirements, we propose to use mobile heterogeneous platform for on-board raw SAR data processing system. Then we describe the raw data processing steps based on Range-Doppler Algorithm for stripmap mode UAV SAR. Experiment results using a middle-end CPU-GPU mobile heterogeneous hardware development kit with CUDA programming interface and raw data input from actual UAV mission demonstrate the capability of the proposed mobile heterogeneous platform for SAR processing on-board JX-2 UAV.

This paper presents the development of unmanned aerial vehicle (UAV) -based Circularly Polarized Synthetic Aperture Radar (CP-SAR) raw data processing system for the experimental JX-2 UAV. First, we present the design and outline of CP-SAR system, followed by derivation of resolution and raw data rate value from axial ratio and geometry. Following the signal processing requirements, we propose to use mobile heterogeneous platform for on-board raw SAR data processing system. Then we describe the raw data processing steps based on Range-Doppler Algorithm for stripmap mode UAV SAR. Experiment results using a middle-end CPU-GPU mobile heterogeneous hardware development kit with CUDA programming interface and raw data input from actual UAV mission demonstrate the capability of the proposed mobile heterogeneous platform for SAR processing on-board JX-2 UAV.

This paper presents the development of unmanned aerial vehicle (UAV) -based Circularly Polarized Synthetic Aperture Radar (CP-SAR) raw data processing system for the experimental JX-2 UAV. First, we present the design and outline of CP-SAR system, followed by derivation of resolution and raw data rate value from axial ratio and geometry. Following the signal processing requirements, we propose to use mobile heterogeneous platform for on-board raw SAR data processing system. Then we describe the raw data processing steps based on Range-Doppler Algorithm for stripmap mode UAV SAR. Experiment results using a middle-end CPU-GPU mobile heterogeneous hardware development kit with CUDA programming interface and raw data input from actual UAV mission demonstrate the capability of the proposed mobile heterogeneous platform for SAR processing on-board JX-2 UAV.

This paper presents the development of unmanned aerial vehicle (UAV) -based Circularly Polarized Synthetic Aperture Radar (CP-SAR) raw data processing system for the experimental JX-2 UAV. First, we present the design and outline of CP-SAR system, followed by derivation of resolution and raw data rate value from axial ratio and geometry. Following the signal processing requirements, we propose to use mobile heterogeneous platform for on-board raw SAR data processing system. Then we describe the raw data processing steps based on Range-Doppler Algorithm for stripmap mode UAV SAR. Experiment results using a middle-end CPU-GPU mobile heterogeneous hardware development kit with CUDA programming interface and raw data input from actual UAV mission demonstrate the capability of the proposed mobile heterogeneous platform for SAR processing on-board JX-2 UAV.

A circularly polarized antenna array was designed for use with an airborne C-band synthetic aperture radar (SAR) measurement system. SAR performance parameters were designed and used as the performance requirements of the array antenna. A single patch antenna was first designed to conform to the required operating frequency and axial ratio for circular polarization. This was then followed by the linear array and feed design. Several important antenna performance parameters customized for our SAR measurements were achieved in this study. Among them are low axial ratio of under 3dB with 125 MHz bandwidth via corner truncated square patches for circular polarization; steep scanning angle of 40 degrees using phased delayed 10-element array at 0.53 lambda element spacing; suppressed side-lobe level utilizing the Dolph-Chebyshev synthesis method; and reduced radiation from spurious feeds through optimized feed network using T-junctions and mitered bends. The antenna performance was estimated, followed by full electromagnetic wave simulation at each design step. The optimized design was used for fabrication of the antenna and the array antenna performance parameters was verified through measurements in an anechoic chamber. Results show agreement between theoretical and simulated data which match the design parameters. A planar array structure is also proposed to increase the total array gain.

A circularly polarized antenna array was designed for use with an airborne C-band synthetic aperture radar (SAR) measurement system. SAR performance parameters were designed and used as the performance requirements of the array antenna. A single patch antenna was first designed to conform to the required operating frequency and axial ratio for circular polarization. This was then followed by the linear array and feed design. Several important antenna performance parameters customized for our SAR measurements were achieved in this study. Among them are low axial ratio of under 3dB with 125 MHz bandwidth via corner truncated square patches for circular polarization; steep scanning angle of 40 degrees using phased delayed 10-element array at 0.53 lambda element spacing; suppressed side-lobe level utilizing the Dolph-Chebyshev synthesis method; and reduced radiation from spurious feeds through optimized feed network using T-junctions and mitered bends. The antenna performance was estimated, followed by full electromagnetic wave simulation at each design step. The optimized design was used for fabrication of the antenna and the array antenna performance parameters was verified through measurements in an anechoic chamber. Results show agreement between theoretical and simulated data which match the design parameters. A planar array structure is also proposed to increase the total array gain.

A circularly polarized antenna array was designed for use with an airborne C-band synthetic aperture radar (SAR) measurement system. SAR performance parameters were designed and used as the performance requirements of the array antenna. A single patch antenna was first designed to conform to the required operating frequency and axial ratio for circular polarization. This was then followed by the linear array and feed design. Several important antenna performance parameters customized for our SAR measurements were achieved in this study. Among them are low axial ratio of under 3dB with 125 MHz bandwidth via corner truncated square patches for circular polarization; steep scanning angle of 40 degrees using phased delayed 10-element array at 0.53 lambda element spacing; suppressed side-lobe level utilizing the Dolph-Chebyshev synthesis method; and reduced radiation from spurious feeds through optimized feed network using T-junctions and mitered bends. The antenna performance was estimated, followed by full electromagnetic wave simulation at each design step. The optimized design was used for fabrication of the antenna and the array antenna performance parameters was verified through measurements in an anechoic chamber. Results show agreement between theoretical and simulated data which match the design parameters. A planar array structure is also proposed to increase the total array gain.

A circularly polarized antenna array was designed for use with an airborne C-band synthetic aperture radar (SAR) measurement system. SAR performance parameters were designed and used as the performance requirements of the array antenna. A single patch antenna was first designed to conform to the required operating frequency and axial ratio for circular polarization. This was then followed by the linear array and feed design. Several important antenna performance parameters customized for our SAR measurements were achieved in this study. Among them are low axial ratio of under 3dB with 125 MHz bandwidth via corner truncated square patches for circular polarization; steep scanning angle of 40 degrees using phased delayed 10-element array at 0.53 lambda element spacing; suppressed side-lobe level utilizing the Dolph-Chebyshev synthesis method; and reduced radiation from spurious feeds through optimized feed network using T-junctions and mitered bends. The antenna performance was estimated, followed by full electromagnetic wave simulation at each design step. The optimized design was used for fabrication of the antenna and the array antenna performance parameters was verified through measurements in an anechoic chamber. Results show agreement between theoretical and simulated data which match the design parameters. A planar array structure is also proposed to increase the total array gain.

A circularly polarized antenna array was designed for use with an airborne C-band synthetic aperture radar (SAR) measurement system. SAR performance parameters were designed and used as the performance requirements of the array antenna. A single patch antenna was first designed to conform to the required operating frequency and axial ratio for circular polarization. This was then followed by the linear array and feed design. Several important antenna performance parameters customized for our SAR measurements were achieved in this study. Among them are low axial ratio of under 3dB with 125 MHz bandwidth via corner truncated square patches for circular polarization; steep scanning angle of 40 degrees using phased delayed 10-element array at 0.53 lambda element spacing; suppressed side-lobe level utilizing the Dolph-Chebyshev synthesis method; and reduced radiation from spurious feeds through optimized feed network using T-junctions and mitered bends. The antenna performance was estimated, followed by full electromagnetic wave simulation at each design step. The optimized design was used for fabrication of the antenna and the array antenna performance parameters was verified through measurements in an anechoic chamber. Results show agreement between theoretical and simulated data which match the design parameters. A planar array structure is also proposed to increase the total array gain.