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In state-of-art digital systems the control device, which usually has a sequential structure, is one of the most important units. Moore finite state machine (FSM) is often used to implement such schemes. While implementing a digital system based on FPGA chips at the design stage of the FSM circuit there is a problem of optimizing the characteristics of its circuit. These characteristics include hardware costs (semiconductor element area occupied by the FSM circuit), speed, and power consumption. Methods of solving this problem depend on the features of the FSM and the circuitry. The features of the Moore FSM are 1) the presence of classes of pseudo-equivalent states and 2) the absence of direct dependence of outputs on inputs. Features of FPGA are: 1) the presence of embedded memory blocks EMB, that can be configured, and 2) a very limited number of inputs of the table type LUT (look-up table). This work aims to develop a method for reducing the number of tabular elements in the circuit of Moore FSM, taking into account both the features of the Moore FSM and the circuitry on which the implementation of the digital system control device is realized. A method for optimizing the cost of equipment in the circuit of the Moore FSM, which is implemented on a mixed basis of LUT and EMB elements, is proposed. The method is based on the use of classes of pseudo-equivalent states of the Moore FSM and it is advisable to use it if the developer of the circuit of the control device can use only a limited number of EMB blocks. It is proposed to present the state code in the form of a concatenation of state class codes and element codes of these classes. Such an approach reduces requirements for the number of EMB inputs. The conditions of application of the proposed method are shown. An example of the synthesis of the circuit of the FSM using the proposed method is given. [ABSTRACT FROM AUTHOR]

In advance digital systems, implemented using various VLSI circuits, an important issue remains to reduce the area of the circuit, which is occupied by the control device, and, consequently, reduce the delay time and the amount of power consumption. As a rule, reducing the area of the circuit of the control device allows improving its other characteristics. Methods for solving this problem to some extent depend on the features of the implemented control algorithm and element basis. The article proposes a method for reducing the number of LUT (Look-Up-Table) elements in the scheme of a composition microprogram control unit (CMCU), based on converting the addresses of the outputs of linear operator circuits (LOC) into output codes. This transformation reduces the number of inputs of the addressing scheme of microinstructions, which is especially important when implementing the circuit of the control device on the FPGA basis due to the small number of inputs of elements of the tabular type LUT. The outputs of the LOC are encoded as elements of some classes of partitioning the set of outputs. This approach allows you to move from a multi-level microinstruction addressing scheme to a two-level one. The control memory and the address conversion block are implemented on embedded memory blocks. The proposed method is an adaptation of the method of double coding of states of Miles automata to the features of CMCU. The method is advisable to use if the microinstruction addressing unit is represented by a multi-level scheme. This is possible if the number of arguments in the memory excitation functions exceeds the number of LUT inputs. If the bit width of the microinstruction address exceeds the number of LUT inputs, then the address converter block circuit is also multilevel. Analysis of standard automata from the library and the Virtex 7 basis showed that this method can be applied to 68% of the library elements. The article considers an example of the synthesis of a CMCU circuit using the proposed method. [ABSTRACT FROM AUTHOR]

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