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High performance infrared focal plane arrays (FPAs) play a critical role in a wide range of imaging applications. However the high cost associated with the required cooling and serially processed die-level hybridization is major barrier that has thwarted Mid-wavelength Infrared (MWIR) detector technology from penetrating largevolume, low-cost markets. Under the Defense Advanced Research Projects Agency (DARPA) WIRED program, the HRL team has developed a wafer level integration schemes to fabricate large format Antimonidebased MWIR FPAs on Si Read Out Integrated Circuit (ROIC) as a means to achieve significant fab cost reduction and enhanced production scalability. The DARPA-hard challenge we are addressing is the thermal and stress management in the integration of two dissimilar materials to avoid detector and ROIC degradation and to maintain structure integrity at the wafer scale. In addition, a digital ROIC with extremely large well capacity was designed and taped-out, in order to increase the operating temperature of the FPAs. In this talk, we discuss our progress under the DARPA WIRED program.

Single walled carbon nanotubes have garnered substantial interest in the electronic materials research community due to their unparalleled intrinsic electrical properties. In addition, their mechanical robustness and thin geometries make SWNTs ideal candidates for transparent electronics. Aligned arrays of SWNTs grown via chemical vapor deposition (CVD) on quartz enable device uniformity and wafer scale integration with existing commercial semiconductor processing methods. A crucial roadblock in incorporation of SWNTs in commercial electronics has been the co-existence of metallic and semiconducting SWNTs. Demanding device metrics in high performance and complex integrated electrical devices, sensors, and other applications dictate the necessity of pristine, purely semiconducting arrays of SWNTs. By exploiting a novel process in nanoscale flow of thin film organic coatings, we have demonstrated a method to purify as-grown aligned arrays to produce such as result. Comparison with single nanotube statistics, characterization using a novel thermal scanning probe microscopy technique, as well as corroboration with thermal modeling validated the result. Thin film field effect transistors exhibiting mobilities exceeding ~1000cm 2 /Vs and on/off ratios exceeding 10,000 were fabricated using the purified semiconducting SWNTs. This manuscript reviews some of these results, which represent the first successful demonstration of purification of aligned arrays of SWNTs, in a robust and scalable scheme that allows integration of aligned arrays into complex, high performance electrical devices. We separately also describe new results on the advanced development of soft lithography techniques with the ability to transfer print aligned arrays of SWNTs onto transparent substrates after synthesis and processing, thereby completing a direct pathway to achieve complex, high performance, and highly integrated transparent SWNTs electronics, sensors, or other devices.

This paper presents a review of recent work on high speed tunable and fixed wavelength vertical cavity surface emitting lasers (VCSELs) at Chalmers University of Technology. All VCSELs are GaAs-based, employ an oxide aperture for current and/or optical confinement, and emit around 850 nm. With proper active region and cavity designs, and techniques for reducing capacitance and thermal impedance, our fixed wavelength VCSELs have reached a modulation bandwidth of 23 GHz, which has enabled error-free 40 Gbps back-to-back transmission and 35 Gbps transmission over 100 m of multimode fiber. A MEMS-technology for wafer scale integration of tunable high speed VCSELs has also been developed. A tuning range of 24 nm and a modulation bandwidth of 6 GHz have been achieved, enabling error-free back-to-back transmission at 5 Gbps.

A simple and low-cost technology for tunable vertical-cavity surface-emitting lasers (VCSELs) with curved movable micromirror is presented. The micro-electro-mechanical system (MEMS) is integrated with the active optical component (so-called half-VCSEL) by means of surface-micromachining, using a reflown photoresist droplet as sacrificial layer. The technology is demonstrated for electrically pumped, short-wavelength (850nm) tunable VCSEts. Fabricated devices with 10 mu m oxide aperture are singlemode with sidemode suppression >35 dB, tunable over 24 mit with output power up to 0.5 mW, and have a beam divergence angle

Using wafer scale optics, wafer scale integration, and wafer level packaging of image sensor, we developed small form factor (3.3mm×3.3mm×2.4mm), low manufacturing cost, Pb-free solder reflow compatible digital camera modules which are suitable for many applications including mobile electronic devices, automotives, security, and medical applications.

While silica waveguide PLC products have been deployed in various systems and applications, hybrid integration of semiconductor opto-electronic devices on silica-based planar lightwave circuit (PLC) has become the mainstream platform for small form factor, low-cost and high volume integrated transceiver modules. One of the main benefits of hybrid integration is the wafer-scale process, which greatly reduces chip/module size and assembly cost. This paper reviews the development of this technology, and as an example, presents a hybrid integrated transmitter with four wavelengths on silica PLC chip for LX4 and 10GbE applications.

Design and fabrication of thin film GaAs Grating-Assisted Resonant-Cavity LEDs (GA-RCLED) emitting at 980 nm are reported. The devices are fabricated by gluing the sample and a transfer substrate with benzocyclobutene (BCB) and consequently thinning the sample. The design is optimised for a high extraction efficiency. The efficiency of substrate emitting planar RCLEDs is limited by leaky DBR modes. This quasi continuum of modes does not fall in the DBR stop band and is internally reflected at the semiconductor-air interface. Consequently, the leaky modes are absorbed in the substrate and are lost. The use of a thin film device can avoid this loss term. The laterally propagating mode can be recuperated by the use of a grating. The diffractive properties of the periodic grating can redirect the resonant guided mode to the extraction cone. The 2-D grating is defined on the surface of the thin film RCLED by means of holographic exposure. As the devices are thinned they are more compatible with wafer scale integration with electronic devices.

The potential and limits of micromoulding technology for the wafer scale hybrid integration of micro-optic elements on top of arbitrary substrates like glass, Silicon, III/V-semiconductors by a process which is performed in a modified contact mask aligner. The elements are characterised by high precision and stability, temperature stable and precise pitch, index, homogeneity, uniformity across the wafer, and they fulfill additional requirements for a practical application (AR-coating, separation in a dicing saw). Additionally, the technology for a two- sided replication of elements has been developed. The precision of lens arrays fabricated by reflow and UV-moulding is investigated, and the high performance of these arrays in the collimation of fiber arrays is shown. Steps toward a wafer scale integration of lens arrays with vertical cavity surface emitting lasers (VCSELs) by locally selective replication are demonstrated.

A new vertical chip integration is proposed, based on the UTCS concept. It consists in stacking thinned chips on top of a silicon substrate. Lateral and vertical metal interconnections and the thinned chips are embedded in BCB layers. This wafer scale integration technique is presented. Thermal behavior of such stacked structure is also discussed.

With higher complexity of optical networks there is an increasing demand for components which allow to manipulate the optical signals without conversion to the electronic domain. Besides modulation the key functions needed for advanced telecom applications are multiplexing and demultiplexing in the time and frequency domains, wavelength filtering, routing, switching, dispersion equalising. This paper describes the state-of-the art of planar guided wave circuits (integrated optical devices) made from SiO 2 , InP, LiNbO 3 and polymers, which are going to replace discrete components based on fibres, thin film technologies and bulk optics. Special emphasis will be put on scalability and the capability for higher monolithic or hybrid integration. As wafer scale integration, i.e. one circuit occupies a whole wafer, has been reached for specific components such as high channel count arrayed waveguide grating devices (Phasars) and switch matrices, new device structures which consume less real estate have to be elaborated.

A replication technique allowing for the wafer scale integration of microoptical elements is presented and illustrated by various examples. The technique is based on polymer UV reaction moulding using a modified contact mask aligned where mask and wafer are replaced by the replication tool and an arbitrary substrate, respectively. The technology takes advantage of the high precision and adjustment accuracy of photolithography equipment. The replication masters are nickel shims, etched Silicon wafers or uv-transparent fused silica tools. The latter ones allow for replication on opaque substrates. Additionally, polymer elements with unique properties can be obtained by the combination of replication and resist technology using partially transparent replication tools. Wafer scale hybrid integration of microoptical subsystems is accomplished by replication of polymer elements like lenses, lens arrays, micro prisms etc. onto semiconductor wafers containing detectors or VCSELs, or by combining microoptical elements on both sides of a glass wafer. The use of thin layers of uv cured polymers on inorganic substrates results in good thermal and mechanical stability compare to all-polymer devices.

System alignment is often the cost driver in the production of optical system. In order to both miniaturize and reduce production costs, wafer scale integration of active and passive components is required. This integration relies on a host of techniques to align and bond active and passive devices into a monolithic structure. Moreover, this initial packaging is accomplished while the optics and supporting structures are in wafer form, thereby providing parallel fabrication with resultant cost savings. This paper describes the fundamental techniques for producing IMOS from wafer scale substrates. The relative merits of each approach are discussed, along with design concerns for successful application. Two example systems are discussed, each using a different fabrication technique.

Wafer scale integration (WSI) lithography is the technique used to fabricate ultra large scale integration (ULSI) integrated circuits significantly greater in size than current products. Applications for WSI lithography include large solid state detector arrays, large area liquid crystal displays, high speed mainframe supercomputers, and large random access memories. The lithography technology required to manufacture these devices is particularly challenging, requiring stringent control of both submicron critical dimensions and accurate alignment of level to level device patterns over large chip areas.

A discontinuity has developed between the densities available with ULSI circuits and printed circuit board assemblies. Multichip module (MCM) technologies are poised to bridge that gap. Properly designed 3-D MCMs can deliver the compact size and high-speed of near wafer scale integration but notwithout significant electro-mechanical design challenges. This paper explores the natural constraints shaping future high speed interconnect design. 1. The Problem The transmission of subnanosecond signals alone is not difficult. Difficulties arise when one attempts to assemble multiple circuits into a system that need to transfer information at subnanosecond speeds. The system design puzzle in figure [1] depicts the problem faced by computer designers . '' Success is measured by how cost effectively one is able to interconnect and integrate the processor cache main memory data I/O cooling and the DC power system. Solutions to this challenge are evolving at a revolutionary pace. The subnanosecond pulse shown in figure [2] is representative of the information signals transferred between logic circuits of the system. Signal rise and fall times of less than 100 picoseconds are common today. One could slow down the pulse edge rise time to alleviate current switching problems while sacrificing system performance. Lowering voltage swings will also assist with the current switching demands. 2. The System Volume All the components that go into a system occupy space. Less space translates into hiher speeds and lower materials costs.© (1991) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

SUMMARY The Westinghouse WSI program for the development of complete signaland data processors is driven top—down by study and understandingof systems needs. An important result of the project is a generalpackaging scheme called "Dual Composite Technology" (DCT). Evolu-tionary research and development of DCT has progressed to the pointof experimental verification of key aspects of the approach.Sufficient data has been accumulated to confirm that DCT is ther-mally efficient, rugged, and has significant potential for reduc-tion of the size and weight of modular electronics. Power andsignal distribution are managed by using multilevel flat cableswhich make contact directly to the top surface of the wafers. Cost,reliability and performance benefits are expected as an intrinsiccharacteristic of the simplified nature of DCT modular structures. 6 . ACKNOWLEDGEMENT Some portions of the Westinghouse WSI development program have beenfunded by government contracts. Much of the early work was par—tially sponsored by AFWL/NTC, Kirtland AFB, NM. The technical moni-tor was Lt. Raymond Ord.

HWSI''s impact on the size weight power cost speed and reliability of advanced systems is well recognized. Using the HWSI designers have profound opportunity to create innovative components and systems. However the HWSI so far is not accessible to most of them because of its high cost in prototyping and low-volume manufacturing. To solve this problem a proposal is being studied to develop a compact integrated prototyping center which delivers semi-custom HWSI modules within hours after the design is finished. The center conducts three major tasks: 1) fabricating interconnects by optical scanning and chemical etching 2) developing a solder mask by optical scanning and 3) soldering flip-chip assemblies by pickandplace and reflow. Through system simulation the proposed design for the center requires only eight automated units while maintaining a reasonable prototyping turn-around time (5 hours for the first module and 13 hours for a batch of 20 modules) . The corresponding packaging cost for each 1 inch square module ranges from $150 to $500 depending on the annual prototyping volume. A!© (1991) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Theoretical and practical considerations for optimized laser microsurgery on semiconductor devices are presented and discussed. Various commercially available lasers suitable for microsurgery are described, although the present work centers around the use of a xenon laser. Along with a thorough discussion of the xenon lasers operating characteristics, a number of novel xenon laser-based failure analysis techniques developed in the wafer scale integration program at Trilogy Systems Corp. are reported. Over the past 10 to 15 years, laser technology has been used in semiconductor manufacturing technology to solve an increasing number of problems to which it is uniquely suited. Lasers have been successfully used in the areas of photomask repair, resistor trimming, cutting of redundant circuit links, laser formed connections, and failure analysis (1-4). The property of laser technology which makes it so useful is the ability to apply a relatively uniform dose of photonic energy (0.01 - 1.5 mJ) in a very short time (1nS - 1.5µS) to the microscopic areas of interest in integrated circuits (1 Am2 - 100 Am2) using more or less standard optical components. In this paper, several laser based techniques which have proven exceptionally useful in the production of fully functional wafer scale integrated circuit prototypes at Trilogy Systems Corp. are reported as well as the results of a study of the operating characteristics of the Florod L.F.A. xenon laser system used in this study.

The recent resurgence of interest in Wafer Scale Integration (WSI) is driven by a requirement for dense multilayer interconnect at wiring capacities far in excess of that which is achievable in ceramic hybrid packages. All of the problems associated with achieving satisfactory yield in such structures must now be reexamined to see whether the current technology is capable of achieving what has proven so elusive in the past. One of the relevant technologies is direct write electron beam lithography. Initially. efforts are being directed at fabricating wire at rather large dimensions (5-10 pm) with similar wire separations. At these dimensions. good clean room practices should be adequate to fabricate about 20-70 meters of fault-free wire on 97% of the wafers. However. longer wire lengths encounter some defects with higher probability. The IBM EL-2 electron beam lithography system available at the Rensselaer Center for Integrated Electronics is capable of achieving discretionary wafer wide wire patterning because it can be used in direct write to wafer mode with excellent registration and low stitching error. The availability of this tool eliminates the cost of plate making and permits the use of adaptive wafer wire rework for repair. In this paper we examine some of the strategies and technical issues associated with E-Beam patterning of wafer length interconnections.

A novel CAD system for use in the manufacture of high resolution chrome masks for wafer scale integrated optic devices is described. The etching of titanium waveguide structures is considered and it is demonstrated that SF6, plasma etching techniques can be used to advantage. The packaging requirements of water scale integrated optic structures are out-lined and a novel fibre attachment technique described.