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In this paper, the analytical modeling of surface potential, threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) of negative capacitance (NC) silicon nanotube FETs (SiNTFETs) are presented. The surface potential model is obtained by solving the 3D Poisson's equation in cylindrical coordinates with the suitable boundary conditions in the channel region. The impact of the drain coupling capacitance (Cd) on the internal gate voltage (Vint) is included in the model as it influences the performance of NC FETs. Negative DIBL property resulting from the NC effect is demonstrated with the help of surface potential and threshold voltage modeling. The thickness of the ferroelectric (tfe) and ferroelectric parameter (α) are varied to observe the impact of NC on device performance. The threshold voltage (Vth) roll-off and subthreshold swing (SS) of NC SiNTFET are presented at variable channel length (L). A minimum SS of 46.81 mV/decade is obtained in the range of L with a tfe of 2 nm which is well below the Boltzmann limit of 60 mV/decade. A positive Vth roll-off is observed in NC SiNTFETs with a tfe of 2 nm at a higher drain voltage (Vds) of 0.7 V owing to negative DIBL. The model results are in good agreement with the TCAD simulation results. [ABSTRACT FROM AUTHOR]

Dielectric Pocket Packed Double-Gate-All-Around ( D P P - D G A A ) MOSFETs are one of the preferred choices for ULSI applications because of significantly low off-current, reduced power dissipation, and high immunity to short channel effect. However, D P P - D G A A suffer from self-heating due to the unavailability of appropriate heat take-out tracks. This Paper analysis the effect of self-heating (SHEs) for D P P - D G A A MOSFETs by electro-thermal (ET) simulations with hydrodynamic and thermodynamic transport models. The electrothermal characteristics against various device dimensions such as spacer size, device width,thermal resistance of the contacts, and drain voltage have been investigated. The effect of SHE on the drive current has also been evaluated. Further, Self-heating impacts on thermal noise have been analyzed in detail using Sentauras TCAD simulator. [ABSTRACT FROM AUTHOR]

In this paper, a multivariable non-linear regression is used to predict the influence of key device parameters core radius (tc) and channel length (L) on device performance of silicon nanotube FET (Si NTFET). The sensitivity of the device for tc and L is assessed in terms of variation in threshold voltage (VTH), subthreshold swing (SS), ON current (ION), and OFF current (IOFF). A TCAD assisted machine learning (ML) approach is developed for the training and testing of ML algorithms. A dataset of 4641 samples is created from the simulation of device structure by varying two crucial input parameters, core radius (tc) and channel length (L). The output parameters, VTH, SS, ION, and IOFF are extracted from the simulated transfer characteristics. 70% of the dataset is used for algorithm training and the remaining 30% is used for testing. The random forest (RF) regressor and gradient boosting (GB) regressor algorithms are adopted and compared their performance. The GB regressor algorithm offered the best prediction under the training phase which is further used for testing purposes. For GB regressor, mean square error (MSE) of 3.13 × 10−10 V, 0.1019 mV/decade, 6.40 × 10−13A, and 2.85 × 10−16A is achieved under testing for VTH, SS, ION, and IOFF, respectively. A measurable impact on ION and IOFF of the device is noticed with a change in tc from 2 to 7 nm for considered L of 10 nm to 100 nm. [ABSTRACT FROM AUTHOR]

In nanoscale FETs, the confined geometry and increased packaging density induce increased power density, which translates into larger heat generation. The substrate's low thermal conductivity also leads to poor heat dissipation, leading to a further rise in temperature and aggravated self-heating effects (SHEs). The incessant scaling of transistor size demands a rigorous study on the impact of SHEs and ambient temperature variations on advanced MOSFET structures' electrical characteristics. Therefore, in this work, an investigation on the electro-thermal (ET) behaviour of the nanoscale RingFET has been conducted using the Sentaurus TCAD device simulator. The hydrodynamic carrier transport model has been used in 3-D ET simulations to analyze the ET behaviour of the RingFET. A comparative analysis of the DC characteristics with and without SHEs has been presented via current-voltage and transconductance-voltage characteristics, which are further used to compute the ZTC (zero temperature coefficient) bias point. A detailed analysis of the device's electrical behaviour with the variation in channel length, gate oxide thickness, substrate doping, and drain radius has also been presented. Finally, the influence of SHEs on device characteristics at various ambient temperatures has also been reported. [ABSTRACT FROM AUTHOR]

The dielectric pocket gate-all-around (DPGAA) MOSFET is being considered the best suited candidate for ULSI electronic chips because of excellent electrostatic control over the channel. However, the phenomena of self-heating and hot carrier injection (HCI) severely affect the performance of the device, and make the behaviour of the DPGAA FET very unpredictable. In the present article, a comprehensive investigation under the influence of self-heating effects has been done for the variation in the lattice and carrier temperature against spacer length, ambient temperature, device length, and thermal contact resistance including ON and Off currents with gate bias voltage (VGS). In order to analyse the SHEs, the hydrodynamic (HD) and thermodynamic (TD) transport models have been used for three-dimensional (3D) electrothermal (ET) simulation. The Lucky (hot carrier injection) model has been used to study the HCI degradation in DPGAA MOSFET using Sentaurus 3D TCAD simulator. [ABSTRACT FROM AUTHOR]

Self-heating effects (SHE) in silicon-on-insulator (SOI) based tri-gate junctionless field effect transistor (TG-JLFET) due to low thermal conductivity of buried oxide (SiO2) is studied in this paper. Self-heating results in degradation of drain current due to reduced mobility and also negative differential conductance (NDC) is seen in saturation region. This paper shows that substrate bias voltage can dynamically reduce self-heating and NDC in TG-JLFETs. The analysis is carried out by three-dimensional TCAD simulation using Sentaurus device simulator. [ABSTRACT FROM AUTHOR]

In this paper, 2-D analytical models of channel central potential, threshold voltage, subthreshold current and subthreshold swing for graded channel double gate (GC-DG) Junctionless FETs (JLFETs) have been presented. The 2-D Poisson's equation has been solved to determine the channel central potential by parabolic approximation method with appropriate boundary conditions. The minimum potential for the channel is obtained from the channel potential expression in order to formulate threshold voltage, subthreshold current and subthreshold swing. The validity of the model results has been verified using TCAD numerical data obtained from 2-D ATLAS device simulator from Silvaco. [ABSTRACT FROM AUTHOR]

In this work, a threshold voltage model of Tri-Gate Schottky-Barrier (TGSB) MOSFET is presented by coupling threshold voltage models of symmetric and asymmetric double-gate Schottky-Barrier (SB) MOSFET structures giving due weight to each structure. The electrostatic potentials of double-gate SB MOSFETs are obtained using evanescent mode analysis method considering light doping in the channel region. In TGSB MOSFETs, the leakiest path in the subthreshold regime of device operation is located at the mid of the bottom of the channel region. The minimum potential of this leakiest path is considered to be the virtual cathode potential, which is subsequently used to calculate the threshold voltage of the SB MOS devices. The effects of device parameters like oxide thickness, buried oxide (BOX) thickness, channel height, width, and length, doping concentration and Schottky-Barrier height on threshold voltage have been extensively studied in this work. The proposed model results have been verified with numerical simulation results obtained from the 3-D device simulator of Sentaurus TCAD. [ABSTRACT FROM AUTHOR]

Objective: Type I collagen polypeptides contribute significantly to the structural composition of ligament tissue matrix. Since anterior cruciate ligament (ACL) tears account for roughly 50% of all knee injuries in sports, the objective of the study was to investigate association of Sp1-transcription factor binding site polymorphism COLIA1 Sp1 + 1245 G > T with ACL injury risk among Indian athletes. Methods: A total of 166 athletes (90 with ACL tears and 76 as control) were recruited and were genotyped for COLIA1 Sp1 + 1245 G > T polymorphism using allele-specific PCR (AS-PCR) method. Result: Both the groups were matched for nature of sports, training regimen, and other demographic characteristics. We observed no significant difference between ACL cases and control group in GT or TT genotype frequency distribution (p = 0.967) and T-allele frequency distribution (p = 0.861) for COLIA1 Sp1 + 1245 G > T polymorphism. Also, the three models of inheritance of minor allele failed to show any statistical significance in the present study. Conclusion: COLIA1 Sp1 + 1245 G > T polymorphism has been studied in relation to many connective tissue pathologies. This is probably the first study to investigate the association of collagen protein genes with ACL injury risk on Indian athletes. Further studies with more SNPs in genes encoding fibril-forming collagen and large sample sizes are necessary to fully understand the genetic link to ACL injuries among athletes. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs) is presented. The threedimensional (3D) Poisson equation in cylindrical coordinates has been solved with suitable boundary conditions to find the surface potential along the channel length. The inversion charge density (Qinv) has been calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship. Subsequently, the calculated inversion charge density (Qinv) has been equated to a threshold charge density (Qth) in order to find the threshold voltage (Vth) expression. The effect of physical device parameters, including the tube thickness, on the threshold voltage and drain induced barrier lowering (DIBL) of the device has been discussed. The model results have been verified with the simulation data obtained by the device simulation software ATLAS. [ABSTRACT FROM AUTHOR]

Many major rival models of the origin of the Hindu caste system co-exist despite extensive studies, each with associated genetic evidences. One of the major factors that has still kept the origin of the Indian caste system obscure is the unresolved question of the origin of Y-haplogroup R1a1*, at times associated with a male-mediated major genetic influx from Central Asia or Eurasia, which has contributed to the higher castes in India. Y-haplogroup R1a1* has a widespread distribution and high frequency across Eurasia, Central Asia and the Indian subcontinent, with scanty reports of its ancestral (R*, R1* and R1a*) and derived lineages (R1a1a, R1a1b and R1a1c). To resolve these issues, we screened 621 Y-chromosomes (of Brahmins occupying the upper-most caste position and schedule castes/tribals occupying the lower-most positions) with 55 Y-chromosomal binary markers and seven Y-microsatellite markers and compiled an extensive dataset of 2809 Y-chromosomes (681 Brahmins, and 2128 tribals and schedule castes) for conclusions. A peculiar observation of the highest frequency (up to 72.22%) of Y-haplogroup R1a1* in Brahmins hinted at its presence as a founder lineage for this caste group. Further, observation of R1a1* in different tribal population groups, existence of Y-haplogroup R1a* in ancestors and extended phylogenetic analyses of the pooled dataset of 530 Indians, 224 Pakistanis and 276 Central Asians and Eurasians bearing the R1a1* haplogroup supported the autochthonous origin of R1a1 lineage in India and a tribal link to Indian Brahmins. However, it is important to discover novel Y-chromosomal binary marker(s) for a higher resolution of R1a1* and confirm the present conclusions.Journal of Human Genetics (2009) 54, 47–55; doi:10.1038/jhg.2008.2; published online 9 January 2009 [ABSTRACT FROM AUTHOR]

The present paper is about using three popular performance boosters in a device to battle with deterioration in device characteristics imposed by temperature variation. The dielectric pocket (DP) technology has been utilized in double gate-all-around MOSFET to limit the leakage current problem. Further, high-K dielectric as gate oxide is employed so that ON-state current may be improved with enhanced device scalability. The boosted immunity towards short-channel effects (SCEs) and improvement in the device's analog performance is demonstrated through comparison between dielectric pocket high-K double Gate-All-Around (DP-DGAA) and double Gate-All-Around (DGAA) MOSFETs with temperature variation from 300 to 500 K by using commercially available ATLAS, a three-dimensional (3D) device simulator from SILVACO. [ABSTRACT FROM AUTHOR]