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Object detection using convolutional neural networks (CNNs) has garnered a lot of interest due to their high performance capability. Yet, the large number of operations and memory fetches to both on-chip and external memory needed for such CNNs result in high latency and power dissipation on resource constrained edge devices, hence impeding their real-time operation from a battery supply. In this paper, a resource and cost efficient hardware accelerator for CNN is implemented on an FPGA. Using an existing metric DSP efficiency and a new metric Cost efficiency as the primary optimization variables, exploration of algorithms and hardware using a design space exploration tool, called ZigZag, is undertaken. An optimized architecture is implemented on a Xilinx XC7Z035 FPGA and tiny-YOLOv2 is mapped to demonstrate the real-time object detection application. Compared to the state-of-the-art (SotA), the implementation results shows that the hardware achieves the best DSP efficiency at 90% and Cost efficiency at 0.146. [ABSTRACT FROM AUTHOR]

With the massive growth of wireless networks comes a bigger impact of collisions and interference, which has a negative effect on throughput and energy efficiency. To deal with this problem, we propose an in-band wireless collision and interference detection scheme based on full-duplex technology. To study its performance, we compare its throughput and energy efficiency with the performance of traditional half-duplex and symmetric in-band full-duplex transmissions. Our analysis considers a realistic protocol and overhead modeling, and a measurement-based self-interference model. Our results indicate that our proposed collision detection scheme can provide significant gains in terms of throughput and energy efficiency in large wireless networks. Moreover, when compared to half-duplex and symmetric full-duplex, our analysis shows that this scheme allows up to 45% more nodes in the network for the same energy consumption per bit. These results suggest that this could be an enabling technology towards efficient, dense wireless networks. [ABSTRACT FROM AUTHOR]

Low power analog-to-digital converters (ADCs) in energy constrained devices, such as wireless sensor readout modules, often target dynamic resolution scalability with application context to reduce the average power consumption. This work implements such an 8-12-bit resolution scalable ADC, using an oversampling and noise-shaping successive approximating register (SAR) architecture. This architecture is selected for its high power efficiency after a detailed comparison of various resolution enhancing techniques within the SAR framework. Specifically, in this paper, three resolution enhancing techniques are reviewed and compared on their energy usage namely: the majority voting, the oversampling, and the oversampling with noise shaping SAR ADC. Furthermore, the proposed resolution scalable ADC simplifies the design of the noise shaping filter by enabling the use of a first order switched-capacitor low-pass filter for shaping the comparator noise and the in-band quantization noise. The ADC design also alleviates the matching concerns by using only an 8-bit capacitive digital-to-analog converter (DAC) for a maximum 12-bit resolution, or 11-bit effective number of bits (ENOB). The architecture can be configured to allow an operation from 8-bit traditional SAR ADC up to an 11-bit ADC by enabling the oversampling and noise shaping loops within the SAR architecture. This ADC is designed to operate with up to 320 kS/s and achieves a power scaling from 80 nW to 1.5 μW, resulting in an steeper energy-ENOB scaling trend compared to state-of-the art resolution scalable ADCs. [ABSTRACT FROM AUTHOR]

This paper presents an energy-efficient digital front-end processor for digital-intensive polar transmitter architecture working on 60 GHz band in standard 28nm CMOS process. This avoids modulating the supply and also eliminates the need of an additional RF limiter and AM detection circuits in the traditional analog-centric polar transmitter architecture. The design challenges on the digital signal processing (DSP) front-end are analyzed and tackled. The systematic optimizations are first explored to minimize the design requirements on the DSP front-end. A pulse shaping filter is designed to shape the frequency spectrum of the quadrature signals so that the signal at the output of the filter is compliant with the spectrum mask requirements. Instead of using computation-intensive raised cosine filter for the pulse shaping, we use poly-phase Cascaded Integrator-Comb (CIC) filter to shape the spectrum. Parallel rotation and vectoring COordinate Rotation DIgital Computers (CORDICs) are designed to perform rectangular-to-polar conversion. Furthermore, a pre-distortion circuit based on look-up table (LUT) is designed to compensate the power amplifier (PA) nonlinearities. Taylor’s approximation is explored to avoid the complex trigonometric computation in the pre-distortion. Finally, an efficient latch-based pipeline is studied to provide the required 7.04 Gsps throughput with less than 60 mW. The synthesis results compare favorably with previously reported architectures. [ABSTRACT FROM AUTHOR]

The ever improving cost advantages and processing capabilities of the technology have been happening according to the so-called Moore's Law. Although digital circuits can significantly benefit from the aggressive scaling, it is very controversial for analog circuit. However, analog circuit still has to follow the scaling trend because a single chip integration offers key commercial advantages. To optimally achieve the best performance/power/cost tradeoff with deeply scaled technology nodes, there is a clear trend and paradigm shift towards digital intensive and digitally assisted transceivers. Successes of such transceivers have been proven for individual transceiver components and narrow band systems. When targeting emerging communication standards, higher carrier frequencies, further technology scaling and reconfigurable radios, required signal processing design and implementation are orders of magnitudes more challenging but potential gains are promising. Based on a variety of transceiver designs implementing emerging architectures for different sub-6 GHz and 60 GHz communication systems, we will highlight the key challenges and opportunities experienced using 40 nm and 28 nm technology nodes. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in $$0.13 \,\upmu \hbox {m}$$ CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only $$113\, \upmu \hbox {W}$$ during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved. [ABSTRACT FROM AUTHOR]