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This paper investigates the problem of a decoupled disturbance compensator (DDC) based stochastic sliding mode control (SMC) design for discrete linear time-invariant systems. In the developed method, the actual disturbance is estimated using the DDC method to design the control input and stabilize the system. The proposed method allows the disturbance compensation to be modified separately from the control input, since the two inputs of system are completely decoupled. To demonstrate the effectiveness of the DDC based discrete-time stochastic SMC, its performance is compared with that of the existing methods using the simulation results. Finally, experimental results are presented to demonstrate the effectiveness of the proposed method.

This paper proposes a deep reinforcement learning (deep RL) method for simultaneously designing several notch filters in complex industrial servo systems. Notch filters are highly effective for suppressing resonances in motion control systems and are widely utilized in industry. However, severe limitations exist in complex servo systems because there are many vibration modes that are difficult to identify. In such cases, several notch filters must be used, but the task of tuning these filters involves lengthy empirical procedures by well-experienced engineers. To automate this tuning process, this paper proposes a novel design method that can design several notch filters simultaneously for the first time. In this method, a deep deterministic policy gradient (DDPG) algorithm with a vector stability margin as the reward function is utilized to find filter parameters in the frequency domain. The proposed method simultaneously finds a set of many parameters for several notch filters that are optimal with respect to stability. Using a real industrial servo system that has multiple resonances, it is demonstrated that the proposed method effectively finds the optimal parameters for several notch filters and successfully suppresses multiple resonances to provide desired performances.

In this paper, a low-power 12-bit successive approximation register (SAR) resistance-to-digital converter (RDC) for resistive microsensors with a figure-of-merit (FoM) of 33 pJ/conversion-step is presented. In the conventional resistive analog front-end (AFE), two-step conversion schemes, including a resistance-to-voltage converter and a voltage-to-digital converter are generally used. The presented SAR RDC can directly convert the resistance changes to digital codes. The proposed SAR RDC consists of a comparing stage, and a SAR operating stage. The preamplifier of comparing stage implements a correlated double sampling (CDS) technique to improve the low-noise characteristic and reduce the low-frequency flicker (1/f) noise. The RDC is designed using SAR scheme to achieve low-power consumption. The SAR RDC achieves a wide input resistance range of 2 MΩ. The SAR RDC is implemented with a 0.18 μm standard complementary metal–oxide–semiconductor (CMOS) process with an active area of 0.35 mm2. All functional blocks, including voltage and current references, oscillators, and timing generators, are integrated on the chip. The proposed RDC consumes 93.2 μW with 1.8 V power supply. The experimental results of the proposed SAR RDC achieve 11.3-bit resolution within a conversion time of 0.92 ms and a figure-of-merit (FoM) of 33 pJ/conversion-step.

This paper proposes a 164 nW inverter-based capacitive readout integrated circuit (IC) for a microaccelerometer. The designed circuit is implemented using a two-stage inverter-based fully differential current-reuse amplifier to achieve ultra-low power consumption. In order to obtain low magnitudes of current consumption, supply voltage and noise characteristic, the amplifier in the capacitive sensing chain is designed using two cascaded current-reuse inverter stages for both high DC gain and output swing. The low-voltage current-reuse two-stage amplifier configuration with resistive common mode feedback can effectively reduce the power consumption. Two passive resistive common mode detectors and an error amplifier constitute the common mode feedback to enhance the operating range. The correlated double sampling technique is also employed to reduce the flicker (1/f) noise. The IC chip is fabricated using a 0.18-µm 1P6M CMOS process, with an active area of 1.74 mm2, and it consumes an extremely low amount of power, 164 nW at a supply voltage of 0.7 V. The input-referred noise floor of the readout IC is measured to be 4.75 aF/√Hz.

This paper presents a new discrete derivative method for adaptive notch filter (ANF)-based frequency estimators. ANF-based frequency estimators are widely used for online frequency estimation because of their small computation requirements and simple structures. A discrete-time derivative is usually required for the estimators because they are implemented in the discrete-time domain. However, conventional discretization processes may cause problems in calculating the derivative of the adaptive filter state. For example, a derivative needs to have a phase of 90°, but finite difference methods produce phase responses that are less than 90° in high-frequency ranges. This phenomenon causes inaccurate frequency estimation results in high-frequency ranges. A bilinear transform method can prevent the phase problem, but it has oscillating transient responses, which deteriorate the convergence properties of the estimated frequency. A new discrete derivative method that modifies the bilinear transform is proposed. The proposed method does not produce the oscillating transient response in the steady state. Moreover, the phase responses of this method remain at 90° even in high-frequency ranges. Therefore, the frequency estimators that use the proposed derivative method can accurately estimate the frequencies of input signals in various frequency ranges.

This paper presents a capacitive analog front-end (AFE) integrated circuit (IC) with a dual-mode automatic parasitic cancellation loop. Capacitive AFEs are widely used for various capacitive microsensors based on micro-electro-mechanical system technologies. This paper presents a capacitive AFE IC with a dual-mode automatic parasitic cancellation loop. The capacitive AFE adopts the correlated double-sampling technique for low-noise characteristics. The automatic parasitic cancellation loop removes the unwanted offset caused by the input parasitic capacitances by implementing a successive approximation register scheme. The automatic parasitic cancellation loop includes two parts: a capacitor domain cancellation loop and a charge domain cancellation loop. The capacitor domain loop and charge domain loop execute coarse parasitic and fine parasitic cancellations, respectively. The chip is fabricated using the 0.18-μm complementary metal–oxide–semiconductor process and has an active area of 2.39 mm2. With the dual-mode parasitic cancellation loop, the input parasitic capacitance, ranging from −10.6 to 10.6 pF, can be cancelled with a resolution of 0.224 fF. The measured automatic offset cancellation time is lower than 14 ms. The power consumption is 928 μW with a 3.3 V supply.

This paper presents a novel method for estimating the heading angle of a home service robot. The images captured from a forward viewing mono-camera, gyroscope data, and wheel encoder data are used as sensory inputs. The data rates of camera, gyroscope, and encoder are 1 Hz, 50 Hz, and 50 Hz, respectively. The camera is slightly tilted by 16.5° to increase the amount of visual information obtained. The context of this study is simultaneous localization and mapping (SLAM) in an indoor home environment. The ceiling lines, i.e., the intersection between the ceiling and wall, are used as the only landmarks for the heading angle estimation. In our method, since the ceiling lines are used as the sole landmarks, line parameterization and data association problem can be simplified when compared to the general line based methods. In home environment, the ceiling line features can be easily detected regardless of the robot rotation. The developed method can be used to accurately estimate the global heading angle while the robot is in motion. A ceiling line map is also reconstructed. The reconstructed ceiling line map provides intuitively understandable spatial information about the environment using only a few features. The experimental results demonstrate that it is feasible to use the proposed method for an indoor home environment.

The concepts of microrobots has been drawn significant attentions recently since its unprecedented applicability in nanotechnology and biomedical field. Bacteria attached microparticles presented in this work are one of pioneering microrobot technology for self-propulsion or producing kinetic energy from ambient for their motions. Microfluidic device, especially utilizing laminar flow characteristics, were employed for anisotropic attachment of Salmonella typhimurium flagellated chemotactic bacteria to 30 um × 30 um and 50 um × 50 um microparticles that made of biodegradable polymer. Any toxic chemicals or harmful treatments were excluded during the attachment process and it finished within 100 s for the anisotropic attachment. The attachments were directly confirmed by fluorescent intensity changes and SEM visualization. Chemotaxis motions were tracked using aspartate and the maximum velocity of the bacteria-attached microrobot was measured to be ~5 um/s which is comparable to prior state of art technologies. This reusable and scalable method could play a key role in chemotaxis delivery of functional microparticles such as drug delivery system.

This paper presents a low noise accelerometer microsystem with a highly configurable capacitive interface circuit. A programmable capacitive readout circuit is designed to minimize the offset and gain error due to the parasitic capacitance mismatch and the process variations. The interface circuit is implemented in a 0.5 μm 2P3M CMOS technology with EEPROM. The interface circuit and MEMS sensing element are integrated in a single package, and consist the accelerometer microsystem. The supply voltage and supply current of the system are 5 V and 1.17 mA, respectively. The input range and gain are 2.5 V and 0.5 V/g, respectively. The max---min gain error and max---min offset error after calibration was measured to be 1.2% FSO and 3.3% FSO, respectively. The signal to noise ratio (SNR) and noise equivalent resolution (NER) are measured to be 93.1 dB and 110.6 μg/?Hz, respectively, when a 40 Hz, 5 g sinusoidal input acceleration is applied.

This paper deals with lane assignment problem in the automated highway systems (AHS). The purpose of lane assignment strategies is to increase the throughput on multi-lane highways with many entry and exit points, based on the itineraries of vehicles using the highway (point of entry, time of entry and exit point) and effects of maneuvers. Using the partitioned lane assignment strategies, the lane assignment problem is formulated as an optimal problem to find proper positions of partitions on an itinerary matrix. Then the optimal problem is solved with genetic algorithm (GA). The validation of the proposed algorithm is conducted by comparing it with a random strategy in a realistic situation.

Quantum information processing (QIP) has become a hot research topic as evidenced by S. Haroche and D. J. Wineland receiving the Nobel Prize in Physics in 2012. Various MEMS-based microfabrication methods will be a key enabling technology in implementing novel and scalable ion traps for QIP. This paper provides a brief introduction of ion trap devices, and reviews ion traps made using conventional precision machining as well as MEMS-based microfabrication. Then, microfabrication methods for ion traps are explained in detail. Finally, current research issues in microfabricated ion traps are presented. The QIP renders significant new challenges for MEMS, as various QIP technologies are being developed for secure encrypted communication and complex computing applications.

Polysilicon films deposited by low pressure chemical deposition (LPCVD) are the most widely used structural material for microelectromechanical systems (MEMS). However, the structural properties of LPCVD polysilicon films are known to vary significantly, depending on deposition conditions as well as post-deposition processes. This paper investigates the effects of phosphorus doping and texture on Young's modulus of polysilicon films. Polysilicon films are depostied at 585°C, 605"C, and 625°C to a thickness of 2µm. Specimens with varying phosphorus doping levels are prepared by diffusion doping at various temperatures and times using both POCl3 and phosphorsilicate glass (PSG) as the source. Texture is measured using an X-ray diffractometer. Young's modulus is calculated by taking the average of the values calculated from the resonant frequencies of four-different size lateral resonators. Our results show that Young's modulus of diffusion doped polysilicon films decreases with increasing doping concentration, and increases with increasing texture.