Search

With ever increasing use and the number of users on the internet, data has become vulnerable to attacks. One such attack is Denial of Service (DoS) attack. This attack is meant to temporarily or indefinitely make unavailable a machine or network resources thereby making the system inaccessible. In this paper, an intrusion detection system is built using Deep Learning approaches Deep neural network and Convolutional Neural Network to detect DoS attacks. CICIDS2017 dataset is used to train the model and test the performance of the model. The experimental trials show that the proposed model outperforms all the previously implemented models.

VLSI technology has eulogistically grown over the years. This has been made feasible due to continuous scaling of technology. Miniaturization of technology and conscientious demand of high-speed applications have resulted in dense and compact packaging of on-chip interconnects and devices. Copper has been widely used as an on-chip interconnect material in VLSI chips. However, copper is constrained by the grain and surface boundary scattering effects at scaled technology nodes that limit its utility and further incorporation in futuristic integrated circuit (IC) designs. Subsequently, carbon-based on-chip interconnects have been investigated and proven to be one of the effective alternatives to conventional copper interconnects. The present work vividly explores and investigates carbon nano-materials that can be used for high-speed VLSI interconnects. The other important entanglement with on-chip interconnect is that its parasitic increases and henceforth output performance degrades as the length of wiring over IC increases. This can be eminently alleviated using prospective booster insertion in between on-chip interconnects. The elegant booster insertion technique for prosperous carbon interconnects has been marginally explored till date and henceforth taken up in this work. This paper meticulously investigates various system characteristics such as delay, power dissipation, crosstalk, signal integrity, eye diagram for different interconnect materials such as copper, carbon-based CNTs and GNRs. It is observed that carbon interconnects impressively outperform in terms of delay, power, crosstalk and high-speed operation than conventional copper interconnects.

The floating-point (FP) addition is the most frequently used FP operation. Here we are using single-electron transistor (SET) for floating-point addition. This research aims to implement a 32-bit binary floating-point adder with IEEE 754 standard using SET. In floating-point arithmetic, FP addition is the most difficult activity and it offers more delay and more power consumption. Here we are comparing SET and CMOS-based (16 nm) floating-point adder. SET-based FP adder consumes very less power and also very less delay. For simulation and verification, CADENCE virtuoso is used. According to our results, SET-based FP addition has 79.70% improvement in power and 97.67% faster than CMOS-based FP.

A smart soldier health monitoring system using embedded electronics and wireless communications is presented to keep real-time track of conditions of all the soldiers on the battlefield. A wireless body area network (WBAN) is created by treating each soldier as a node and each node consists of different sensors monitoring the condition of that particular soldier which could be integrated inside a uniform or a bulletproof jacket. The attributes tracked by the system are motion and physiological health of the soldier and the environment. After gaining the knowledge of these attributes, the control room can take decisions accordingly and create an effective battle strategy.

Interconnects are densely laid as multiple layers in ICs and play a dominant role in characterizing the system performance. At nanodimensions, variability and reliability in interconnects become a dominant concerning issue. Variability analysis can be accomplished using several statistical mathematical techniques, such as Monte-Carlo, parametric, process corner, ANOVA and rank table analyses. However, these conventional techniques are becoming obsolete and deficient in determining the severe variability effects of the sophisticated, densely packed and enormously large on-chip interconnects. Moreover, traditional techniques are tremendously computational-expensive. Henceforth, in the present paper, prospective neural network-based back-propagation technique is incorporated to capture the effect of highly variable parameters that are existing in on-chip interconnects. Back-propagation neural network (BPNN) is used along with Levenberg–Marquardt (LM) algorithm to adjust weights of hidden layer in order to minimize error. The proposed model is efficient and versatile such that it predicts the reliability of the circuit performance based on input parameters, such as interconnect resistance, inductance and capacitance. The performance parameter considered for the developed model is mean square error. The obtained results exhibit high accuracy and adaptability. The accuracy of the proposed model is assessed through regression, error and histogram plots.

Electronic devices are the basic building blocks in integrated circuits. Silicon-based devices are dominating the VLSI industry since decades. However, with miniaturization of the technology, quantum effects aggregate extensively at nano-dimensions, and silicon-based devices are harder to scale down than tens of nanometer. As a result, traditional silicon FETs at nano-era are becoming less significant. The rise of nano-era and recent research trends have shown that graphene and related materials (GRMs) are emerging as promising candidates for future devices. In this chapter, the physics governing the graphene material is discussed. Thereafter, analytical model of graphene FET (GFET) is presented. Further, advanced GFET is explored, and the high end novel GFET-based inverter and adder circuits are implemented using HSPICE. To investigate the GFET performance efficiency, a comparative analysis has also been made with respect to conventional SiFET devices. The technology node considered for SiFET is 22 nm for the various analyses presented in the chapter.

The present paper analyzes process, voltage and temperature variation effects in current-mode (CM) interconnect system. CM signaling is considered as one of the advanced signaling schemes and effective in achieving high performance in integrated circuits. The impact of variability has been accessed using technology scaling, parametric and process corner analyses. It is analyzed that FF process corner model is the fastest while SS model results in least power dissipation in the circuit. Parametric sensitivity analysis reveals that variation in threshold voltage and supply voltage dominantly impacts the propagation delay and power dissipation, respectively, in the system. The variability effects in CM interconnect system are analyzed for scaled technology nodes from 130 to 32 nm. SPICE is used for simulative analyses.

This paper presents a single-precision floating point (IEEE 754 standard) matrix multiplier module. This is constructed using subblocks, which include floating point adder and floating point multiplier. These subblocks are designed to achieve the goal of low power consumption. Different architectures of subblocks are compared on the basis of energy-delay product. Design and simulations have been performed for 180 and 45 nm technology node. Simulation results show that design of floating point matrix multiplier is better at 45 nm than 180 nm technology node in terms of lesser delay by 43% and energy-delay product by 97.86% at 1 V. Also, 45 nm technology cells occupy only 6.25% of the area as compared to 180 nm cells.

Bundled single-wall carbon nanotube (SWCNT) interconnects have been investigated as one of the prominent replacements to copper interconnects in nano-scale regime. This paper investigates the performance of SWCNT bundle interconnect using current-mode signaling (CMS) scheme. Time-domain analytical model is derived for CMS SWCNT bundle interconnects using finite-difference time-domain (FDTD) technique. This model for the first time accurately considers the CMOS gate driver in its analytical FDTD formulation for CMS SWCNT bundle interconnects. The performance of CMS SWCNT bundle interconnect is compared with the conventional CMS copper interconnects. It is investigated that CMS SWCNT bundle interconnects have lower propagation delay than CMS copper interconnects.

This paper deals with frequency and stability response of single wall carbon nanotube bundle (SWB) and multiwall carbon nanotube bundle (MWB) at global interconnect lengths. The performance of SWB and MWB interconnects are analyzed using driver-interconnect-load system. It is analyzed that MWB interconnects are more stable than SWB interconnects. It is illustrated that stability of both SWB and MWB interconnects increases with increase in interconnect length. The analytical model for stability and frequency response using ABCD matrix has been formulated. Using frequency response, it is observed that the bandwidth of SWB and MWB interconnects are 7.94 and 22.2 GHz respectively for an interconnect length of 500 µm. The results are verified using SPICE simulations. The time delay analysis has been performed for different interconnect lengths. Further, it is investigated that delay reduces with increasing number of shells in MWB interconnect.