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Two types of low-power asynchronous comparators featured with input data statistical characteristic are proposed in this article. The asynchronous ripple comparator stops comparing at the first unequal bit but delivers the result to the least significant bit. The pre-stop asynchronous comparator can completely stop comparing and obtain results immediately. The proposed and contrastive comparators were implemented in SMIC 0.18 μm process with different bit widths. Simulation shows that the proposed pre-stop asynchronous comparator features the lowest power consumption, shortest average propagation delay and highest area efficiency among the comparators. Data path of low-density parity check decoder using the proposed pre-stop asynchronous comparators are most power efficient compared with other data paths with synthesised, clock gating and bitwise competition logic comparators. [ABSTRACT FROM PUBLISHER]

In this article, we proposed a high-speed, high fan-in dynamic CMOS comparator with low transistor count. Our approach is to construct the dynamic comparator based on the prior superiority of dynamic CMOS comparator and to further enhance its operating speed. Constructing the comparator with dynamic CMOS architecture, we can save 63.2% transistor count as compared with the conventional static CMOS design. The main contribution to accelerate the speed of dynamic comparator is to solve the problem of ‘weak 0’ existing in the PMOS of pull-down network. Instead, as an alternate to PMOS in the pull-down network, we use NMOS combined with an additional inverter in the front of the NMOS input gate. In this way, we can perform the same function as PMOS, but transmitting with both ‘good 1’ and ’good 0’. As a result, the proposed dynamic comparator can operate with lower propagation delay in the pull-down network. Finally, the proposed 64-bit dynamic comparator circuit can operate correctly under a clock frequency of 450 MHz with 0.18 µm technology while the prior circuit can only operate under 250 MHz at the same time. [ABSTRACT FROM PUBLISHER]

This paper reports the design of multi-standard sigma delta modulator with low power consideration. It uses the cascaded methodology for modulator design to reduce power dissipation and single feedback system has been used to provide higher stability. The concept of oversampling and noise shaping is used in the design of modulator to increase Signal to Noise Ratio (SNR). The OP-AMP designed has a gain of 62 dB and phase margin of 72° to make the design stable. The second order sigma delta modulator designed can be used for either GSM or WCDMA applications at a sampling frequency of 5 MHz and 20 MHz, respectively. The bandwidth of the signal considered for GSM and WCDMA is 200 KHz and 2 MHz, respectively. The SNR and dynamic range obtained for GSM is 82 dB and 71 dB, respectively, and for WCDMA the same is 62 dB and 54 dB, respectively. The multi-standard modulator is designed in standard 180 nm CMOS technology at a power supply of 1.8 V and the total power consumed is 4.867 mW. [ABSTRACT FROM AUTHOR]