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Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V. [ABSTRACT FROM AUTHOR]

As an initial block in the receiver front-end, LNA needs to achieve high gain with minimal noise at high frequencies. LNA designs at 5G communication have drawbacks such as increased noise figure, minimum gain, and poor linearity. A CMOS Low-Noise Amplifier for the frequency range of 30 GHz with optimization technique of current reuse technique and linearization technique is proposed and implemented to obtain maximum gain with reduced noise figure with improved linearity in this paper. The linearization technique improves the input of third-order intercept point ( I I P 3 ) of an LNA. The parameters, such as sufficient gain, low noise and enhanced linearity, are considered to design the LNA for wireless 5G communication. The proposed design shows an improvement in gain and lesser noise figure compared to conventional designs. The simulation results show that the proposed LNA provides a maximum gain of 20.6 dB, a noise figure of 3.1 dB and I I P 3 of 6 dB at 30 GHz with a power consumption of 6.2 mW from a supply voltage of 1.2 V. The proposed Low-Noise Amplifier is designed and simulated in the 45 nm CMOS technology. [ABSTRACT FROM AUTHOR]