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The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short‐period orbits as well as increasing the randomness of the generated bit sequences, the proposed algorithm periodically changes the seed parameters of the LCG blocks. The proposed clock divider‐based pseudorandom bit generator is compared with other LCG‐based realisations, showing great improvement. First, a clock divider is utilised for generating a maximum length of 22n pseudorandom bits for n‐bit operands size which leads to lowering the hardware cost. Secondly, it generates high‐speed random bits at a uniform clock rate with one initial clock latency. Third, the proposed technique provides good statistical properties. The proposed architecture is implemented using Verilog HDL and further prototyped on commercially available field programmable gate array (FPGA) devices Virtex‐5, Virtex‐7, and Artix‐7. The realisation of the proposed architecture in these FPGA devices accomplishes an improved data throughput and utilises minimum FPGA resources (in terms of look‐up‐tables and flip‐flops) which are compared with the existing techniques. The generated bit sequence from the experiment is further analysed briefly for sequence size and verified for randomness by using the National Institute of Standards and Technology benchmark test.

Summary A wide locking range divide-by-5 injection-locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18-μm 1P6M CMOS process. Conventional divide-by-5 ILFD has limited locking range. The proposed divide-by-5 ILFD is based on a capacitive cross-coupled voltage-controlled oscillator (VCO) with a dual-resonance resonator, which is implemented in the divide-by-5 ILFD to obtain a wide overlapped locking range. At the drain-source bias VDD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide-by-5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm2.

A system of radio over free space optic (RoFSO) system using the multi-optical carriers has been generated by the microring resonators integrating an add/drop filter. These obtained carriers have shown sufficiently stable for propagating in free space channels while experiencing very low dispersion. Moreover, this technique is appropriated for higher capacity that can be serviced in a system of wavelength-division multiplexing (WDM) RoFSO, where there are 16 carriers created, where each carrier has 12.5 GHz free spectral range (FSR) and 220 MHz full-width at half-maximum (FWHM) and 8 orthogonal frequency division multiplex (OFDM) signals, then they separately modulated with 8 out of these 16 carriers. After the modulation, by utilizing an free space optic (FSO) antenna, all carriers have the optical multiplexing and transmission to a FSO channel. On the receiver side, the demultiplexing is performed and finally the performance of the system subsequently is analyzed by calculation of the constellation diagram and error vector magnitude (EVM).

In this article, a new design of a Wilkinson power divider is presented that offers substantially improved amplitude and reduced size characteristics over a broad frequency range compared to a conventional Wilkinson power divider. The improvement in bandwidth is obtained by reducing inductance and number of lumped components in even mode. The analytical design equations for this proposed power divider are obtained using even and odd mode analysis. This power divider with a compact size is fabricated using 65 nm 1P9M CMOS technology. The measurement results show an operation bandwidth 26–40 GHz with 15 dB input, output return loss, and 0.7 dB insertion loss. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:128–131, 2017

Recently, a signal processing using positive and negative edges of clock is used by memory and various digital devices to improve performance of digital circuits. In a signal processing using double edges, 50% duty cycle of an output signal of clock generator is an important factor. In this paper, we propose the programmable divider with which we always obtain the output signal of 50% duty cycle unrelated to the division ratio. The circuit configuration of this divider is very simple, and the operation is stable regardless of the increase in the division ratio. Also, when the proposed divider was included in the division ratio changeable-digital phase locked loop DC-PLL, the output signal is always kept to 50% duty cycle regardless of the frequency of input signal. In experimental results using a field programmable gate array, we confirmed that this DC-PLL has the expected characteristics for phase error, lock-in range, and initial pull-in.

A wide locking range nMOS divide-by-2 RLC injection-locked frequency divider ILFD was designed and implemented in the TSMC 0.18-µm BiCMOS process. The ILFD is based on a cross-coupled oscillator with one direct injection MOSFET and a RLC resonator. The RLC resonator is used to extend the locking range so that dual-band locking ranges can be merged in one locking range at both low and high injection powers. At the drain-source bias of 0.9V for switching transistors, and at the incident power of 0dBm the locking range of the divide-by-2 ILFD is 7.24GHz, from the incident frequency 2.65 to 9.89GHz, the locking range percentage is 115.47%. The power consumption of ILFD core is 8.685mW. The die area is 0.726×0.930mm2. Copyright © 2016 John Wiley & Sons, Ltd.

This article presents an unequal Wilkinson power divider (UWPD) with a compact size that uses S- to Y-parameter conversion. The proposed UWPD design method involves connecting shunt reactance elements at all ports; specifically, a parallel circuit consisting of a resistor and capacitor is connected at isolation positions. To validate this method, we simulate the UWPD at center frequency of 450 MHz, with a 20° phase delay and a 3:1 power division; during the simulation, we take measurements whose characteristics agree well with the simulation results. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1655–1658, 2016

In this paper, we study an optimized block-diagonal zeroforcing (BD-ZF) precoder in two-tiered cognitive networks, consisting of a macro-cell (MC) and a small-cell (SC). By exploiting multi-user multiple input multiple outputVandermonde-subspace frequency division multi-plexing (MIMO-VFDM) transmission, a cognitive SC can coexist with an MC. We first devise a cross-tier precoder (CTP) based on the idea of Vandermonde-subspace frequency division multiplexing (VFDM) to cancel the interference from SC to MC. And then, we adopt BD-ZF intra-tier precoder (ITP) to suppress the multi-user interference among SC. In the case that the dimension of the provided null space is larger than what BD-ZF ITP requires, we develop an optimized ITP. By optimizing the rotating and selecting matrix, all limited channel gain is collected, which results in a good performance of throughput. Numerical results are presented to demonstrate the throughput improvement of the proposed optimized BDZF ITP and to discover the impact of imperfect channel state information (CSI).

This article presents theoretical design of dual band unequal power divider based on coupled line structure. The structure consists of two coupled line segments along with five transmission line segments used to satisfy unequal matching characteristic. The isolation is achieved using a circuit, which is a combination of inductor, capacitor, and resistor. Design equations of proposed power divider and the circuit providing isolation are based on circuit representation of ideal transmission lines. Simulation and measured results are given to verify the theoretical design equations. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:953–956, 2016

A new leakage-tolerant true single-phase clock dual-modulus prescaler based on a stage-merged scheme is presented. Leakage-restricting transistors are used to reduce the leakage currents at critical nodes, and leakage-related malfunctions are eliminated at minimal cost in terms of speed, power, and area overheads. An HSPICE simulation in a 40-nm process shows that the proposed divide-by-2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable with the performance levels of referenced designs. Copyright © 2016 John Wiley & Sons, Ltd.

This letter presents a wide-locking range CMOS divide-by-3 injection-locked frequency dividers (ILFD) using single-ended injection signal. The fabricated 0.18 μm CMOS ÷3 ILFD uses cross-coupled switching transistors, single-injection MOSFET, and a dual-resonance RLC resonator. The consumed power of the ÷3 ILFD core is 7.97 mW at the DC drain-source voltage 0.76 V. At an external injected signal power Pinj = 0 dBm, the measured locking range is 2.97 GHz (25.25%) from 10.28 to 13.25 GHz and the operation range is 5.17 GHz (48.5%) from 8.08 to 13.25 GHz. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2720–2723, 2015

This letter presents a three-phase VCO consisted of three identical single-ended Clapp pMOSFET VCOs coupled by a pMOSFET ring and tail inductors. The three-phase circuit operation is based on the interaction of frequency tripler and divide-y-3 injection-locked frequency divider in addition to the MOSFET-ring coupling. The fully integrated 8.5 GHz three-phase VCO was fabricated in 90 nm CMOS process, the frequency tuning range is from 8.08 to 8.94 GHz and the VCO-core power consumption is 4.04 mW at the supply voltage of 0.88 V. The measured phase noise is −117.18 dBc/Hz at 1 MHz offset frequency from the carrier frequency 8.822 GHz. The VCO occupies a chip area of 0.864 × 0.76 mm2 and provides a figure of merit of −190.1 dBc/Hz. The phase noise is reduced through optimizing capacitor value in the Colpitts negative resistance cell. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2529–2532, 2015

A five-port power divider with single-ended input and two differential-ended outputs is proposed. The frequency ranges from 9 to 11 GHz with a central frequency of 10 GHz. A stepped impedance line with open stubs is used between differential pairs for broadening the bandwidth and miniaturization of the divider. The divider is fabricated and the measurement results comply with the simulation. A proper performance for differential mode signal is achieved. The insertion loss is within 1.8 dB, the isolation is more than 15 dB, and the return loss is more than 11 dB. In addition, the common mode suppression is reached as well. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2669–2673, 2015

A novel wide locking range divide-by-4 injection-locked frequency divider ILFD is proposed in the paper and was implemented in the TSMC 0.18µm 1P6M CMOS process. The divide-by-4 ILFD uses two injection transistors in series and DC-biased above threshold voltage and a frequency doubler to enhance the function of linear mixers. At the drain-source bias of 0.9V and at the incident power of 0 dBm, the locking range of the divide-by-4 is 2.6GHz; from the incident frequency 12.2to 14.8GHz, the percentage is 19.26%. The core power consumption is 10.35mW. The die area of ILFD is 1.026×0.943mm2. Copyright © 2015 John Wiley & Sons, Ltd.

We propose a scalable support WDM-based orthogonal frequency division multiple access-passive optical network uplink transmission system using an injection-locked Fabry–Perot laser diode (IL-FP-LD). This system uses an injection-locking technique to enhance the usable bandwidth by making stable channel states. By properly controlling the IL-FP-LD operation, the number of optical network units (ONU) within a wavelength can be increased, which improves the optical bandwidth efficiency for the uplink transmission. The experimental results show an enhanced modulation bandwidth of 3.5 GHz. Compared with a conventional RSOA which has a modulation bandwidth of 1.5 GHz, our scheme improves the number of ONUs that can be accommodated within a wavelength more than two times. The total discrete multitone signal received from the ONUs, with QPSK mapping on the subcarriers was 6.77 Gbps over a 23-km standard single mode fiber transmission. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1727–1732, 2015

In this paper, a novel filtering power divider with external isolation resistors is presented. The proposed power divider can be considered as an integration of a bandpass filter and a Gysel power divider. Based on the circuit topology, a high-order filtering power divider can be easily realized. Odd- and even-mode models are employed to analyze the filtering and power splitting functions. For demonstration, a third-order filtering power divider operating at 1.5 GHz is designed and implemented. The measured results exhibit an isolation between the output ports that is better than 20 dB at around the center frequency.

A 60-GHz fundamental frequency phase locked loop (PLL) as part of a highly integrated system-on-chip transmitter with on-chip memory and antenna is presented. As a result of localized optimization approach for each component, the PLL core components only consume 30.2 mW from a 1.2 V supply. A systematic design procedure to achieve high phase margin and wide locking range is presented. The reduction of parasitic and fixed capacitance contributions in the voltage controlled oscillator enables the coverage of the complete 802.11 ad frequency band from 57.2 to 65.8 GHz. A new 4-stage distribution network supplying the local oscillator (LO) signal to the mixer, the feedback loop and the external equipment is introduced. The prescaler based on the static frequency division approach is enhanced using shunt-peaking and asymmetric capacitive loading. The current mode logic based divider chain is optimized for low power and minimum silicon foot-print. A dead-zone free phase frequency detector, low leakage charge pump, and an integrated second-order passive filter completes the feedback loop. The PLL implemented in 65 nm CMOS process occupies only 0.6 mm2 of chip space and has a measured locking range from 56.8 to 66.5 GHz. The reference spurs are lower than −40 dBc and the in-band and out-of-band phase noise is −88.12 dBc/Hz and −117 dBc/Hz, respectively. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:660–667, 2015

In this letter, we introduce a frequency division concept for passive wireless sensors utilizing the intermodulation communication principle. This concept enables multiple identifications (IDs) and multiple access protocol when several sensors are within the reading range of the corresponding reader. The ID and multiple access scheme based on frequency division is experimentally demonstrated with 10 binary passive wireless sensors operating simultaneously in the 866 MHz UHF band. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:274–277, 2015

SUMMARY This paper introduces the implementation of an application-specific complementary metal oxide semiconductor frequency division multiplexer as a novel solution to interface magnetic resonance (MR) phased arrays of micro-detectors to an image-processing unit, thus reducing the complexity and space issues associated with MR detector arrays. The frequency multiplexer, in a compact 3 × 4 mm silicon die, is designed to operate at 400 MHz, which is the Larmor frequency of 1H protons in a 9.4-T MR imaging system. The system implements eight channels, where each channel consists of a low-noise amplifier, a frequency mixer, and a band-pass filter. The maximum gain of an individual channel after the band-pass filter stage is 38 dB. The suppression of the local oscillator ranges from 40 to −51 dB, and the maximum coupling between channels is −39 dB. The input dynamic range of an individual channel is 8 mV. Each channel consumes 54 mA from a 3.3-V source. The chip operates without errors within a high 9.4-T magnetic field. Copyright © 2014 John Wiley & Sons, Ltd.

In orthogonal frequency division multiple access-passive optical network (OFDMA-PON) uplink transmission with a direct detection system, the optical beat interference (OBI) noise is a very critical issue in regard to channel performance degradation. We have proposed a novel technique to suppress the OBI noise in intensity modulation and direct detection OFDMA-PON links by using an optical spectrum broadening method using the RF-clipping tone to improve the SNR of the discrete multitone modulation (DMT) signal with OBI noise suppression. We also experimentally analyzed the dependency of the RF clipping tone on the OBI noise suppression and dither effect. The results show that the received DMT signal in the optical line terminal can achieve 3 Gb/s over a 23 km SSMF with a BER of 2.3×10−4. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2706–2711, 2014

A fully integrated 10.5-GHz divide-by-3 (1/3) injection-locked frequency divider (ILFD) that can provide extra locking range is presented. The ILFD consists of a previously measured on-chip 10.5-GHz voltage controlled oscillator (VCO) functioning as an injection source, a 1/3 ILFD core, and an output inverter buffer. A phase tuner implemented using an asymmetric inductor is proposed to increase the locking range through even-harmonic phase tuning. With a fixed internal injection signal power of only −18 dBm, a 25% enhancement in the locking range from 12 to 15 MHz is achieved with the proposed phase tuning. The proposed even-harmonic phase tuning can be used to provide extra locking range to those achieved by other techniques. The proposed integrated 1/3 ILFD has a frequency tuning range of 3.3–4.2 GHz. It is realized using a 0.18-μm BiCMOS process, occupies 0.6 mm × 0.7 mm, and consumes 10.6 mA while the ILFD core alone only consumes 6.15 mA from 1.8-V supply voltage. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2249–2252, 2014

A novel compact power divider with good frequency response and wide stopband based on composite right-/left-handed (CRLH) transmission line is presented in this article. To provide bandpass-filtering frequency response, the bandpass filtering circuits is applied to this power divider using the CRLH resonators. The bandpass filtering circuit can generate two transmission zeros at the lower and upper stopband and have a wide upper stopband. Besides, the phase shift of the CRLH filter is tuned to be 90° for the sake of replacing the conventional quarter-wave length branch line in the power divider. Moreover, the capacitive coupling between the input and output of the resonator is used simultaneously to generate three additional transmission zeros beside the passband edges. Then, the frequency selectivity of the power divider is greatly improved. A resistor is placed at the center of the symmetric plane to produce good isolation between the two outputs. A filter-integrated power divider operating at 3.7 GHz is implemented. Good agreement between the simulated and measured results is observed. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2122–2125, 2014

A 26–47.9 GHz ultrawideband CMOS dual injection-locked frequency divider (dual-ILFD) with high input impedance is demonstrated. As the differential input signal is injected into the gate of the PMOS tail transistor and NMOS switch transistor, the proposed divider has high input impedance and can be driven easily by the preceding driving circuits. Meanwhile, the locking range of the proposed divider is extended significantly by fully utilizing the dual-injection technique. The proposed dual-ILFD is fabricated in a standard 90-nm CMOS process and on-wafer measurements are performed. The measurements show that the free-running frequency of the divider is 19.11 GHz. At an incident power of 0 dBm, a total locking range from 26 to 47.9 GHz is achieved. The power consumption is 2.88 mW at a supply voltage of 1.2 V. The total chip size is 0.62 × 0.42 mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2126–2129, 2014

A wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18-μm SiGe 3P6M BiCMOS process is presented. The ÷3 ILFD circuit is realized with an n-core MOS LC-tank oscillator. The ILFD uses a push-push signal circuit and two linear mixers with one radio-frequency injection input port and one push-push signal input port. An HBT is used to amplify the push-push signal and extend locking range. The core power consumption of the ILFD core is 13.2 mW at the drain-source voltage of 0.8 V. The divider's free-running frequency is tunable from 3.079 to 3.163 GHz and at the incident power of 0 dBm, the locking range is 19.28%, from 8.9 to 10.8 GHz. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:493–497, 2014

This article presents an unequal Gysel power divider (UGPD) based on circuit transformation, which is converted from a Π- to a T-type circuit. The Π-type circuit of a conventional unequal Gysel divider consists of two different value resistors and its connection transmission line. In the proposed T-type circuit, the dummy transmission line and the other transmission line with shunt resistor at center position is connected in parallel. Theoretical analysis was performed to derive the design equations for the proposed circuit conversion. For the validation of the circuit transformation, the UGPD using a T-type circuit at the center frequency of 2 GHz was fabricated and measured. The measured characteristics agreed well with the simulation results. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1529–1531, 2015

The design of a planar in-phase power divider for wideband applications is presented. The proposed divider uses a broadside coupled microstrip/slotline configuration with an improved isolation between the output ports using suitable isolation resistor. The proposed design is suitable for single layer integration as both the input and output ports are located at the same layer. Although the device can be used for any wideband application, the developed prototype is designed to operate within the band 2-5 GHz, which is used in microwave-based head imaging systems. The simulated and experimental results of the developed divider show equal power division with less than 0.5 dB of additional insertion loss, less than 2 degrees of phase imbalance, more than 13 dB of isolation and more than 10 dB of return loss over the band 2.3-4.7 GHz. It has a compact size with an overall dimension of 30 x 30 mm(2). (c) 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:789-791, 2015

A wide locking range and low phase noise injection-locked frequency divider has been developed by CMOS 0.13-μm technology. The proposed differential complementary injection-locked frequency divider (CILFD) consists of five-stage complementary inverter type connection. The differential input and output are implemented using auxiliary cross-coupled inverters. The measurement results show a divide-by-5 division ratio and a locking range from 1.5 to 4.5 GHz with an input power lower than −5 dBm. The power consumption of CILFD is 1.0 mA from 1.4-V power supply when it locked at 3-GHz input signal. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:31–34, 2014

A wide locking range divide-by-2 CMOS LC-tank injection locked frequency divider is proposed and is realized with two mixers in series and a cross-coupled oscillator with dual-resonance LC resonator to provide large output voltage swings at high- and low-frequency bands. The dual-band function can be obtained without switching. Measurement results show that at the supply voltage of 0.8 V, the free-running frequency is from 3.571 to 3.974 GHz for the high-frequency band and from 2.278 to 2.349 GHz for the low-frequency band. At Vtune = 1.2 V, an external injected signal power of 0 dBm provides a low-band divide-by-2 locking range (57.7%) from 2.87 to 5.2 GHz and a high-band locking range (25.7%) from 7.1 to 9.2 GHz. At Vtune = 0 V an external injected signal power of 0 dBm provides a high-band locking range (46.5%) from 5.6 to 9 GHz and a low-band locking range (25.0%) from 2.8 to 3.6 GHz. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2333–2337, 2013

This article presents the design and implementation of a wideband frequency synthesizer which uses a direct digital synthesis as a fractional divider in the phase-locked loop. The frequency resolution is 7.1 × 10−5 Hz. A phase-domain model of this synthesizer is analyzed and simulated. A formula of output phase noise is derived. The output phase noise of synthesizer is −124 dBc/Hz (10 kHz offset) at the frequency of 1 GHz. The frequency synthesizer model has been designed with advantages of wide bandwidth, low phase noise, high-frequency resolution, low spurious, high frequency stability, and simple structure. With frequency multiplier and divider module, the frequency band of synthesizer can be extended from 250 MHz to 8 GHz. The module is suitable for communication instrument. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2454–2457, 2013

Up until now, the key issue in practical applications of three-dimensional magnetotelluric (3D MT) inversion is low efficiency of computation. By further analysis of the data-space inversion approach of 3D MT, we develop a massively parallel inversion scheme on the basis of frequency division and matrix decomposition, and implement its procedure by using MPI on the Dawn TC5000A high-performance computing platform. The algorithm we develop includes the parallel calculation of 3D forward modeling, sensitivity matrix and cross-product matrix, as well as the update of model parameters. The algorithm has the advantages of higher efficiency in computation and lower memory storage in which the storage amount of sensitivity matrix at every single computing node is 2/N times as much amount as a PC (N is the number of nodes included in parallel computation). Furthermore, we test the implemented scheme with synthetic data from two 3D theoretical models and analyze the computational efficiency under multiple-nodes computing. The numerical experiment results show that the 3D data-space parallel inversion algorithm is feasible and efficient. Compared with the implementation on single PC, the parallel scheme is not only able to improve the computing speed and shorten the computation time, but also enlarge the calculational scale, which would advance greatly the utility of 3D MT inversion.

A direct conversion transmitter with low noise and low power is presented in this article.A quadrature driver amplifier is used to remove the Inphase-Quadrature crosstalk in a passive mixer operating with 50% duty cycle local oscillator (LO). In the quadrature LO generation, an inductor-less injection-locked frequency divider is utilized to reduce the phase noise contribution with cost of a small current and area. Fabricated in 65 nm CMOS process, a transmitter prototype is designed for wideband code division multiple access (WCDMA) application. Measurement results show that the proposed transmitter achieves 1 dBm maximum output power at 2.53 GHz, 1.7% error vector magnitude (EVM), and −158.5 dBc/Hz output noise at the receiver (RX) band, eliminating the need for the surface acoustic wave (SAW) filter in a traditional transmitter design, with an area of 0.18 mm2 and a total power consumption of 37.8 mW. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1217–1221, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27571

A method for analyzing the nonlinear dynamics of the injection-locked frequency dividers in synchronized operation mode is presented, including the stability analysis of locked states. We use a specific divide-by-two circuit, namely a differential LC CMOS divider with a complementary topology, as a guideline for presentation, showing that the sizing of the devices significantly affects the synchronization mechanism of the divider, which exhibits a very rich dynamical behavior. We provide closed-form expressions to determine the amplitude and the phase in the locked state, as well as the locking range, leading to accurate results, which are validated by numerical simulations. The presented analysis of the frequency divider dynamics enables us to establish that stable locked oscillations occur on the whole locking range predicted by the well-known Adler's equation and that these are possible also beyond that range. Copyright © 2013 John Wiley & Sons, Ltd.

This article presents a novel method for the design of tunable and miniaturized power dividers.It is based on three impedance transformers and requires a single bias voltage command, instead of three commands needed for more classical designs. This single voltage simplifies the power divider in terms of design and use. For a proof-of-concept, a power divider with a 950 MHz working frequency has been designed, with two output varactors tuning the power repartition through the two output ports. Thanks to the developed approach, the miniaturization ratio between our power divider and the Wilkinson one is equal to 75.5% at 950 MHz. Measurements show a wide tunable power ratio between the two output ports (1:3.4), a very good matching in the pass band (return loss better than 16 dB), low insertion loss (0.6 dB), and a tunable bandwidth of ±15%. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:357–363, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27297

A dual-modulus of 2/3 injection-locked frequency divider with wide locking ranges is presented in this work. It uses an active inductor as the resonance loop, and a tunable active-resistance is introduced to control the operation point and reinforce the injection efficiency. Simulations and measurements show that the proposed design can realize large locking ranges without any extra tuning, and cost low power consumption and small area. The divider was fabricated under the Chartered 0.35 μm CMOS technology, and the chip area is about 544 μm2. Measurements show that it has locking ranges from 1.5 to 2.05 GHz and 1.74 to 1.95 GHz at 0 dBm input power for divide-by-2 and -3, respectively, and the power consumed is only about 1.49 mW. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:269–272, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27290

A quad-band (0.8, 1.7, 2, and 1.4 GHz) wideband code division multiple access (W-CDMA) transceiver, which uses a divide-by-2.5 frequency divider in local parts of a direct-conversion architecture, has been developed. Using the fractional-2.5 frequency divider reduces the fractional bandwidth of the voltage-controlled oscillator and avoids injection locking of the local RF synthesizer perfectly. This transceiver achieved 3% error-vector magnitude and—46 dB ACLR, which satisfy the margin given in standard specifications. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

A 21.68 GHz low-power frequency synthesizer with a LC-tank voltage-controlled oscillator (VCO) is implemented in TSMC 90 nm CMOS process.In this proposed circuit, there are three important features. The primary advantage of this circuit is the use of an all-NMOS cross-coupled Colpitts VCO, which decreases transistor parasitic capacitances and reduces phase noise. Second, an injection-locked frequency divider (ILFD) is utilized in the first divider stage to divide the high frequency signal. Third, a low supply voltage of 1.2 V is used to reduce power consumption. Measured results achieve that the locked output frequency is tunable from 21.54–21.96 GHz and the phase noise is about −97.47 dBc/Hz at 1 MHz offset from 21.68 GHz. The mixed output power spectrum at ILFD output frequency of 10.22 GHz is −2.97 dBm and the overall power consumption is 9.24 mW. Including pads, the chip area is 0.8 (0.8 × 1.0) mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:200–205, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27229

In this article, we propose and demonstrate an orthogonal frequency division multiplexing-radio over fiber (OFDM-ROF) system based on three channels sextupling-frequency scheme using an external modulation of a distributed feedback laser diode (DFB-LD) and dual drive Mach–Zehnder modulator (DD-MZM) for carrying 100 GHz W-band frequency multiple-input multiple-output (MIMO)-OFDM signals with 90 Gbps downstream. MIMO-OFDM algorithms effectively compensate for impairments in the wireless link. Without using costly W-band components, a transmission system with 50 km single mode fiber (SMF) and 4 m wireless transmission operation at 100 GHz is experimentally validated. The power penalties for MIMO-OFDM signals of base stations are less than 3 dBm. For the upstream transmission, wavelength reuse with 30 Gbps 4QAM upstream signals is experimentally demonstrated. The minimum optical spectral gap between residue downstream OFDM band and upstream OFDM band that guarantees a tolerable amount of optical interference has been determined through experiment. The frequency of local oscillator is reduced due to frequency sextupling scheme. The cost of the proposed system is largely reduced. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:93–99, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27251