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Vehicular ad‐hoc networks (VANETs) support features like comfort, safety, and infotainment, enhancing traffic efficiency. However, traditional VANETs struggle with dynamic and large‐scale networks due to fixed policies and complex architectures, such as constantly changing vehicle positions. Software‐defined networks (SDN) can address these challenges by offering centralized, logical control, making VANETs more flexible and programmable. While SDNs improve VANET efficiency and add security benefits, they also introduce new security risks by incorporating novel technologies and architectural elements. Since VANET services rely heavily on data communication, compromised data (e.g., modified, falsified) could significantly impact driver and vehicle safety, making secure communication vital. Security threats specific to SDNs, like vulnerabilities in centralized control or flow‐based threats exploiting dynamic routing, necessitate robust cryptographic solutions to secure vehicle communications and data exchange. Various cryptographic algorithms, differing in performance, speed, memory requirements, and key sizes, pose challenges in selecting the optimal one for SDN‐based VANETs. This study evaluated seven cryptographic algorithms, including Blowfish, data encryption standard, triple data encryption standard, Rivest–Shamir–Adleman, advanced encryption standard (AES), advanced encryption standard with elliptic curve cryptography (AES‐ECC), and advanced encryption standard with elliptic curve Diffie‐Hellman (AES‐ECDH), in a simulated SDN‐based VANET. The findings show AES‐ECDH as the most effective overall, though the best choice depends on specific deployment scenarios and application needs. [ABSTRACT FROM AUTHOR]

Communication security has become particularly crucial with the rapid development of the Internet of Things (IoT). Frequency hopping spread spectrum (FHSS) technology, a prevalent method in wireless communication, has a wide range of applications in the Internet of Things. Enhancing the security of frequency hopping sequences is an essential means to improve the security of frequency hopping communication in the Internet of Things, as the performance of frequency hopping sequences plays a crucial role in frequency hopping systems. This paper proposes constructing secure adaptive frequency hopping sequence sets based on the advanced encryption standard (AES) algorithm. As a block cipher algorithm with superior security, the AES algorithm can provide a fundamental guarantee for the security of the proposed frequency hopping sequences. The mapping methods from ciphertext sequences to frequency hopping sequences proposed in this paper can achieve the construction of frequency hopping sequences of any frequency set size to meet the requirements of adaptive frequency hopping. In addition, we also model and analyse the problem of overlapping spectrum band of the IoT groups in the industrial, scientific, and medical (ISM) band, aiming to achieve better packet transmission performance by adjusting the frequency set size. [ABSTRACT FROM AUTHOR]

The most cutting‐edge innovation in recent times, cloud technology, changed the whole computer paradigm from less capable, specific, user‐isolated offline systems to potent multi‐server interactive systems. Despite being a huge benefit, controlling the security and accessibility of data stored in the cloud is a difficult task. Hence, this article presents a four‐phased security paradigm for securing data generated by internet of things (IoT) devices and transmitted to fog servers. In the article, we outline a comprehensive, cutting‐edge architecture for safeguarding and protecting the information that IoT devices produce and transmit to the cloud. The suggested architecture blends the advantages of an innovative mutual authentication algorithm, a novel key distribution algorithm, and a novel encryption hybrid algorithm for maximum effectiveness and increased security. The findings demonstrate that the suggested protocol outperforms previous techniques in terms of time and resource consumption and throughput. In contrast to previous protocols, the suggested approach reduces encrypting time by 28% and decryption time by about 32%, while the volume of encrypted messages produced stays consistent. There has also been a 28% increase in encryption throughput. Proposed work demonstrates minimal resource utilization, good performance and a higher level of security robustness. [ABSTRACT FROM AUTHOR]

Mobile Internet services are developing rapidly for several applications based on computational ability such as augmented/virtual reality, vehicular networks, etc. The mobile terminals are enabled using mobile edge computing (MEC) for offloading the task at the edge of the cellular networks, but offloading is still a challenging issue due to the dynamism, and uncertainty of upcoming IoT requests and wireless channel state. Moreover, securing the offloading data enhanced the challenges of computational complexities and required a secure and efficient offloading technique. To tackle the mentioned issues, a reinforcement learning‐based Markov decision process offloading model is proposed that optimized energy efficiency, and mobile users' time by considering the constrained computation of IoT devices, moreover guarantees efficient resource sharing among multiple users. An advanced encryption standard is employed in this work to fulfil the requirements of data security. The simulation outputs reveal that the proposed approach surpasses the existing baseline models for offloading overhead and service cost QoS parameters ensuring secure data offloading. [ABSTRACT FROM AUTHOR]

Now‐a‐days advanced cryptographic algorithms are needed in order to improve data security and confidentiality. One such algorithm used prominently is advanced encryption standard (AES) algorithm. AES is a complex algorithm with multiple rounds of processing data and occupies more space or area when implemented on hardware. Since each sub‐step of computation has a similar structure, the proposed method employs the novel idea of using the same hardware to implement the AES functionality. Hence the number of logical units occupied are leveraged. The proposed scheme, Mux‐Demux pair method (MDP), uses a mux‐demux structure. It is implemented on Virtex‐7 and ZynQ7000 FPGAs and the code is written in Verilog HDL language in the Vivado software. The proposed work when simulated on Virtex‐7 occupies an area of 1932 slices, giving an optimized throughput of 10.167 Gbps while the work simulated on ZynQ7000 occupies an area of 3253 slices, resulting in a throughput of 23.858 Gbps. [ABSTRACT FROM AUTHOR]

Multiple‐Input Multiple‐Output Orthogonal Frequency Division Multiplexing (MIMO‐OFDM) is an essential technology in the wireless communication system. However, its performance is significantly affected by Carrier Frequency Offset (CFO), which leads to inter‐carrier interference (ICI). The CFO estimation and compensation techniques are used to mitigate the Doppler effect. In addition, the confidentiality of data is a key factor of the system. This paper proposes a Turbo‐based encryption and coding scheme to improve reliability and security for the MIMO‐OFDM wireless communication systems affected by the Doppler frequency offset. In our proposed scheme, the secret key is produced from channel parameters between legitimate users and it is used as a seed for generating a pseudo‐random bit sequence using an Advanced Encryption Standard (AES) generator with variable key lengths. The Turbo code's puncturing mechanism is controlled by this pseudo‐random bit sequence. The proposed method is applied to the system with different modulation schemes through the Rayleigh channel. The simulation results show that the system affected by the Doppler effect would obtain the best performance when using the highest key length of the AES generator, the BPSK, and a great number of receive antennas. Furthermore, the proposed solution outperforms several previous approaches for the MIMO‐OFDM systems. [ABSTRACT FROM AUTHOR]

The appearance of quantum computing in the short foreseeable future and its capability to break conventional cryptographic algorithms forces to change the paradigm of secure real‐time communications. Thus, government organizations, data centers, and enterprises among others are migrating their public key infrastructure towards using post‐quantum cryptography (PQC) algorithms in order to mitigate the security threats posed by quantum computers. This letter presents the first quantum resilient secure end‐to‐end communication link based on PQC algorithms operating between two data‐processing units DPU. Both data‐processing units employ on‐board ARM processors to perform the computationally expensive cryptographic building blocks—in that case CRYSTALS‐Kyber as a key encapsulation mechanism and CRYSTALS‐Dilithium for digital signature scheme in combination with advanced encryption standard with 256‐bit key. [ABSTRACT FROM AUTHOR]

With the majority of users migrating to a cloud computing platform, the responsibility for data security has increased considerably. As data with various levels of sensitivity moves out of the confines of the system firewall, there is no control over where it resides; it depends on the cloud server being used. This makes the use of secured cryptographic algorithms necessary to improve data security and maintain the confidentiality of data. The encryption algorithm used most extensively today is the Advanced Encryption Standard (AES). Hardware acceleration with Field Programmable Gate Array can improve the performance of AES. This study examines various approaches for improving data encryption methods that can be utilized as hardware accelerators to improve the fundamental AES cipher. Some research publications suggest ways to boost throughput while others advise ways to save area and power. Many subsequent developments have also used other cryptographic methods such as RSA and ECC to improve key management security. This study examines the outcomes of multiple ways for metrics including throughput, area, power, and data security, and explains some of the best implementation solutions for each metric individually. [ABSTRACT FROM AUTHOR]

Summary: In semiconductor industry, reusability‐based System‐on‐Chip architecture using hardware intellectual property (IP) cores play a prominent role in Internet‐of‐Things (IoT) applications for secure data transmission. The advent of IoT makes it possible for physical things to transmit, process, compute, and receive data over internet. But, it also introduces in‐device communication security vulnerabilities. Advanced Encryption Standard (AES) IP has been used to address security vulnerabilities in IoT. It is an efficient and high‐performance crypto algorithm used in IoT devices for secure and fast data encryption. However, due to rise of many attacks, the security of AES IP is also under threat. Hardware obfuscation is one such prominent countermeasure that mitigates hardware attacks such as tampering, reverse engineering, and malicious alteration. This article presents secure AES IP mechanism using the potential technique of obfuscation inspired by the concept of combinational hardware Trojan. Experimental results show that the proposed technique is resilient against reverse‐engineering, malicious alteration, Boolean satisfiability attack, and key‐sensitizing attacks. The confusion and diffusion features of obfuscated AES IP are higher in terms of Hamming distance, avalanche effect, and balance rate. The proposed technique is implemented in Basys‐3 FPGAs within 5% of power and area overhead while maintaining high throughput. [ABSTRACT FROM AUTHOR]

In this article, Internet of Things (IoTs) devices are used for sensing the data through which the device owners earn revenue. Interested users can purchase data from IoT device owners, according to their demands. However, users are not confident about the quality of data they are purchasing. Moreover, the users do not rely on the device owner and are not willing to initiate data trading. Currently, data trading systems have many drawbacks, as they involve a third party, security and reputation mechanisms. Therefore, in this article, IoTs and BlockChain (BC) are integrated to monetize IoT's data and provide trustful data trading. A BC based review system to monetize IoT's data trading is developed through Ethereum smart contracts. The review system encourages the owners to provide authentic data and solves the issues regarding data integrity, fake reviews and conflicts between entities. Reviews and ratings are stored in the BC database for providing a guarantee about the data quality to users. To maintain data integrity, we use an advanced encryption standard (AES)‐256 encryption technique to encrypt data. Moreover, an arbitrator entity is responsible to resolve conflicts between data owner and users. The incentive is provided to the users and arbitrators to increase user participation and honesty. Simulations are performed for the validation of our system. We examine the proposed model using three parameters: gas consumption, mining time and encryption time. [ABSTRACT FROM AUTHOR]

Summary: In implementing well‐known advanced encryption standard (AES) algorithm, the main part for constructing the hardware is S‐Box, which is abbreviated from substitution box. This is the basic component of symmetric key cryptographic algorithm, and it requires in AES because of its nonlinear organization with multiplicative inversion. This S‐Box is designed by two transformations, ie, inversing the multiplication part in Galois field directed with modified affine transformation. The limitation of S‐Box is more time and power consumption. This limitation has to be overcome by doing slight modification in affine and inverse affine transform. The time consumption for AES S‐Box is decreased by the proposed transformation method. The proposed system achieved 39% power when compared with the existing system; the proposed system is efficient. [ABSTRACT FROM AUTHOR]

Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low‐cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32‐bit data‐path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple‐bit (byte) simultaneous faults at each pipeline stage's logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault‐masking capability for multiple‐bit (byte) faults. Finally, it is shown that the Application‐Specific Integrated Circuit implementation of the fault‐tolerant architectures using the composite field‐based S‐box, CFB‐AES, and ROM‐based S‐box, RB‐AES allows better area usage, throughput and fault resilience trade‐off compared to their counterparts. So, it provides the most appropriate features to be used in highly‐secure resource‐constraint applications. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a lightweight 8‐bit S‐box and combined S‐box/S‐box−1 with a security level equal to the AES S‐box is presented. From the viewpoint of hardware implementation, the S‐box has better hardware and timing complexities. The structure is based on an efficient field inversion and a low‐cost affine transformation. The field multiplications over 픽24 in the inversion circuit are implemented by resource sharing to reduces logic gates. The original equations of the inversion over 픽24 are optimally rewritten. In addition, a part of the S‐box called Part1 is optimized for reducing area and delay. This part consists of two addition operations, one multiplication, field squaring, and multiplication by constant λ, which all operations are over 픽24. The subblocks of Part1 are combined to generate a unified structure. Security analysis of the proposed S‐box showed that the structure has a security level equal to the Advanced Encryption Standard (AES) S‐box. The implementation results in 180‐ and 65‐nm Complementary metal oxide semiconductor (CMOS) technologies show the proposed S‐box and combined S‐box/S‐box−1 are comparable in terms of area, delay, and area × delay than most of the famous S‐boxes. The proposed S‐box is a high‐secure and area‐efficient S‐box as a good candidate for block ciphers. [ABSTRACT FROM AUTHOR]

This paper describes an image encryption algorithm that utilises a plaintext‐related quantisation scheme. Various plaintext‐related approaches from other algorithms are presented and their properties are briefly discussed. Main advantage of the proposed solution is the achievement of a similar behaviour like that of more complex approaches with a plaintext‐related technique used in a rather simple step such as quantisation. This design should result in a favourable computational complexity of the whole algorithm. The properties of the proposal are evaluated by a number of commonly used numerical parameters. Also, the statistical properties of a pseudo‐random sequence that is quantised according to the plain image pixel intensities are investigated by tests from NIST 800‐22 suite. Obtained results are compared to values reported in related works and they imply that the proposed solution produces encrypted images with comparable statistical properties but authors' design is faster and more efficient. [ABSTRACT FROM AUTHOR]

Summary: For a smart cloud computing system, security and privacy are the required factors. In recent days, the evolvement of cloud technology is immense, according to which several cloud service providers (CSPs) evolved. Each CSP has its infrastructure with its security policies. Even though still the security in cloud computing is an existing challenge, it is more important to maintain the trustiness of cloud environment among the cloud users. On this motto, we propose a novel tailored—advanced encryption standard (AES) Cryptographic Algorithm (TCA). AES is one of the popular cryptography algorithms. We indulged in increasing the performance of this algorithm by minimizing the time taken for the cryptography process. Here, the cryptography is processed with AES algorithm. In order to improve the efficiency of AES, a concept of a chunk file system is introduced. The input file is chunked into multiple which facilitates quick and effective encryption. To prove the efficiency of our proposed system, a comparison work is carried out with the existing algorithms lightweight keyword searchable encryption (LFSE) and cloud key management system (CKMS). The comparison work is based on the aspect of time taken during key generation, encryption and decryption. The obtained result is plotted, and comparison output clearly states our TCA's excellence in the aspect of efficiency compared to others. [ABSTRACT FROM AUTHOR]

Summary: With the growth of wireless environments, confidential communication has become an important part of daily life. Generally, a wireless medium uses cryptography techniques when transmitting data to provide end‐to‐end protection. Most of the hardware‐efficient cryptosystems do not satisfy the security requirements. In this paper, we concentrate both on security issues and hardware efficiency and present an area‐efficient, high‐throughput hardware structure to implement a hybrid cryptosystem to avoid security problems. The security enhancements are done using a key enhancement process, and it is achieved by using a hybrid encryption cryptosystem. In this paper, we combine block and stream cipher encryption algorithms to frame the hybrid algorithm. We consider advanced encryption standard (AES) as the block cipher and Rivest cipher‐4 (RC4) as the stream cipher. Due to the hybrid systems, performance metrics, such as area, throughput, and power consumptions, are affected. Moreover, advanced arithmetic logic (ie, field arithmetic) combined with the on‐the‐fly key expansion technique is used to minimize area consumption, and parallel subpipeline technique is used to enhance the system throughput. The proposed hybrid architecture (AES‐RC4) is implemented in a field‐programmable gate array with a Xilinx tool. [ABSTRACT FROM AUTHOR]

The multiplication strategy is a trending technology in chip programming model; also, it is used in different applications for different purpose. This research aims to develop the floating point double precision Furer Toom cook fast integer multiplication model in the Advanced Encryption Standard process round to enhance the security. In addition, the cryptography algorithms have been broken due to some harmful attack. So the main focus of this present research is to enhance the security measures in communication channel. Moreover, the proposed model is implemented in Xilinx and simulated in cadence 90 nm technology. By comparing the proposed work with recent existing models, the proposed research has reduced the power consumption as 5331.73 nW, thus 89% of power is reduced by the proposed Furer Toom cook multiplication model. The reduction of power enhanced the performance of multiplication algorithm so, while it is utilized in any application, it could not cause any loss of process. In addition, the developed strategy is process within 563 MHz frequency and utilized 11 250 cells. Thus, the proposed model provides better security for all wireless appliances. [ABSTRACT FROM AUTHOR]

A system‐on‐a‐chip (SoC) processor core contains several numbers of chips integrated into a single chip where each and every integrated circuit (IC) consists of multiple blocks. Hence, data routing from one chip to another creates a difficult issue in the SoC. A network‐on‐a‐chip (NoC) router has been mainly used to obtain highly reliable data transmission from a source to a destination using low power, low hardware complexity, and high speed to achieve efficient routing in the SoC core, which contains a router, network links (NLs), and network interface (NI). The heart of the NoC core, ie, the router, consists of a finite state machine (FSM), input/output FIFO, a crossbar switch, and an arbiter; however, the XY routing technique was incorporated into the NoC router to achieve high switching speed, and the FSM is used as a controller for the router along with the data stored in FIFO. The multiplexing and demultiplexing operations were also carried out in the crossbar switch in which a grant signal is being generated using the compact round‐robin arbiter and an Advanced Encryption Standard (AES) scheme, which is incorporated into the NoC router to achieve high reliability. The chief goal is to establish an efficient NoC router using an improved AES algorithm to achieve high reliability, small chip size, low power consumption, and high performance. Similarly, an optimized composite S‐box is designed using a compact multiplicative inverse unit with an improved inverse MixColumns structure proposed using compact 09, 0b, 0d, and 0e operations and retiming pipelined inclusively with clock gating methods (CGMs) applied in the targeted AES scheme. Hence, the retiming method can be used to shrink the number of registers by placing the register in an optimum location with low area and power in retiming‐based AES. The switching activity of the clock signal is reduced by using the CGM, which has low power consumption and high speed for clock gating–based AES. Therefore, the high performance–based AES is designed using a pipelined technique with high chip size and power due to the insertion of a large number of registers into the AES circuits. Five types of AES structures are designed, and the die size, delay, power, and 90% security with an optimized AES technique incorporated into a 3×3 NoC router with mesh topology are analyzed. Finally, the comparison between the existing and proposed NoC routers was carried out to analyze the area, delay, and power (ADP) product, and the NoC router design was formulated using Verilog HDL, and limitations along the synthesis process were executed using a ModelSim and Xilinx ISE tools. [ABSTRACT FROM AUTHOR]

In this work, we present a methodology of systematic design of an improved genetic algorithm (IGA)‐based secure communication in multiple time‐delay chaotic (MTDC) systems with advanced encryption standard (AES) and optimal H∞ performance. To hide the message contents via chaotic signals, various approaches have been developed. Nevertheless, the attacks proposed in many studies have demonstrated that most of these approaches are not secure or have a low security. Therefore, in order to enhance the overall security, this work endeavors to combine chaotic synchronization with AES algorithm. The encryption method not only increases the strength of the communications system, but effectively protects the encrypted message as well. Finally, a numerical example is provided to show the achievements of this study. [ABSTRACT FROM AUTHOR]

Summary: Nowadays, security and data access control are some of the major concerns in the cloud storage unit, especially in the medical field. Therefore, a security‐aware mechanism and ontology‐based data access control (SA‐ODAC) has been developed to improve security and access control in cloud computing. The model proposed in this research work is based on two operational methods, namely, secure awareness technique (SAT) and ontology‐based data access control (ODAC), to improve security and data access control in cloud computing. The SAT technique is developed to provide security for medical data in cloud computing, based on encryption, splitting and adding files, and decryption. The ODAC ontology is launched to control unauthorized persons accessing data from storage and create owner and administrator rules to allow access to data and is proposed to improve security and restrict access to data. To manage the key of the SAT technique, the secret sharing scheme is introduced in the proposed framework. The implementation of the algorithm is performed by MATLAB, and its performance is verified in terms of delay, encryption time, encryption time, and ontology processing time and is compared with role‐based access control (RBAC), context‐aware RBAC and context‐aware task RBAC, and security analysis of advanced encryption standard and data encryption standard. Ultimately, the proposed data access control and security scheme in SA‐ODAC have achieved better performance and outperform the conventional technique. [ABSTRACT FROM AUTHOR]

Summary: Industrial Internet of Things (IIoT) is an emerging technology that relies on the use of massively connected sensor nodes to gather industrial‐related data. The collected data are used for postanalysis to generate insights for reducing production down time, cost optimization, and predictive maintenance. One of the key requirements for sensor node in such application is the data confidentiality; as such sensor data may potentially leak the manufacturing and industrial secret to their competitors. In this paper, a field programmable gate array (FPGA)‐based sensor node with Advanced Encryption Standard (AES) crypto‐processor is proposed to safeguard the sensor data. A novel queue system is proposed to further reduce the data processing time and energy consumption. The proposed queue system is able to achieve 1.48× speed up and ∼16% energy reduction, which makes it a competitive candidate for Industrial IoT applications. The technique developed in this paper can also be extended to implement FPGA‐based gateway with encryption feature, which is very useful for edge computing in IoT applications. [ABSTRACT FROM AUTHOR]

This study presents the algebraic cryptanalysis of a continuous‐time chaotic random number generator (RNG) based on a Zhongtang chaotic system. The chaos‐based RNG provides key values for logic encryption, round key formation and the substitution box (S‐box) generation steps in AES (advanced encryption standard). In this study, an attack method is proposed to exploit the weaknesses of the chaos‐based RNG used in this cryptographic system. By observing a chaotic state variable and knowing the structure of the target RNG, output bit sequence of the target RNG is reproduced by a clone RNG used in master–slave synchronisation scheme. The feasibility of the attack system is confirmed through simulation and numerical results. Through this attack method, the same S‐box parameters and key values can be obtained which can be used for decryption of the proposed encryption algorithm. This study targets a specific continuous‐time chaos‐based RNG and the associated cryptographic system as a case study. However, the cryptanalysis method described in this study is applicable to any continuous‐time or discrete‐time chaos‐based RNGs. Therefore, this study highlights the security vulnerabilities of chaos‐based RNGs and emphasises that deterministic chaos phenomena itself should not be considered as the actual source of randomness. [ABSTRACT FROM AUTHOR]

Summary: Noise is an important ingredient for side‐channel‐analysis countermeasures security. However, physical noise is in most cases not sufficient to achieve high‐security levels. As an outcome, designers traditionally aim to emulate noise by harnessing shuffling in the time domain and algorithmic noise in the amplitude domain. On one hand, harnessing algorithmic noise is limited in architectures/devices which have a limited data‐path width. On the other hand, the performance degradation due to shuffling is considerable. A natural complement to operation shuffling is the hardware‐based intra‐cycle shuffling (ICS), which typically shuffles the sample time of bits within a clock cycle (instead of micro‐processor operations). Such architecture eliminates the performance overhead due to shuffling within a single cycle, it is algorithm‐independent, i.e., no need in partitioning of operations, and as it is hardware‐based, the data‐path width can be tailored to better exploit algorithmic‐noise. In this manuscript, we first analyze the noise components in physical designs to better model the algorithmic noise. We then perform an information‐theoretic (IT) analysis of both shuffling countermeasures. The last part of the manuscript deals with real‐world architectures analysis: IT analysis of an Advanced Encryption Standard (AES) core implemented over a 32‐ and 128‐bit wide data‐path embedded with intra‐cycle shuffling and two flavors of shuffling generation (memory‐based and on‐line permutation generation). The manuscript is concluded by underling the benefits which can be achieved with the ICS architecture. [ABSTRACT FROM AUTHOR]

Security is a challenging issue in resource‐constrained applications, e.g. in an embedded system. This study focused on practical lightweight fault‐tolerant strategies for hardware implementation of Advanced Encryption Standard (AES) to mitigate the‐reliability issue of secure architectures. In this work, a‐fault‐tolerant architecture called configurable fault‐tolerant AES (CFTA), and its variants, called robust CFTA (R‐CFTA), R‐CFTA+, high throughput CFTA (HT‐CFTA), HT‐CFTA4R, HT‐CFTA8R, and HT‐CFTA+, are introduced. Proposed approaches exploit the‐inherent parallel architecture of AES for employing redundancy at low cost. CFTA and HT‐CFTA can tolerate all single permanent and transient faults in the‐AES blocks and also all multiple permanent and transient faults in the‐same block. R‐CFTA upgrades the‐fault‐tolerant aspect of CFTA and HT‐CFTA and it is also able to tolerate all single‐ and multiple‐transient faults in two AES functional blocks during a round. The proof is provided to show the fault masking ability of provided architectures. Furthermore, R‐CFTA+ and HT‐CFTA+, which are suitable for high‐security sensitive applications are suggested. In addition, the proposed fault‐tolerant designs are implemented on both field programmable gate array and application‐specific integrated circuit platforms, and their implementation area, frequency, and throughput are discussed and compared with other related works. Moreover, system‐efficiency, as an important design metric, is reported for proposed structures. [ABSTRACT FROM AUTHOR]

As more and more confidential information is being transmitted securely, the use of cryptographic algorithms is expanded. However, existing cryptographic algorithms are subject to various malicious attacks. Fault injection attack is one of the most effective attacks that are able to extract private information with the inexpensive requirement and short amount of time. AES is a block cipher that is used in many critical applications. Here, a lightweight error‐detection architecture for AES has been proposed; the authors call it as high throughput fault‐resilient AES (HFA). In the proposed architecture, the authors use parallel AES architecture, which contains four equivalent blocks and split each block into two pipeline stages. The authors have shown that HFA achieves high error‐detection rate while keeping overheads reasonable. [ABSTRACT FROM AUTHOR]

A large number of studies are there for Advanced Encryption Standard (AES) fault attack analysis, but less for fault recognition. This paper presents a recognition method for single‐byte fault which is induced in the last three rounds of AES. Studying the differential characteristics of Sbox, the single byte fault induced in ninth round or tenth round will be identified respectively with 9.3 and 9.1 ciphertexts. For the fault induced in eighth round, the fault value can be obtained with 188.5 ciphertexts by analyzing the differential features of two Sboxes and MixColumns. As an auxiliary means for fault attacks, this method is used to realize the byte or bit level physical positioning of confidential data in the encryption chip, which is beneficial to reduce the blindness of the attacker's experiments and obtain the sensitive area of fault attack. [ABSTRACT FROM AUTHOR]

Internet protocol security (IPSec), secure sockets layer (SSL)/transport layer security (TLS) and other security protocols necessitate high throughput hardware implementation of cryptographic functions. In recent literature, cryptographic functions implemented in software, application specific integrated circuit (ASIC) and field programmable gate array (FPGA). They are not necessarily optimized for throughput. Due to the various side‐channel based attacks on cache and memory, and various malware based exfiltration of security keys and other sensitive information, cryptographic enclave processors are implemented which isolates the cryptographically sensitive information like keys. We propose a partitioned enclave architecture targeting IPSec, TLS and SSL where the partitioned area ensures that the processor data‐path is completely isolated from the secret‐key memory. The security processor consists of a Trivium random number generator, Rivest–Shamir–Adleman (RSA), advanced encryption standard (AES) and KECCAK cryptos. We implement three different optimized KECCAK architectures. The processing element (PE) handles all communication interfaces, data paths, and control hazards of network security processor. The memory of KECCAK and AES communication is done via a direct memory access controller to reduce the PE overhead. The whole system is demonstrated by FPGA implementation using Vivado 2015.2 on Artix‐7 (XC7A100T, CSG324). The performances of the implemented KECCAKs are better in terms of security, throughput and resource than the existing literature. [ABSTRACT FROM AUTHOR]

This study presents an implementation flaw in Differential Power Analysis Contest (DPA) Contest v4. This version of DPA Contest uses Advanced Encryption Standard (AES) protected against side‐channel attacks using rotating s‐box masking (RSM) countermeasure. The authors identify a flaw in the masking scheme that was used in this contest. More specifically, the problem lies in an unfortunate choice of values for masks. An unbalance in the masking scheme leads to a first order leakage. This vulnerability could be used in order to mount a first order side‐channel attack against AES‐RSM. The attack was implemented and tested on DPA Contest v4 reference traces. The authors also provide a way to avoid the newly discovered problem and suggest new values for masks. [ABSTRACT FROM AUTHOR]

This paper presents secure data processing with a massive-parallel single-instruction multiple-data (SIMD) matrix for embedded system-on-chip (SoC) in digital-convergence mobile devices. Recent mobile devices are required to use private-information-secure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end-user's operation for maintaining the safety condition. To satisfy these security-related requirements, we propose the interleaved-bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massive-parallel SIMD matrix processor (MX-1) for interleaved-bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization-approved block ciphers, a data encryption standard (DES), triple-DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX-1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX-1 results are almost constant for all confidentiality modes. The practical-use energy efficiency of parallel block cipher processing with the evaluation board for MX-1 was found to be about 4.8 times higher than that of a BeagleBoard-xM, which is a single-board computer and uses the ARM Cortex-A8 mobile processor. Furthermore, to improve the operation of a single-bit logical function, we propose the development of a multi-bit logical library for interleaved-bitslice cipher processing with MX-1. Thus, the number of clock cycles is the smallest among those reported in other related-studies. Consequently, interleaved-bitslice block cipher processing with five confidentiality modes on MX-1 is effective for the implementation of parallel block cipher processing for several digital-convergence mobile devices. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [ABSTRACT FROM AUTHOR]

Fault attack is a type of active attack which retrieves the secret key by injecting computational faults. Laser is one of the most common fault injection methods. When attacking substitution‐permutation networks‐ciphers, S‐box is often chosen as the laser injection target. However, the adversary has to know whether the S‐box is corrupted or not after each injection, which was difficult in real‐world attacks. Two analysing methods to distinguish the S‐box faults for different ciphers is proposed in this Letter. A laser‐based physical experiment is carried out to verify the authors' methods on Advanced Encryption Standard and PRESENT ciphers on an ATmega163L microcontroller. Experimental results show that their methods can precisely distinguish S‐box faults merely using dozens of ciphertexts. [ABSTRACT FROM AUTHOR]

Many e-business or social network servers have been constructed on cloud. On such open environments, private data of massive users have to be protected by encrypting, such as using Advanced Encryption Standard (AES), and furthermore, this process must be finished in a short time for users' better experience. This gives huge pressure on cloud servers, especially common servers, such as web servers. We urgently need an inexpensive and highly efficient method to relieve cloud servers' pressure. Fortunately, many cores of a graphics processing unit (GPU) can undertake this hard mission because of stronger computing power and lower price. The GPU environments can be virtualized on demand by cloud through the vCUDA technology. Of course, for those clouds not equipped with a GPU, a central processing unit (CPU) can still work as multithreads in parallel. Thus, in a cloud, AES can be parallelized using many cores of a GPU or multicores of a CPU with high efficiency and low cost. For typical cloud applications, such as web services, there are massive users and each one has short plaintext. If we simply parallelize AES in such an application, we cannot obtain better performance because of the GPU's extra data transferring cost. Thus, we coalesce the massive users' data and cut these data into same-length slices for improving the performance of parallel AES as much as possible. So we design six parallel AES algorithms using GPU parallelism or CPU parallelism, which differ in parallel scope and whether data are coalesced or cut to slices. Specifically, they are coalescent and sliced GPU (GCS), coalescent and unsliced GPU, uncoalescent GPU, coalescent and sliced CPU, coalescent and unsliced CPU, and uncoalescent CPU. Moreover, we implement them on two representative platforms and evaluate their performance. Through comparing their performance, GCS has the best performance among these algorithms. In a cloud with Nvidia GPUs, GCS is a more powerful algorithm for massive users' data encrypting, relatively. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper introduces a new type of collision attack on first-order masked Advanced Encryption Standards. This attack is a known-plaintext attack, while the existing collision attacks are chosen-plaintext attacks. In addition, our method requires significantly fewer power measurements than any second-order differential power analysis or existing collision attacks. [ABSTRACT FROM AUTHOR]

The design of ultra‐low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2‐Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1‐Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent. [ABSTRACT FROM AUTHOR]

Security has been identified as a critical dimension in the design of embedded systems for almost a decade. A well‐recognised critical threat against the security of embedded systems is represented by 'side‐channel attacks (SCAs)', which mandate the application of specially tailored countermeasures. These countermeasures are significantly demanding in terms of computation effort, and have traditionally been applied by hand. The recent introduction of a methodology to gauge the security margins provided by software cipher implementations, allows the integration of the automated application of countermeasures into platform‐based system‐level design methodologies. The authors introduce in the design space of block cipher implementations a new metric concerning the resistance against SCAs, provide a systematic method for the selection of the most appropriate cipher given the security and performance trade‐offs, and point out the performance requirements for the random number generator. Moreover, they discuss the implications of the design space extension on system runtime adaptivity. The experimental evaluation demonstrates that a single cipher does not cover optimally a range of convenient operating points and that ciphers like a Serpent, which are considered slow in non‐protected implementations, can outperform primitives like the Advanced Encryption Standard when implementations with equal security guarantees against SCAs are considered. [ABSTRACT FROM AUTHOR]

SUMMARY E2, a block cipher, is an Advanced Encryption Standard candidate designed and submitted by Nippon Telegraph and Telephone Corporation. It employs a Feistel structure as global structure and two-layer substitution-permutation network structure in round function. The conservative structure makes E2 immune to kinds of current cryptanalysis. Previously, there is no result of impossible differential attacks on E2 because it was once supposed to have no more than five-round impossible differential characteristic. In this paper, we present a series of six-round impossible differential characteristics of E2 with/without initial transformation (IT)/ final transformation (FT) functions. Based on these impossible differentials, the immunity of E2 against impossible differential cryptanalysis is evaluated. We perform a seven-round attack on tweaked E2 (E2 without IT and FT ) with 128, 192, and 256 bits key and an eight-round attack on tweaked E2 with 256 bits key. The seven-round attack requires about 2120 chosen plaintexts and 2115.5 seven-round encryptions; the eight-round attack needs 2121 chosen plaintexts and less than 2214 eight-round encryptions. We also discuss the seven-round attack on E2 with IT or FT, and the result shows that the attack has the same complexities with the seven-round attack on tweaked E2. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In wireless sensor networks, data encryption and channel coding are considered together for ensuring secure and robust communication. In order to achieve this purpose, we introduce a new joint scheme, namely ‘Multilevel/Advanced Encryption Standard-Low Density Parity Check Coded-Continuous Phase Frequency Shift Keying (ML/AES-LDPCC-CPFSK)’. AES algorithm is the most powerful and widely used symmetric key cryptography in providing secure data transmission. LDPC codes have very large Euclidean distance and use iterative decoding algorithms. In this study, we have increased error performance employing multilevel structure to AES and LDPC. In all communications systems, phase discontinuities of modulated signals result in extra bandwidth requirements. CPFSK, which is a special type of continuous phase modulation, is a powerful solution for this problem. In this paper, we simulate error performance of ML/AES-LDPCC-CPFSK for regular LDPC codes. Simulation results are drawn for 4CPFSK, 8CPFSK and 16CPFSK over wireless cooperative sensor networks. Using this scheme, we are able to improve bit error performance, channel throughput, security level of communication and reduction in complexity compared with related schemes such as various turbo code structures. Copyright © 2009 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this Letter, an efficient implementation of the bit‐parallel polynomial basis (PB) multiplier over the binary field GF(28) generated by the type I irreducible pentanomial f(y) = y8 + y4 + y3 + y + 1 is presented. This pentanomial is especially important because it is used in the advanced encryption standard (AES). Therefore, any optimisation of the multiplier complexity over this finite field is very relevant because efficient AES implementation can be obtained. The bit‐parallel multiplier here presented has the lowest delay known to date for similar multipliers based on this irreducible pentanomial. [ABSTRACT FROM AUTHOR]

Application of control or modelling technology covers many diverse fields of practical systems. The switched time-delay systems can be modelled from some practical systems, such as automotive engine control systems, chemical processes, power systems, and power electronics. The paper by Ko-Fei Lee and Ching-Hung Lee proposes a servo-tuning system for five-axis machine tools using a virtual feed drive system in which the particle swarm optimization (PSO) algorithm was adopted to identify and estimate the optimal system parameters. [Extracted from the article]

A power analysis attack countermeasure, called power‐awareness‐based hiding, is proposed. It is effective in implementing nonlinear operations, S‐boxes, in cryptographic algorithms. An advanced encryption standard (AES) S‐box circuit has been implemented in this approach using the Domino logic array style. The post‐layout simulation results show that the power‐aware hiding AES S‐box achieves a delay of 1.56 ns and a mean power consumption of 3.57 mW. The proposed method improves the power delay product by 65%, the normalised energy deviation by 43% and the normalised standard deviation by 30% compared to other secure methods. [ABSTRACT FROM AUTHOR]

Fault attack is a type of active attack which retrieves the secret key by injecting computational faults. Laser is one of the most common fault injection methods. When attacking substitution-permutation networksciphers, S-box is often chosen as the laser injection target. However, the adversary has to know whether the S-box is corrupted or not after each injection, which was difficult in real-world attacks. Two analysing methods to distinguish the S-box faults for different ciphers is proposed in this Letter. A laser-based physical experiment is carried out to verify the authors' methods on Advanced Encryption Standard and PRESENT ciphers on an ATmega163L microcontroller. Experimental results show that their methods can precisely distinguish S-box faults merely using dozens of ciphertexts. [ABSTRACT FROM AUTHOR]

Cyber-physical systems (CPSs) are physical embedded systems with enhanced operations for monitoring, coordination, control, and integration by a computing and communication core.[1] Examples of CPSs include transportations systems,[2] medical systems,[3] and manufacturing systems.[4] A CPS can be security-critical, safety-critical, or both. On the other hand, a CPS is considered to be safety-critical if it can harm its environment, eg, a malfunctioning autonomous vehicle might harm its passengers.[5] A CPS dealing with both security and safety concerns is considered to be a security- and safety-critical CPS. Finally, the paper proposes security solutions for data management systems by identifying various security vulnerabilities in internal security algorithms of such systems. [Extracted from the article]

Robot Operating System (ROS) is a middleware for connecting different components of robots. However, its use is becoming more popular in other domains such as in the automotive sector where initial prototypes have been customized and deployed in cars for demonstrating different functional purposes. Nevertheless, ROS has not been yet tested enough to be used in secure and safety environments. For example, in order to strengthen our ROS architecture, we have encrypted the messages within it. Therefore, this paper analyses the impact of Advanced Encryption Standard (AES) encryption mechanism and the functional safety of our prototype. In this sense, we are considering encrypting messages and we assess the timing constraints, as suggested by the ISO 26262, required for assuring a secure communication between components. [ABSTRACT FROM AUTHOR]

A deep learning (DL)-assisted and combined side-channel attack (SCA) is exploited to disclose the secret key of an advanced encryption standard (AES) cryptographic circuit with a countermeasure. Different physical leakages of the protected AES cryptographic circuit such as power dissipation and electromagnetic (EM) emission are captured together at first. Then the deep neural networks are utilised to model the relationship between the power noise and the EM noise by analysing the captured power dissipation and EM emission profiles. Ultimately, a special power attack is performed on the protected AES cryptographic circuit to leak the secret key efficiently through using the EM noise to filter the power noise. As demonstrated in the results, for the conventional SCAs, the secret key of the protected AES cryptographic circuit is undisclosed to the adversary even if 1 million plaintexts are enabled. By contrast, only analysing 32,500 number of plaintexts are sufficient to leak the secret key if the DL-assisted and combined SCA is executed. [ABSTRACT FROM AUTHOR]

A masked advanced encryption standard (AES) physical unclonable function (PUF) architecture is proposed for hardware authentication against hybrid side-channel (SCA) and machine-learning attacks (MLAs). The random mismatches of the load capacitance of the masked substitution-boxes in the AES cryptographic circuit induced by the fabrication process are utilised for generating the critical-authentication data against SCAs. Moreover, a mask data is added to the input challenge data to mask the actual input data of the proposed PUF against MLAs. As demonstrated in the results, the masked AES PUF proposed shows a nearly 51.1% uniformity, 50.7% inter- Hamming distance, and 98.1% reliability. Furthermore, if a hybrid SCA/MLA is performed on the proposed PUF by combining the corresponding side-channel leakage with the deep neural network algorithm, the prediction rate of the output responses of the masked AES PUF is only 55.2% after 100,000 number of challenge-to-response pairs are used for training. [ABSTRACT FROM AUTHOR]

Summary: With the rapid development of information technology, the security of massive amounts of digital data has attracted huge attention in recent years. The Advanced Encryption Standard (AES) algorithm and the Security Hash Algorithm 3 (SHA3) are extensively used as cryptographic algorithms for protecting the security of information. The Sunway TaihuLight, with massive heterogeneous many‐core SW26010 processors, has the peak performance of over 100 PFlops. To achieve high efficiency of data encryption/decryption and guarantee the data integrity for large‐scale applications, this paper proposes a fast and secure data protecting model using the parallel AES algorithm and the SHA3 on the Sunway TaihuLight. According to the particular computing architecture and memory hierarchy of the Sunway TaihuLight, we propose a fine‐grained software design for the data protecting model to fully exploit the parallelism and properly arranges the data on the Sunway. Furthermore, we propose optimization strategies for the parallel AES algorithm of the data protecting model. It is proved that our data protecting model has high security, good scalability, and excellent encryption/decryption efficiency on the Sunway. Our data protecting model achieves a high throughput of 269.95 Gbits/s, and the optimized parallel AES algorithm achieves 511.28 Gbits/s on the Sunway. [ABSTRACT FROM AUTHOR]

Summary: Software defined wireless sensor network (SDWSN) is a recent evolution in networking that improves network performance and scalability. However, Quality of Service (QoS) and security are major the issues in SDWSN due to inefficient route selection (traffic load minimization algorithm) and insecure cryptography scheme (homomorphic algorithm). This paper proposes novel three‐tier architecture for secure cluster‐based SDWSN (SeC‐SDWSN) environment to ensure QoS and security for WSN using SDN. In the first tier, sensor nodes are segregated into multiple clusters by secure hash tree‐based clustering (SHTC) algorithm. Within each secure cluster, data transmission is performed through optimal route selected by adaptive spider monkey optimization (ASMO) algorithm in which two new fitness factors (F1, F2) are formulated by multiple QoS metrics. For data security, parallel advanced encryption standard with cipher block chaining (PAES‐CBC) algorithm is proposed. Aggregated ciphertext is transmitted to optimal switch in the second tier by using fuzzy weighted technique for order preference by similarity to ideal solution (FW‐TOPSIS) algorithm according to selection criteria. Switches forward the data to sink node based on flow rules deployed by SDN controllers in the third tier. SDN controllers provide global view on the entire network and deploy flow rules on switches in accordance to network status and security level. Extensive simulation in ns‐3 shows that the proposed three‐tier architecture achieves 5% throughput improvement, 7.8% PDR improvement, and 16% energy consumption improvement. [ABSTRACT FROM AUTHOR]

The article offers information on a deep learning (DL)-assisted and combined side-channel attack (SCA) method produced by the researchers from the Old Dominion University and the University of Minnesota Twin Cities for improving the cryptographic circuit secret key of an advanced encryption standard (AES) efficiencies. It mentions about the use of cryptographic circuits for encrypting processors and Internet of Things (IoT) devices.