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The choice of the ideal material employed in selector devices is a tough task both from the theoretical and experimental side, especially due to the lack of a synergistic approach between techniques able to correlate specific material properties with device characteristics. Using a material‐to‐device multiscale technique, a reliable protocol for an efficient characterization of the active traps in amorphous GeSe chalcogenide is proposed. The resulting trap maps trace back the specific features of materials responsible for the measured findings, and connect them to an atomistic description of the sample. The metrological approach can be straightforwardly extended to other materials and devices, which is very beneficial for an efficient material‐device codesign and the optimization of novel technologies. [ABSTRACT FROM AUTHOR]

In this study, the radiation effects of electron beam (e‐beam) on field‐effect transistors (FETs) using transition‐metal dichalcogenides (TMD) as a channel are carefully investigated. Electron‐hole pairs (EHPs) in SiO2 generated by e‐beam irradiation induce additional traps, which change the surface potential of the TMD channel, resulting in strong negative shifts of transfer characteristics. These negative shifts, which remind one of n‐doping effects, are highly affected not only by the condition of e‐beam irradiation, but also by the gate bias condition during irradiating. As a result of the e‐beam irradiation effect, band bending and contact resistance are affected, and the degree of formation of oxide traps and interface traps varies depending on the gate bias conditions. In the case of VG > 0 V application during e‐beam irradiation, the negative shifts in the transfer characteristics are fully recovered after ambient exposure. However, the interface traps increase significantly, resulting in variations of low‐frequency (LF) noise and time‐dependent current fluctuations. [ABSTRACT FROM AUTHOR]

Field‐effect transistors (FETs), using transition metal dichalcogenides (TMD) as channels, have various types of interfaces, and their characteristics are sensitively changed in temperature and electrical stress. In this article, the effect of fast cyclic thermal stress on the performance of FETs using TMD as a channel is investigated and introduced. The Al2O3 passivation layer is deposited onto the TMD channel by atomic layer deposition process, and the hysteresis decreases and the direction changes from clockwise to counterclockwise. Applying cyclic thermal stress that rapidly heats and cools by 90 K in a 20 s cycle increases and decreases drain current repeatedly as charges move between the TMD channel and the interface traps. As cyclic thermal stress is applied, permanent interfacial damage occurs, resulting in increased interface trap density at the bottom and decreased hysteresis. These experimental results are also shown through technology computer‐aided design simulations. In addition, series resistance and mobility attenuation factor increase due to the concentration of the conduction paths at the bottom of the channel. [ABSTRACT FROM AUTHOR]

In this study, high‐performance few‐layered ReS2 field‐effect transistors (FETs), fabricated with hexagonal boron nitride (h‐BN) as top/bottom dual gate dielectrics, are presented. The performance of h‐BN dual gated ReS2 FET having a trade‐off of performance parameters is optimized using a compact model from analytical choice maps, which consists of three regions with different electrical characteristics. The bottom h‐BN dielectric has almost no defects and provides a physical distance between the traps in the SiO2 and the carriers in the ReS2 channel. Using a compact analyzing model and structural advantages, an excellent and optimized performance is introduced consisting of h‐BN dual‐gated ReS2 with a high mobility of 46.1 cm2 V−1 s−1, a high current on/off ratio of ≈106, a subthreshold swing of 2.7 V dec−1, and a low effective interface trap density (Nt,eff) of 7.85 × 1010 cm−2 eV−1 at a small operating voltage (<3 V). These phenomena are demonstrated through not only a fundamental current–voltage analysis, but also technology computer aided design simulations, time‐dependent current, and low‐frequency noise analysis. In addition, a simple method is introduced to extract the interlayer resistance of ReS2 channel through Y‐function method as a function of constant top gate bias. [ABSTRACT FROM AUTHOR]

Metal-insulator-metal capacitors (MIMCAP) with stoichiometric SrTiO3 dielectric were deposited stacking two strontium titanate (STO) layers, followed by intermixing the grain determining Sr-rich STO seed layer, with the Ti-rich STO top layer. The resulted stoichiometric SrTiO3 would have a structure with less defects as demonstrated by internal photoemission experiments. Consequently, the leakage current density is lower compared to Sr-rich STO which allow further equivalent oxide thickness downscaling. [ABSTRACT FROM AUTHOR]