Search

Detection of vector magnetic fields at nanoscale dimensions is critical in applications ranging from basic material science and fundamental physics to information storage and medical diagnostics. So far, nanoscale vector magnetic field sensing is achieved solely by exploiting a single nitrogen‐vacancy (NV) center in a diamond, by evaluating the Zeeman splitting of NV spin qubits by using the technique of an optically‐detected magnetic resonance. This protocol requires a complex optical setup and expensive detection systems to detect the photoluminescence light, which may limit miniaturization and scalability. Here, a simple approach with all‐electric operation to sensing a vector magnetic field at 200 × 200 nm2 dimensions is experimentally demonstrated, by monitoring a stochastic nanomagnet's transition probability from a metastable state, excited by a driving current due to spin‐orbit torque, to a settled state. [ABSTRACT FROM AUTHOR]

Summary: A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2. [ABSTRACT FROM AUTHOR]

Analog arithmetic operations are the most fundamental mathematical operations used in image and signal processing as well as artificial intelligence (AI). In‐memory computing (IMC) offers a high performance and energy‐efficient computing paradigm. To date, in‐memory analog arithmetic operations with emerging nonvolatile devices are usually implemented using discrete components, which limits the scalability and blocks large scale integration. Here, a prototypical implementation of in‐memory analog arithmetic operations (summation, subtraction and multiplication) is experimentally demonstrated, based on in‐memory electrical current sensing units using spin‐orbit torque (SOT) devices. The proposed structures for analog arithmetic operations are smaller than the state‐of‐the‐art complementary metal oxide semiconductor (CMOS) counterparts by several orders of magnitude. Moreover, data to be processed and computing results can be locally stored, or the analog computing can be done in the nonvolatile SOT devices, which are exploited to experimentally implement the image edge detection and signal amplitude modulation with a simple structure. Furthermore, an artificial neural network (ANN) with SOT devices based synapses is constructed to realize pattern recognition with high accuracy of ≈95%. [ABSTRACT FROM AUTHOR]

A wideband low‐phase noise VCO is proposed for multi‐standard wireless communication system. An 8‐shaped high‐Q inductor is employed to enhance the performance of the VCO. The frequency pulling is reduced by using the 8‐shaped coil. Implemented in a 180 nm CMOS process, the VCO can provide a very wide tuning range of 65.4% from 2.49 to 4.91 GHz. A phase noise lower than −121.25 dBc/Hz is obtained at 1 MHz offset over the whole working band while the current consumed varies from 3.5 to 8.7 mA. [ABSTRACT FROM AUTHOR]

A novel wideband down‐conversion mixer is proposed for multi‐standard wireless applications between 100 MHz and 2.5 GHz. A transconductance stage with two pairs of compensatory transistors is adopted for high linearity. Differing from the ordinary differential multi‐gated transistor technique utilised in Gilbert mixer, the design proposed concerns about both gm″ and gm compensation of the transconductance stage in order to improve both input‐referred third‐order intercept point (IIP3) and 1 dB gain compression point (CP1 dB). Realising in Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm RF CMOS process, the mixer provides a gain of 8.9 dB, a maximum IIP3 of 5.8 dBm, a maximum CP1 dB of −4 dBm and a minimum noise figure (NF) of 9.6 dB. [ABSTRACT FROM AUTHOR]

A high‐linearity CMOS power amplifier (PA) operating at 2.4 GHz with an integrated diode lineariser is presented. A diode‐connected N‐type MOS transistor is used to increase the Vgs of the power transistor as input power increases for linearity improvement. The CMOS PA fabricated in 180 nm CMOS technology achieved 32 dB small signal gain, 30.2 dBm Psat, 28.2 dBm P1 dB, and a 31.1% peak power added efficiency. By adopting the proposed diode lineariser, the output 1 dB is improved from 24.9 to 28.2 dBm. [ABSTRACT FROM AUTHOR]

A wideband voltage‐controlled oscillator (VCO) covering 2.24–4.95 GHz for multi‐standard wireless applications is presented. Realised in TSMC 180 nm RFCMOS process, the VCO provides a phase noise <–124.2 dBc/Hz at a 1 MHz offset in the whole frequency range, while drawing 10 and 18 mA at 4.95and 2.24 GHz from a 1.8 V supply, respectively. The achieved tuning range is 75% and the core chip area is 0.51 mm². [ABSTRACT FROM AUTHOR]

A wideband single‐ended input, differential output balun‐LNA is proposed for multi‐standard wireless applications between 10 MHz and 3 GHz. The common‐gate (CG) input stage in combination with a noise cancellation topology is adopted for wideband input matching and low‐noise figure. An output stage with gm″ compensation technique is utilised to promote the limited gain of the CG input stage, and obtain an optimised linearity performance. Realised in TSMC 180 nm RF CMOS process, the LNA provides a gain of 19.7 dB, a maximum input third‐order interception point of 1.13 dBm, and a minimum NF AQ1 of 1.93 dB over a 3 dB bandwidth from 10 MHz to 1.7 GHz. Meanwhile, the proposed LNA shows good measured performance over the frequency band of 1.7–3 GHz. [ABSTRACT FROM AUTHOR]

An enhanced electrostatic discharge (ESD) power clamp for an antenna switch controller with silicon‐on‐insulator (SOI) complementary metal‐oxide‐semiconductor (CMOS) technology is presented. The gate drive voltages of larger n‐type metal‐oxide‐semiconductor transistors in a stacked configuration of a RC‐triggered power clamp have been optimised to obtain larger discharging capability and shorter turn‐on time compared to the conventional topology. The proposed ESD power clamp circuits are implemented in a double‐pole five‐throw antenna switch controller and the experimental results confirm the validity of this approach. [ABSTRACT FROM AUTHOR]