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This paper provides a comprehensive review of various error compensation techniques for fixed-width multiplier design along with its applications. In this paper, we have studied different error compensation circuits and their complexities in the fixed-width multipliers. Further, we present the experimental results of error metrics, including normalized maximum absolute error , normalized mean error and normalized mean-square error to evaluate the accuracy of fixed-width multipliers. This survey is intended to serve as a suitable guideline and reference for future work in fixed-width multiplier design and its related research. [ABSTRACT FROM AUTHOR]

The soft set theory proposed by D. Molodtsov in 1999 is a general mathematical method for dealing with uncertain data. Now many researchers are applying soft set theory in decision making problems. Graph theory is the mathematical study of objects and their pairwise relationships, known as vertices and edges, respectively. The concept of soft graphs is used to provide a parameterized point of view for graphs. Directed graphs can be used to analyze and resolve problems with electrical circuits, project timelines, shortest routes, social links and many other issues. We introduced the notion of the soft directed graph by applying the concepts of soft set in a directed graph. In this paper, we introduce the concept of soft subdigraph and some soft directed graph operations like AND operation, OR operation, soft union, extended union, extended intersection, restricted union and restricted intersection and investigate some of their properties. [ABSTRACT FROM AUTHOR]

D. Molodtsov proposed soft set theory in 1999 as a general mathematical framework for dealing with uncertain data. Many academics are now applying soft set theory in decision-making problems. In graph theory, a directed graph is a graph made up of vertices connected by directed edges, also known as arcs. Electrical circuits, shortest routes, social links and a variety of other problems can all be analyzed and solved using directed graphs. In this paper, we introduce soft directed graphs by applying the concept of soft set to directed graphs. Soft directed graphs provide a parameterized point of view for directed graphs. We define and investigate the degrees and matrices associated with a soft directed graph. We also introduce several product operations in soft directed graphs and analyze some of their features. [ABSTRACT FROM AUTHOR]

The work presented in this paper concerns the design of an on-chip GaN transformer. The integrated transformer is composed of two planar stacked coils with spiral octagonal geometry. A comparison is done on different analytical methods to calculate the inductance of the transformer spiral planar coils. Three transformers with different outer diameters are compared to illustrate the influence of the coil geometry. The estimated inductance and dc series resistance are evaluated. Using COMSOL Multiphysics 5.3 software, the thermal effect is illustrated in the integrated transformer operating at high frequencies. The different parasitic effects created by the planar stacked layers are validated by the equivalent electrical circuit, and the different electrical parameters are calculated. [ABSTRACT FROM AUTHOR]

Extreme multistable systems can show vibrant dynamical properties and infinitely many coexisting attractors generated by changing the initial conditions while the system and its parameters remain unchanged. On the other hand, the frequency of extreme events in society is increasing which could have a catastrophic influence on human life worldwide. Thus, complex systems that can model such behaviors are very significant in order to avoid or control various extreme events. Also, hidden attractors are a crucial issue in nonlinear dynamics since they cannot be located and recognized with conventional methods. Hence, finding such systems is a vital task. This paper proposes a novel five-dimensional autonomous chaotic system with a line of equilibria, which generates hidden attractors. Furthermore, this system can exhibit extreme multistability and extreme events simultaneously. The fascinating features of this system are examined by dynamical analysis tools such as Poincaré sections, connecting curves, bifurcation diagrams, Lyapunov exponents spectra, and attraction basins. Moreover, the reliability of the introduced system is confirmed through analog electrical circuit design so that this chaotic circuit can be employed in many engineering fields. [ABSTRACT FROM AUTHOR]

This paper introduces a new 3D conservative chaotic system. The oscillator preserves the energy over time, according to the Kaplan–Yorke dimension computation. It has a line of unstable equilibrium points that are investigated with the help of eigenvalues and also numerical analysis. The bifurcation diagrams and the corresponding Lyapunov exponents show various behaviors, for example, chaos, limit cycle, and torus with different parameters. Other dynamical properties, such as Poincaré section and basin of attraction, are investigated. Additionally, an oscillator's electrical circuit is designed and implemented to demonstrate its potentiality. [ABSTRACT FROM AUTHOR]

2R-1C equivalent circuit is widely used in electrochemical impedance spectroscopy (EIS), such as modelling of lithium-ion batteries, bioimpedance analysis and water quality monitoring. It allows for an analysis of the basic electrical behavior of electrochemical systems and understanding of the underlying principles. However, the reported parameter estimation methods are usually deployed on the PC-based processing units that limit in-situ and unsupervised applications, where estimation results are free from user inputs. This paper presents a novel methodology for extracting the values of 2R-1C equivalent circuit by solely utilizing the measured impedance modulus. Unlike iterative and PC-based estimation methods, this approach eliminates user inputs in terms of a need for an initial guess, addressing a significant drawback of those approaches. The proposed work was validated by simulated and experimentally obtained impedance. Moreover, details of deployment on the PC-based and embedded hardware were also reported. The utilization of embedded hardware platform (Mega2560) enables an efficient processing of EIS data (80 milliseconds for 100 datapoints) by creating opportunities for in-situ parameter extraction of equivalent electrical circuits. [ABSTRACT FROM AUTHOR]

This paper presents a low-power low-noise instrumentation amplifier (IA) for bio-potential recording. The proposed IA is based on a novel Gm-RSC structure, whose gain is determined by the transconductance (Gm) and the equivalent resistance (R) of the switched-capacitor (SC) load. The transconductance amplifier stage is based on the current-reuse telescope topology to achieve low noise at low-power dissipation. A resistor-controlled oscillator is designed to generate desirable operational frequency for SC load and to continuously tune the mid-band gain of the IA for different biomedical applications. Measurement results show that the input referred noise of the proposed IA is about 1.27μVRMS (BW=150Hz) and the noise efficiency factor is 3.3. The range of tunable gain is from 28 to 40dB. The common mode rejection ratio and power supply rejection ratio at 50Hz are 72 and 78dB, respectively. The IA consumes only 660nA current at 1.2V supply and the active area of the IA is only 0.035mm2. [ABSTRACT FROM AUTHOR]

Quantum-dot Cellular Automata (QCA) presents a new model at Nano-scale for possible substitution of conventional Complementary Metal–Oxide–Semiconductor (CMOS) technology. On the other hand, an Arithmetic Logic Unit (ALU) is a digital electronic circuit which performs arithmetic and bitwise logical operations on integer binary numbers. Therefore, QCA-based ALU is an important part of the processor in order to develop a full capability processor. Although the QCA has become very important, there is not any comprehensive and systematic work on studying and analyzing its important techniques in the field of ALU design. This paper provides the comprehensive, systematic and detailed study and survey of the state-of-the-art techniques and mechanisms in the field of QCA-based ALU designing. There are three categories in which QCA plays a role: ALU, logic unit (LU) and arithmetic unit (AU). Each category presents the important studies. In addition, this paper reviews the major developments in these three categories and it plans the new challenges. Furthermore, it provides the identification of open issues and guidelines for future research. Also, a Systematic Literature Review (SLR) on QCA-based ALU, LU and AU is discussed in this paper. We identified 1,960 papers, which are reduced to 26 primary studies through our paper selection process. According to the obtained results from 2001 to 2015, the number of published articles are very high in 2014 and low in 2005 and 2009. This survey paper also provides a discussion of considered mechanisms in terms of ALU, LU and AU attribute as well as directions for future research. [ABSTRACT FROM AUTHOR]

The local fractional derivative (LFD) has gained much interest recently in the field of electrical circuits. This paper proposes a non-differentiable (ND) model of high-pass filter described by the LFD, where the ND transfer function is obtained with the help of the local fractional Laplace transform, and its parameters and properties are studied. The obtained results reveal the sufficiency of the LFD for analyzing circuit systems in fractal space. [ABSTRACT FROM AUTHOR]

In this paper, one-dimensional time fractional telegraph equation is deduced using fractional Ohm's law in transmission lines. The nonlocal behavior, arising from the time fractality, is discussed via fractional calculus. Here, the time fractional differential equation related to electrical GLRC circuit is proposed in terms of the Liouville–Caputo fractional derivative. To keep the dimensionality of the physical parameters L , C the new parameter σ is introduced. This parameter (σ) characterizes the existence of fractional structure in the system. The analytical solution of the proposed equation is obtained by using Laplace transform method in terms of Mittag-Leffler function which describes physical system with memory. The order of the time derivative being considered is 0 < α ≤ 1. The result of an example shows that the behavior of voltage depends on the value of the fractional order of the proposed equation. [ABSTRACT FROM AUTHOR]

Two new minimum passive component oscillators using inverting current conveyor (ICCII-) acting as a voltage negative impedance converter are generated from the Sallen Key low-pass and high-pass filters. It is also shown that the Sallen Key low-pass, high-pass, and band-pass filters are the origin of the three minimum component oscillators using the current conveyor acting as a current negative impedance converter. In addition, it is also shown that the Sallen Key high-pass and band-pass filters are the origin of the two minimum component oscillators using single input single output transconductance amplifier as the active element. Although this paper is considered partially a review paper it includes new generation methods and new minimum component oscillator circuit realizations. Simulation results for the new oscillators using ICCII- are included. [ABSTRACT FROM AUTHOR]

Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. This nanoelectronic is based on the mapping of binary logic in the two excess electrons configuration within a four-dot cell. In this paper, we propose a new ultra-low energy and low-complexity two-input XOR gate which can be employed as a basic component in designing a wide range of QCA logical circuits. For performance evaluation of the presented design in a large array of QCA structures, even parity generator circuit with different lengths up to 32 bits as well as LFSR circuit are designed and analyzed as instances of logical circuits. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from hardware implementation requirements and energy consumption aspects. QCADesigner tool is utilized to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool. [ABSTRACT FROM AUTHOR]

The ion migration memristor is a nonlinear element with memory function and nanoscale size, it is considered as a potential candidate to reduce system power consumption and circuit size. When it works as the nonlinear part of the chaotic system, rich nonlinear curves will be produced, and at the same time, the complexity of chaotic systems and the randomness of signals will be enhanced. So in this paper, by Matlab numerical simulation, a new double-wing chaotic system based on an ion migration memristor is designed. In reality, there are many systems interfered inevitably by random noise, so in this paper the random bounded noises are also considered. The power spectrum, Lyapunov exponent spectrum, Poincaré map and bifurcation diagram are used to investigate its complex dynamic characteristics. Then, a SPICE-based analog circuit is presented to verify the feasibility of the system, for which the simulation results are consistent with the numerical simulation. Finally, the sliding mode variable structure control is applied to overcome the shortcomings of traditional control method, so that the chaotic orbits can be controlled to any fixed points or periodic orbits, and this provides an insight into chaos control in power electronics systems. [ABSTRACT FROM AUTHOR]

Reversible logic has been recently considered as an interesting and important issue in designing combinational and sequential circuits. The combination of reversible logic and multi-valued logic can improve power dissipation, time and space utilization rate of designed circuits. Only few works have been reported about sequential reversible circuits and almost there are no paper exhibited about quantum ternary reversible counter. In this paper, first we designed 2-qutrit and 3-qutrit quantum reversible ternary up-counters using quantum ternary reversible T-flip-flop and quantum reversible ternary gates. Then we proposed generalized quantum reversible ternary n-qutrit up-counter. We also introduced a new approach for designing any type of n-qutrit ternary and reversible counter. According to the results, we can conclude that applying second approach quantum reversible ternary up-counter is better than the others. [ABSTRACT FROM AUTHOR]

In 2003, a digitally controlled oscillator (DCO) for cellular mobile phones was first proposed and demonstrated, and after that DCOs are widely used along with the rapid development of wireless communications. DCOs based on LC structure gain an advantage over ring oscillators in phase noise and thereby become research hotspot during the last decade. This paper presents a review of inductance capacitance (LC)-DCOs classified by circuit topologies and performance. For each DCO structure, the principle exposition and performance analysis are given in detail. Moreover, a comparison among all kinds of DCOs mentioned in this paper is presented in tabular form. Finally, we discuss the obstacle to the development of DCOs and the possible tendency for future work in summary. [ABSTRACT FROM AUTHOR]

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding "0011" to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%. [ABSTRACT FROM AUTHOR]

This paper exposes circuit design of linear congruential generator (LCG) and implementation in FPGA based on block reduction technique. The circuit is derived from LCG algorithm proposed by Lehmer. Block reduction technique has been used to simplify the circuit. Several net connections among the blocks of the circuit are ignored or disconnected and the multiplier is replaced by a shifter. Simulations of both behavior and timing have been done and the results confirm its algorithm. The Cyclone II EP2C8Q208C8N and Cyclone IV E EP4CE115F29C7N of Altera have been chosen to extract comparison data of speed and occupied area. Further comparison of shift technique and the wordlengths reduction technique has been made. In general, the proposed design is far simpler than the previous published LCG circuit. [ABSTRACT FROM AUTHOR]

As reported in the existing literature, wing attractors are confined to 1D -wing attractors, 2D -grid wing attractors. In this paper, we break this limitation and generate 3D -grid multi-wing chaotic attractors (GMWCAs). The 3D GMWCAs are produced via the following three steps: (1) applying rotation transformation to a double-wing Lorenz-like system to ensure that its saddle-focus equilibria with index 2 are located on the plane ; (2) extending the wing attractors of the transformed Lorenz-like system along the -axis to have mirror symmetry; (3) introducing stair switching functions to increase the number of saddle-focus equilibria with index 2 along the -axis and -axis. Furthermore, some basic dynamical properties of the 3D chaotic system, including equilibria, symmetry, dissipativity, Lyapunov exponents and bifurcation diagram, are investigated and a module-based unified circuit diagram is designed. The effectiveness of this approach is confirmed by both numerical simulations and electrical circuit experiment. [ABSTRACT FROM AUTHOR]

A proposal of a fractional ()-order low-pass filter is presented in this paper. The proposed filter operates in the current-mode and it is designed using Multi-Output Current Followers (MO-CFs), Dual-Output Current Follower (DO-CF), Dual-Output Adjustable Current Amplifier (DO-ACA) and Adjustable Current Amplifiers (ACAs) as active elements within the presented topology of the filter. The filter possesses ability to electronically control its order and also the pole frequency by changing the current gain of current amplifiers (ACAs) already present in the structure. Three different values of the order and pole frequency of the proposed low-pass filter were tested as an example. Design of the proposed filter is supported by simulation and experimental results. Simulations of the circuit are carried out in PSPICE simulator with behavioral models of used active elements. The experimental laboratory measurements are performed with the help of available devices forming equivalent circuits. Simulations and experimental results of the electronical control of the order and pole frequency are compared in this contribution. [ABSTRACT FROM AUTHOR]

In this paper, we construct a discrete nonlocal integrable lattice hierarchy related to a reverse space-time nonlocal nonlinear self-dual network equation which may have the potential applications in designing nonlocal electrical circuits and understanding the propagation of electrical signals. By means of nonlocal version of N -fold Darboux transformation (DT) technique, discrete multi-soliton solutions in determinant form are constructed for the reverse space-time nonlocal nonlinear self-dual network equation. Through the asymptotic and graphic analysis, unstable soliton structures of one-, two- and three-soliton solutions are discussed graphically. We observe that the single components in this nonlocal equation display instability while the combined potential terms with nonlocal P T -symmetry show stable soliton structures. It is shown that these nonlocal solutions are clearly different from those of its corresponding local equation. The results given in this paper may explain the soliton propagation in electrical signals. [ABSTRACT FROM AUTHOR]

This paper proposes an output-capacitorless low-dropout (LDO) regulator with ultra-low quiescent power. It applies an adaptive error amplifier to improve the bandwidth and transient response during heavy load, and a second gain stage to improve the stability during light load. Furthermore, an overshoot and undershoot reduction circuit is used to shorten the settling time when output load is changed. The LDO is fabricated in 0.18m CMOS process and occupies a chip area of 0.06mm2. The LDO is measured to output a stable voltage at 1.6V with a quiescent power of 1.8W. The experimental results also show a good transient response. [ABSTRACT FROM AUTHOR]

A fully-integrated self-startup circuit with ultra-low voltage for thermal energy harvesting is presented in this paper. The converter is composed of an enhanced swing LC oscillator and a charge pump with decreased equivalent input capacitance. The LC oscillator has ultra-low input voltage and high output voltage swing, and the charge pump has a fast charging speed and small equivalent input capacitance. This circuit is designed with 0.18m standard CMOS process. The simulation results show that the output voltage is in the range of 0.14V and 2.97V when the input voltage is changed from 50mV to 150mV. The output voltage could reach 2.87V at the input voltage of 150mV and the load of 1M. The maximum efficiency is in the range of 10.0% and 14.8% when the input voltage is changed from 0.2V to 0.4V. The circuit is suitable for thermoelectric energy harvesting to start with ultra-low input voltage. [ABSTRACT FROM AUTHOR]

In this paper, a switched resistor slicer is proposed to reduce the power consumption of a decision feedback equalizer (DFE). In the proposed structure, summer circuit that consumes most of the power in a DFE has been eliminated and proper resistors are added as the load of a slicer based on a flip-flop output bit stream. Incorporating the proposed DFE circuit with continuous time linear equalizer (CTLE) at the serial link receiver over a 1m NELCO (the NELCO N4000-13 series is an enhanced epoxy resin system engineered to provide both outstanding thermal and high signal speed/low signal loss properties) channel can compensate 24dB loss at the Nyquist frequency of 2GHz. CTLE is adjusted to compensate 6dB of channel loss which remains after utilizing a DFE with three taps. The proposed structure has been designed in 0.18m CMOS technology while consuming 13.5mW from 1.8V supply at 4Gb/s with a bit error rate less than 10. The proposed equalizer power consumption is reduced by 43% compared to the conventional circuit. [ABSTRACT FROM AUTHOR]

In this paper, a CMOS resistor-based current mirror (RBCM) aimed to be used in low-voltage applications is presented. The main features of the proposed current mirror are very low input voltage requirement (a few mV), low output voltage requirement, high output impedance and simple circuitry. The core structure of the proposed RBCM consists of three transistors (excluding bias circuitry) and two low value grounded resistors. The proposed circuit alleviates the need for cascode structures which are conventionally used to boost the output impedance and linearity. SPICE simulations using 0.18m CMOS technology parameters under supply voltage of 0.9V are reported which show input and output voltage requirements of 40mV and 0.1V respectively, low THD of 1.2%, of 496, of 1M, 3dB bandwidth of 181MHz and power dissipation of 154W. A high CMRR differential amplifier and a high performance current difference circuit as applications of the proposed RBCM are given. The proposed RBCM is very useful in tackling restrictions of modern technologies such as reduced supply voltage and transistors low intrinsic output impedance. [ABSTRACT FROM AUTHOR]

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6mW under a 0.8V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04GHz as the tuning voltage is varied from 0.8 to 0.0V. The phase noise is 118.3dBc/Hz at 1MHz offset frequency from the carrier frequency of 2.36GHz and the corresponding figure-of-merit of the QVCO is 183.7dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper describes an analysis of multi-stage and multi-rate IIR switched capacitor (SC) decimators using an interactive switched capacitor multi-rate compiler (ISCMRATE). Motivated by the experimental observations, the purpose of this paper is to explore a portion of characteristics for the multi-stage IIR SC decimators, with their implications in the context of a complete IIR SC filter. To overcome the limitations of conventional multi-stage IIR SC decimators, a novel solution has been introduced for the implementation of a multi-stage IIR SC circuit. Based on the statistical approach of the compiler, we provide the comparative analysis for different IIR SC decimators, including total capacitor area, capacitance spread and arbitrary anti-aliasing amplitude responses with a decimating factor in single and multi-stage building blocks. Examples are given to illustrate the practical feasibility of this compiler. [ABSTRACT FROM AUTHOR]

In this paper, we present a low-voltage tunable active filter for microwave applications. The proposed filter is based on a single-transistor active inductor (AI), that allows the reduction of circuit area and power consumption. The three active-cell bandpass filter has a 1950 MHz center frequency with a -1 dB flat bandwidth of 10 MHz (Q ̃ 200), a shape factor (30-3 dB) of 2.5, and can be timed in the range 1800-2050 MHz, with constant insertion loss. A dynamic range of about 75 dB is obtained, with a PldB compression point of --5dBm. The prototype board, fabricated on a TLX-8 substrate, has a 4mW power consumption with a 1.2 V power supply voltage. [ABSTRACT FROM AUTHOR]

A digital communication channel must have linear-phase characteristic such that the transmitted signal will keep its waveform unchanged after the signal transmission. However, since the actual communication channels usually possess nonlinear phase, it is necessary to connect a phase-linearizing circuit (phase-circuit) to such a nonlinear phase channel for linearizing the whole phase characteristic. In this paper, we propose a new iterative optimization scheme that utilizes the second-order-cone-programming (SOCP) for designing a high-accuracy phase-circuit. By approximating the highly nonlinear design constraint as a second-order-cone (SOC) constraint, a phase-circuit can be successfully designed through iterating the SOCP scheme. As compared to other existing linear-programming (LP) design and SOCP design, this new iterative SOCP-based minimax design can further reduce the peak errors of the frequency response and phase response of the designed phase-circuit. As a consequence, the new design method can further improve the phase-circuit design accuracy. We will utilize two design examples to verify the performance improvements over other existing design techniques. [ABSTRACT FROM AUTHOR]

The concept of using special electrical circuit design to realize "cold resistors", i.e., an active resistor circuitry with lower effective noise temperature, was first introduced about 80 years ago. Later on, various kinds of artificial resistors were applied in different research areas, such as gravitational wave detection, photo-amplifiers and quartz oscillators. Their proofs of concepts were experimentally proved. Unfortunately, the complete theory was not found even though several attempts had been published, sometimes with errors. In this paper, we describe a correct and complete circuit theoretical model of a cold resistor system. The results are confirmed by computer simulations. A design tool for this circuit is also shown. [ABSTRACT FROM AUTHOR]

This paper initially presents a modified T-T filter with high and derives two nodal admittance matrix (NAM) of the filter. Next, in accordance with the nullor-mirror models of the CCCII, 32 different forms of the Tow-Thomas (T-T) filter using various types of the CCCII are synthesized by bracket notation method. One of the synthesized circuits is analyzed to support the generation method. [ABSTRACT FROM AUTHOR]

This paper aims to design an all-digital phase-locked loop (ADPLL) intended for professional digital audio data conversion applications. The method used for designing is based on an analogy between analog PLL and ADPLL. Managing a low-jitter effect, a comparative study between discrete voltage-controlled oscillator (DVCO) and direct digital synthesis (DDS) based on a pseudorandom binary sequence (PRBS) generator is performed. The features of the design in this work are high-precision and low harmonic distortion DDS which is combined with ADPLL. For model-based design validation, a rapid register transfer level (RTL) with VHSIC hardware description language (VHDL) is practiced and the dynamic performance result indicates a significant improvement in total harmonic distortion (THD) (dB) and a better resolution of 18.97bits for audio applications based on the aid of phase dithering DDS enhancement circuit. [ABSTRACT FROM AUTHOR]

In this paper, a multipath fading compensator(MFC) has been introduced and demonstrated to reduce the signal distortion which arose due to Doppler effect, multipath propagation and self-interference for a multichannel uncoordinated code hopping direct sequence spread spectrum (UCH-DSSS) signaling in underwater communication. The bit error rate (BER) performance analysis of the proposed system obtained both analytically and using P-Spice circuit simulation model with and without jamming signal is presented. It is observed that the BER is independent of the frequencies (used in focused acoustic field (FAF) experiments FAF-06 and FAF-05) and is also less than those of the previous works. Oscilloscope traces indicate that the experimental waveform of the proposed four-channel UCH-DSSS transceiver is almost close to those obtained using P-Spice circuit simulation. The experimental values of BER measured by BER meter also matched well with the BER obtained theoretically. Noise margin and distortion performance also are analyzed from the eye pattern which shows that noise margin and distortion also are independent of frequencies (used in both FAF-06 and FAF-05) and the bandwidth of operation of FAF-06 is 5.5 times more than that of FAF-05. [ABSTRACT FROM AUTHOR]

This paper is aimed to report the consequences in the use of the well-known bootstrap technique in single-phase current-fed full-bridge resonant inverters (SPCFFBRIs) operating with and without reactive energy. Based on both simulations (using the PSPICE software) and experiments it is shown that this technique is not feasible for this type of inverters when the load is predominantly reactive. The bootstrap technique conveniently operates when the load is purely resistive or resonant. The unfeasibility in the use of the bootstrap technique with reactive or nonresonant loads comes from the fact that the load voltage is applied to the bootstrap capacitor and, consequently, to the gate of the floating MOSFET, producing an imminent damage both in the control circuit and in the floating MOSFET. Therefore, other alternatives for feeding the floated MOSFETs must be considered. [ABSTRACT FROM AUTHOR]

According to the terminal relations of the DO-OTA, eight nullor-mirror models for the DO-OTA are presented in this paper, Moreover, the NAME method for two different classes of T-T filters is considered. The class I filters, employing three SISO-OTAs, have 16 different forms, and the class II filters, employing one SISO-OTA and one DISO-OTA or one SIDO-OTA, have eight different forms. Due to use of canonic number of components, the circuits are easy to be integrated and their parameters can be tuned electronically through tuning bias currents of the OTAs. The MULTISIM simulation results have been included to verify the workability of the derived circuit. [ABSTRACT FROM AUTHOR]

Ferroresonance overvoltage and over-current can be restrained using nonlinear dynamics. However, the ferroresonance simplified model, which cannot reflect the huge ferroresonance circuit in the grid precisely and cannot satisfy real-time analysis, is adopted in the traditional nonlinear control method. Owing to these shortcomings, the strategy of controlling ferroresonance overvoltage based on voltage time series is proposed. Based on the voltage time series analysis methods, the ferroresonance system is identified using the best embedding dimension and the best time delay obtained from the phase space reconstruction. Afterward, the feedback controller is designed based on the platform of the identified model. Results show that fundamental, subharmonic and chaotic ferroresonance overvoltage can all be controlled using the method presented in this paper even without the system parameters and the accurate system model. Therefore, the control strategy is generally more applicable. [ABSTRACT FROM AUTHOR]

The objective of this paper is to discuss the opportunities of an advanced RFCMOS for millimeter-wave applications based on an assessment of figures of merits including relevant device information. This paper introduces the RF specifications for 45 nm CMOS node and present the evolution of RF-FOMs with gate downscaling over the previous generations. Especially, since 45 nm CMOS is the technology to be available in production, a particular focus on its RF performance for power and bandwidth is given. [ABSTRACT FROM AUTHOR]

In a recent paper the link between the Op Amp-based two integrator loop oscillators and current feedback operational amplifier (CFOA)-based oscillators is detected and clearly explained. It was found that one of the grounded capacitor two CFOA two integrator loop oscillators, however, was not related directly to any of the Op Amp oscillators. In this paper the origin of the two CFOA grounded capacitor oscillator is found to be the passive second-order low-pass filter. It is also found that the differential voltage current conveyor (DVCC) grounded passive element oscillator is generated from the same passive second-order low-pass filter. A new family of grounded capacitor oscillators using current conveyors (CCII) and inverting current conveyors (ICCII) which includes sixteen members is introduced. A second new family of grounded passive elements oscillators using CCII and ICCII which includes eight members is also introduced. A discussion and a comparison with some of the previously reported CCII oscillator circuits is also given at the end of the paper. [ABSTRACT FROM AUTHOR]

In this paper, eight new Frequency Dependent Negative Resistance (FDNR) circuits using two current conveyors or inverting current conveyors or a combination of the two types are introduced. The proposed circuits are canonic and they use two grounded capacitors and one floating resistor. The generation of grounded capacitor minimum passive component oscillators from the FDNR circuits is also considered. It is found that two of the recently reported attractive oscillators are among the family of the generated oscillator circuits. Additional six new oscillator circuits based on the FDNR circuits are introduced in this paper. Spice simulation results using technology: SCN 05 feature size 0.5 μm, MOSIS Vendor: AGILENT to demonstrate the practicality of the proposed oscillators are included. [ABSTRACT FROM AUTHOR]

This paper studied the time evolution of quantum state in a mesoscopic LC circuit with the coupling energy caused by mesoscopic capacitor acting as a tunnel junction. It indicates that the state of the junction evolves into the quantum superposition of two coherent states and, in the state, nonclassical squeezing properties of the circuit appear. It also indicates that the dynamic behavior of the current shows collapse and revival phenomenon. The research in the paper will be helpful to miniaturize integrate circuits and electric components. It will be also important for the utilization of mesoscopic circuits to evolve the quantum states, which work as information carriers. [ABSTRACT FROM AUTHOR]

In this paper, a new memristor is proposed, and then an emulator built from off-the-shelf solid state components imitating the behavior of the proposed memristor is presented. Multisim simulation and breadboard experiment are done on the emulator, exhibiting a pinched hysteresis loop in the voltage-current plane when the emulator is driven by a periodic excitation voltage. In addition, a new simple chaotic circuit is designed by using the proposed memristor and other circuit elements. It is exciting that this circuit with only a linear negative resistor, a capacitor, an inductor and a memristor can generate a chaotic attractor. The dynamical behaviors of the proposed chaotic system are analyzed by Lyapunov exponents, phase portraits and bifurcation diagrams. Finally, an electronic circuit is designed to implement the chaotic system. For the sake of simple circuit topology, the proposed chaotic circuit can be easily manufactured at low cost. [ABSTRACT FROM AUTHOR]

Reversible logic is one of the indispensable aspects of emerging technologies for reducing physical entropy gain, since reversible circuits do not lose information in the form of internal heat during computation. This paper aimed to initiate constructing parity preserving reversible circuits. A novel parity preserving reversible block, HB is presented. Then a new design of a cost-effective parity preserving reversible full adder/subtractor (PPFA/S) is proposed. Next, we suggested a new parity preserving binary to BCD converter. Finally, we proposed new realization of parity preserving reversible BCD adder. The proposed designs are cost-effective in terms of quantum cost and delay. All the scales are in the NANO-metric area. [ABSTRACT FROM AUTHOR]

No fault found (NFF) is a major threat in extremely dependable high-end process node integrated systems, in e.g., avionics. One category of NFFs is the intermittent resistive fault (IRF), often originating from bad (e.g., via- or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g., one month, while the duration of the defect can be as short as 50ns, thus to evoke and detect these faults is a huge scientific challenge. Two methods to detect short pulses induced by IRFs are proposed. To improve the task of maintenance of avionics and reduce the current high debugging costs, an on-chip data logging system with time stamp and stored environmental conditions is introduced. Finally, a hardware implementation of an IRF generator is presented. [ABSTRACT FROM AUTHOR]

Ternary quantum circuits play a significant role in future quantum computing technology because they have many advantages over binary quantum circuits. Subtraction is considered as being one of the key arithmetic operations; hence, subtractors are very essential for the construction of various computational units of quantum computers and other complex computational systems. In this paper, we have proposed the realization of a quantum reversible ternary half-subtractor circuit using a generalized ternary gate, a ternary Toffoli gate, and a ternary C2NOT gate. Based on the realization of the ternary half-subtractor, we proposed the realization of a ternary full-subtractor. [ABSTRACT FROM AUTHOR]

A direct divide-by-2/3 LC injection-locked frequency divider (ILFD) is presented in this paper. The proposed ILFD circuit is based on a CMOS LC tank oscillator coupled with an injection NMOS transistor in series with an inductor. Together with body-biased technique and current-reused topology, the locking range of the ILFD is improved and the power consumption is reduced. The circuit is implemented in a 0.18m standard RF CMOS process. At the incident power of 0dBm, the measured locking range of the divide-by-2 and divide-by-3 modes are from 5.37GHz to 7.68 (8.07GHz to 11.4GHz) GHz, and the core circuit without buffers consumes 3mW at the supply voltage of 1.5V. The chip only occupies without the pads and the buffers. [ABSTRACT FROM AUTHOR]

This paper focuses on applying fractal Julia sets to observe the topological properties related to the signs of the real and reactive electric powers. To perform this, different power combinations were used to represent the fractal diagrams with an algorithm that considers the mathematical model of Julia sets. The study considers three cases: the first study considers the change of real power when the reactive power is fixed; the second study deals with the change of the reactive power when the real power is fixed; and finally, the third study contemplates that both real and reactive powers change. Furthermore, the fractal diagrams of the power in the four quadrants of the complex plane are studied to identify the topological properties for each sign. A qualitative analysis of the diagrams helps identify that complex power loads present some fractal graphic patterns with respect to the signs considered in the different quadrants of the complex planes. The diagrams represented in the complex planes save a relation in the forms and structure with other points studied, concluding that the power is related to other figures in other quadrants. Thus, this result allows a new study of the behavior of power in an electrical circuit by showing a clear relation of the different fractal diagrams obtained by the Julia sets. [ABSTRACT FROM AUTHOR]

In this paper, we investigate energy variation of mesoscopic L-C electric circuit in external electromagnetic field (EMF) due to the energy flow of EMF, we consider this a diffusion process governed by the master equation for diffusion channel with the diffusion rate being determined by the energy flow of EMF. By using the entangled state representation and the method of integration within ordered product of operators we derive time evolution law of the initial density operator of the circuit and the energy variation formula. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel voltage-programmed pixel circuit with polysilicon thin–flim transistors (poly-Si TFTs) for active matrix organic light-emitting diode (AMOLED) displays, which consists of one programming transistor, one driving transistor, four switching transistors and two storage capacitors, respectively. Specifically, the proposed pixel circuit is able to not only efficiently compensate for the threshold variations of TFTs, but also largely suppresses the electrical degradations of the devices caused by the long-term electrical stress. Moreover, the mobility variation of the driving transistor can be compensated as well. The simulation has been performed by HSPICE, and results indicate that the average values of nonuniformities are, respectively, 7.3% as the threshold-voltage varies by ± 0. 5 V and 2.1%, as the mobility of the driving transistor varies by ± 2 0 %, both of which are much lower than that of the conventional two-transistor and one-capacitor (2T1C) pixel. Furthermore, since the OLED is reverse-biased during the nonemission phases, the lifetime of OLED will be extended naturally. As a consequence, the proposed pixel circuit can substantially improve the display performance. [ABSTRACT FROM AUTHOR]